1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_cper.h" 113 #include "amdgpu_xcp.h" 114 #include "amdgpu_seq64.h" 115 #include "amdgpu_reg_state.h" 116 #include "amdgpu_userqueue.h" 117 #include "amdgpu_eviction_fence.h" 118 #if defined(CONFIG_DRM_AMD_ISP) 119 #include "amdgpu_isp.h" 120 #endif 121 122 #define MAX_GPU_INSTANCE 64 123 124 #define GFX_SLICE_PERIOD_MS 250 125 126 struct amdgpu_gpu_instance { 127 struct amdgpu_device *adev; 128 int mgpu_fan_enabled; 129 }; 130 131 struct amdgpu_mgpu_info { 132 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 133 struct mutex mutex; 134 uint32_t num_gpu; 135 uint32_t num_dgpu; 136 uint32_t num_apu; 137 }; 138 139 enum amdgpu_ss { 140 AMDGPU_SS_DRV_LOAD, 141 AMDGPU_SS_DEV_D0, 142 AMDGPU_SS_DEV_D3, 143 AMDGPU_SS_DRV_UNLOAD 144 }; 145 146 struct amdgpu_hwip_reg_entry { 147 u32 hwip; 148 u32 inst; 149 u32 seg; 150 u32 reg_offset; 151 const char *reg_name; 152 }; 153 154 struct amdgpu_watchdog_timer { 155 bool timeout_fatal_disable; 156 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 157 }; 158 159 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 160 161 /* 162 * Modules parameters. 163 */ 164 extern int amdgpu_modeset; 165 extern unsigned int amdgpu_vram_limit; 166 extern int amdgpu_vis_vram_limit; 167 extern int amdgpu_gart_size; 168 extern int amdgpu_gtt_size; 169 extern int amdgpu_moverate; 170 extern int amdgpu_audio; 171 extern int amdgpu_disp_priority; 172 extern int amdgpu_hw_i2c; 173 extern int amdgpu_pcie_gen2; 174 extern int amdgpu_msi; 175 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 176 extern int amdgpu_dpm; 177 extern int amdgpu_fw_load_type; 178 extern int amdgpu_aspm; 179 extern int amdgpu_runtime_pm; 180 extern uint amdgpu_ip_block_mask; 181 extern int amdgpu_bapm; 182 extern int amdgpu_deep_color; 183 extern int amdgpu_vm_size; 184 extern int amdgpu_vm_block_size; 185 extern int amdgpu_vm_fragment_size; 186 extern int amdgpu_vm_fault_stop; 187 extern int amdgpu_vm_debug; 188 extern int amdgpu_vm_update_mode; 189 extern int amdgpu_exp_hw_support; 190 extern int amdgpu_dc; 191 extern int amdgpu_sched_jobs; 192 extern int amdgpu_sched_hw_submission; 193 extern uint amdgpu_pcie_gen_cap; 194 extern uint amdgpu_pcie_lane_cap; 195 extern u64 amdgpu_cg_mask; 196 extern uint amdgpu_pg_mask; 197 extern uint amdgpu_sdma_phase_quantum; 198 extern char *amdgpu_disable_cu; 199 extern char *amdgpu_virtual_display; 200 extern uint amdgpu_pp_feature_mask; 201 extern uint amdgpu_force_long_training; 202 extern int amdgpu_lbpw; 203 extern int amdgpu_compute_multipipe; 204 extern int amdgpu_gpu_recovery; 205 extern int amdgpu_emu_mode; 206 extern uint amdgpu_smu_memory_pool_size; 207 extern int amdgpu_smu_pptable_id; 208 extern uint amdgpu_dc_feature_mask; 209 extern uint amdgpu_freesync_vid_mode; 210 extern uint amdgpu_dc_debug_mask; 211 extern uint amdgpu_dc_visual_confirm; 212 extern int amdgpu_dm_abm_level; 213 extern int amdgpu_backlight; 214 extern int amdgpu_damage_clips; 215 extern struct amdgpu_mgpu_info mgpu_info; 216 extern int amdgpu_ras_enable; 217 extern uint amdgpu_ras_mask; 218 extern int amdgpu_bad_page_threshold; 219 extern bool amdgpu_ignore_bad_page_threshold; 220 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 221 extern int amdgpu_async_gfx_ring; 222 extern int amdgpu_mcbp; 223 extern int amdgpu_discovery; 224 extern int amdgpu_mes; 225 extern int amdgpu_mes_log_enable; 226 extern int amdgpu_mes_kiq; 227 extern int amdgpu_uni_mes; 228 extern int amdgpu_noretry; 229 extern int amdgpu_force_asic_type; 230 extern int amdgpu_smartshift_bias; 231 extern int amdgpu_use_xgmi_p2p; 232 extern int amdgpu_mtype_local; 233 extern int amdgpu_enforce_isolation; 234 #ifdef CONFIG_HSA_AMD 235 extern int sched_policy; 236 extern bool debug_evictions; 237 extern bool no_system_mem_limit; 238 extern int halt_if_hws_hang; 239 extern uint amdgpu_svm_default_granularity; 240 #else 241 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 242 static const bool __maybe_unused debug_evictions; /* = false */ 243 static const bool __maybe_unused no_system_mem_limit; 244 static const int __maybe_unused halt_if_hws_hang; 245 #endif 246 #ifdef CONFIG_HSA_AMD_P2P 247 extern bool pcie_p2p; 248 #endif 249 250 extern int amdgpu_tmz; 251 extern int amdgpu_reset_method; 252 253 #ifdef CONFIG_DRM_AMDGPU_SI 254 extern int amdgpu_si_support; 255 #endif 256 #ifdef CONFIG_DRM_AMDGPU_CIK 257 extern int amdgpu_cik_support; 258 #endif 259 extern int amdgpu_num_kcq; 260 261 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 262 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 263 extern int amdgpu_vcnfw_log; 264 extern int amdgpu_sg_display; 265 extern int amdgpu_umsch_mm; 266 extern int amdgpu_seamless; 267 extern int amdgpu_umsch_mm_fwlog; 268 269 extern int amdgpu_user_partt_mode; 270 extern int amdgpu_agp; 271 extern int amdgpu_rebar; 272 273 extern int amdgpu_wbrf; 274 extern int amdgpu_disable_kq; 275 276 #define AMDGPU_VM_MAX_NUM_CTX 4096 277 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 278 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 279 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 280 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 281 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 282 #define AMDGPUFB_CONN_LIMIT 4 283 #define AMDGPU_BIOS_NUM_SCRATCH 16 284 285 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 286 287 /* hard reset data */ 288 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 289 290 /* reset flags */ 291 #define AMDGPU_RESET_GFX (1 << 0) 292 #define AMDGPU_RESET_COMPUTE (1 << 1) 293 #define AMDGPU_RESET_DMA (1 << 2) 294 #define AMDGPU_RESET_CP (1 << 3) 295 #define AMDGPU_RESET_GRBM (1 << 4) 296 #define AMDGPU_RESET_DMA1 (1 << 5) 297 #define AMDGPU_RESET_RLC (1 << 6) 298 #define AMDGPU_RESET_SEM (1 << 7) 299 #define AMDGPU_RESET_IH (1 << 8) 300 #define AMDGPU_RESET_VMC (1 << 9) 301 #define AMDGPU_RESET_MC (1 << 10) 302 #define AMDGPU_RESET_DISPLAY (1 << 11) 303 #define AMDGPU_RESET_UVD (1 << 12) 304 #define AMDGPU_RESET_VCE (1 << 13) 305 #define AMDGPU_RESET_VCE1 (1 << 14) 306 307 /* reset mask */ 308 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 309 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 310 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 311 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 312 313 /* max cursor sizes (in pixels) */ 314 #define CIK_CURSOR_WIDTH 128 315 #define CIK_CURSOR_HEIGHT 128 316 317 /* smart shift bias level limits */ 318 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 319 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 320 321 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 322 #define AMDGPU_SWCTF_EXTRA_DELAY 50 323 324 struct amdgpu_xcp_mgr; 325 struct amdgpu_device; 326 struct amdgpu_irq_src; 327 struct amdgpu_fpriv; 328 struct amdgpu_bo_va_mapping; 329 struct kfd_vm_fault_info; 330 struct amdgpu_hive_info; 331 struct amdgpu_reset_context; 332 struct amdgpu_reset_control; 333 334 enum amdgpu_cp_irq { 335 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 336 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 345 346 AMDGPU_CP_IRQ_LAST 347 }; 348 349 enum amdgpu_thermal_irq { 350 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 351 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 352 353 AMDGPU_THERMAL_IRQ_LAST 354 }; 355 356 enum amdgpu_kiq_irq { 357 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 358 AMDGPU_CP_KIQ_IRQ_LAST 359 }; 360 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 361 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 362 #define MAX_KIQ_REG_TRY 1000 363 364 int amdgpu_device_ip_set_clockgating_state(void *dev, 365 enum amd_ip_block_type block_type, 366 enum amd_clockgating_state state); 367 int amdgpu_device_ip_set_powergating_state(void *dev, 368 enum amd_ip_block_type block_type, 369 enum amd_powergating_state state); 370 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 371 u64 *flags); 372 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 373 enum amd_ip_block_type block_type); 374 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 375 enum amd_ip_block_type block_type); 376 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 377 378 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 379 380 #define AMDGPU_MAX_IP_NUM 16 381 382 struct amdgpu_ip_block_status { 383 bool valid; 384 bool sw; 385 bool hw; 386 bool late_initialized; 387 bool hang; 388 }; 389 390 struct amdgpu_ip_block_version { 391 const enum amd_ip_block_type type; 392 const u32 major; 393 const u32 minor; 394 const u32 rev; 395 const struct amd_ip_funcs *funcs; 396 }; 397 398 struct amdgpu_ip_block { 399 struct amdgpu_ip_block_status status; 400 const struct amdgpu_ip_block_version *version; 401 struct amdgpu_device *adev; 402 }; 403 404 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 405 enum amd_ip_block_type type, 406 u32 major, u32 minor); 407 408 struct amdgpu_ip_block * 409 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 410 enum amd_ip_block_type type); 411 412 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 413 const struct amdgpu_ip_block_version *ip_block_version); 414 415 /* 416 * BIOS. 417 */ 418 bool amdgpu_get_bios(struct amdgpu_device *adev); 419 bool amdgpu_read_bios(struct amdgpu_device *adev); 420 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 421 u8 *bios, u32 length_bytes); 422 void amdgpu_bios_release(struct amdgpu_device *adev); 423 /* 424 * Clocks 425 */ 426 427 #define AMDGPU_MAX_PPLL 3 428 429 struct amdgpu_clock { 430 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 431 struct amdgpu_pll spll; 432 struct amdgpu_pll mpll; 433 /* 10 Khz units */ 434 uint32_t default_mclk; 435 uint32_t default_sclk; 436 uint32_t default_dispclk; 437 uint32_t current_dispclk; 438 uint32_t dp_extclk; 439 uint32_t max_pixel_clock; 440 }; 441 442 /* sub-allocation manager, it has to be protected by another lock. 443 * By conception this is an helper for other part of the driver 444 * like the indirect buffer or semaphore, which both have their 445 * locking. 446 * 447 * Principe is simple, we keep a list of sub allocation in offset 448 * order (first entry has offset == 0, last entry has the highest 449 * offset). 450 * 451 * When allocating new object we first check if there is room at 452 * the end total_size - (last_object_offset + last_object_size) >= 453 * alloc_size. If so we allocate new object there. 454 * 455 * When there is not enough room at the end, we start waiting for 456 * each sub object until we reach object_offset+object_size >= 457 * alloc_size, this object then become the sub object we return. 458 * 459 * Alignment can't be bigger than page size. 460 * 461 * Hole are not considered for allocation to keep things simple. 462 * Assumption is that there won't be hole (all object on same 463 * alignment). 464 */ 465 466 struct amdgpu_sa_manager { 467 struct drm_suballoc_manager base; 468 struct amdgpu_bo *bo; 469 uint64_t gpu_addr; 470 void *cpu_ptr; 471 }; 472 473 int amdgpu_fence_slab_init(void); 474 void amdgpu_fence_slab_fini(void); 475 476 /* 477 * IRQS. 478 */ 479 480 struct amdgpu_flip_work { 481 struct delayed_work flip_work; 482 struct work_struct unpin_work; 483 struct amdgpu_device *adev; 484 int crtc_id; 485 u32 target_vblank; 486 uint64_t base; 487 struct drm_pending_vblank_event *event; 488 struct amdgpu_bo *old_abo; 489 unsigned shared_count; 490 struct dma_fence **shared; 491 struct dma_fence_cb cb; 492 bool async; 493 }; 494 495 /* 496 * file private structure 497 */ 498 499 struct amdgpu_fpriv { 500 struct amdgpu_vm vm; 501 struct amdgpu_bo_va *prt_va; 502 struct amdgpu_bo_va *csa_va; 503 struct amdgpu_bo_va *seq64_va; 504 struct mutex bo_list_lock; 505 struct idr bo_list_handles; 506 struct amdgpu_ctx_mgr ctx_mgr; 507 struct amdgpu_userq_mgr userq_mgr; 508 509 /* Eviction fence infra */ 510 struct amdgpu_eviction_fence_mgr evf_mgr; 511 512 /** GPU partition selection */ 513 uint32_t xcp_id; 514 }; 515 516 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 517 518 /* 519 * Writeback 520 */ 521 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 522 523 struct amdgpu_wb { 524 struct amdgpu_bo *wb_obj; 525 volatile uint32_t *wb; 526 uint64_t gpu_addr; 527 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 528 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 529 spinlock_t lock; 530 }; 531 532 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 533 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 534 535 /* 536 * Benchmarking 537 */ 538 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 539 540 /* 541 * ASIC specific register table accessible by UMD 542 */ 543 struct amdgpu_allowed_register_entry { 544 uint32_t reg_offset; 545 bool grbm_indexed; 546 }; 547 548 /** 549 * enum amd_reset_method - Methods for resetting AMD GPU devices 550 * 551 * @AMD_RESET_METHOD_NONE: The device will not be reset. 552 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 553 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 554 * any device. 555 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 556 * individually. Suitable only for some discrete GPU, not 557 * available for all ASICs. 558 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 559 * are reset depends on the ASIC. Notably doesn't reset IPs 560 * shared with the CPU on APUs or the memory controllers (so 561 * VRAM is not lost). Not available on all ASICs. 562 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 563 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 564 * but without powering off the PCI bus. Suitable only for 565 * discrete GPUs. 566 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 567 * and does a secondary bus reset or FLR, depending on what the 568 * underlying hardware supports. 569 * 570 * Methods available for AMD GPU driver for resetting the device. Not all 571 * methods are suitable for every device. User can override the method using 572 * module parameter `reset_method`. 573 */ 574 enum amd_reset_method { 575 AMD_RESET_METHOD_NONE = -1, 576 AMD_RESET_METHOD_LEGACY = 0, 577 AMD_RESET_METHOD_MODE0, 578 AMD_RESET_METHOD_MODE1, 579 AMD_RESET_METHOD_MODE2, 580 AMD_RESET_METHOD_LINK, 581 AMD_RESET_METHOD_BACO, 582 AMD_RESET_METHOD_PCI, 583 AMD_RESET_METHOD_ON_INIT, 584 }; 585 586 struct amdgpu_video_codec_info { 587 u32 codec_type; 588 u32 max_width; 589 u32 max_height; 590 u32 max_pixels_per_frame; 591 u32 max_level; 592 }; 593 594 #define codec_info_build(type, width, height, level) \ 595 .codec_type = type,\ 596 .max_width = width,\ 597 .max_height = height,\ 598 .max_pixels_per_frame = height * width,\ 599 .max_level = level, 600 601 struct amdgpu_video_codecs { 602 const u32 codec_count; 603 const struct amdgpu_video_codec_info *codec_array; 604 }; 605 606 /* 607 * ASIC specific functions. 608 */ 609 struct amdgpu_asic_funcs { 610 bool (*read_disabled_bios)(struct amdgpu_device *adev); 611 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 612 u8 *bios, u32 length_bytes); 613 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 614 u32 sh_num, u32 reg_offset, u32 *value); 615 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 616 int (*reset)(struct amdgpu_device *adev); 617 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 618 /* get the reference clock */ 619 u32 (*get_xclk)(struct amdgpu_device *adev); 620 /* MM block clocks */ 621 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 622 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 623 /* static power management */ 624 int (*get_pcie_lanes)(struct amdgpu_device *adev); 625 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 626 /* get config memsize register */ 627 u32 (*get_config_memsize)(struct amdgpu_device *adev); 628 /* flush hdp write queue */ 629 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 630 /* invalidate hdp read cache */ 631 void (*invalidate_hdp)(struct amdgpu_device *adev, 632 struct amdgpu_ring *ring); 633 /* check if the asic needs a full reset of if soft reset will work */ 634 bool (*need_full_reset)(struct amdgpu_device *adev); 635 /* initialize doorbell layout for specific asic*/ 636 void (*init_doorbell_index)(struct amdgpu_device *adev); 637 /* PCIe bandwidth usage */ 638 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 639 uint64_t *count1); 640 /* do we need to reset the asic at init time (e.g., kexec) */ 641 bool (*need_reset_on_init)(struct amdgpu_device *adev); 642 /* PCIe replay counter */ 643 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 644 /* device supports BACO */ 645 int (*supports_baco)(struct amdgpu_device *adev); 646 /* pre asic_init quirks */ 647 void (*pre_asic_init)(struct amdgpu_device *adev); 648 /* enter/exit umd stable pstate */ 649 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 650 /* query video codecs */ 651 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 652 const struct amdgpu_video_codecs **codecs); 653 /* encode "> 32bits" smn addressing */ 654 u64 (*encode_ext_smn_addressing)(int ext_id); 655 656 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 657 enum amdgpu_reg_state reg_state, void *buf, 658 size_t max_size); 659 }; 660 661 /* 662 * IOCTL. 663 */ 664 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 667 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 668 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 669 struct drm_file *filp); 670 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 671 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 672 struct drm_file *filp); 673 674 /* VRAM scratch page for HDP bug, default vram page */ 675 struct amdgpu_mem_scratch { 676 struct amdgpu_bo *robj; 677 volatile uint32_t *ptr; 678 u64 gpu_addr; 679 }; 680 681 /* 682 * CGS 683 */ 684 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 685 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 686 687 /* 688 * Core structure, functions and helpers. 689 */ 690 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 691 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 692 693 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 694 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 695 696 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 697 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 698 699 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 700 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 701 702 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 703 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 704 705 struct amdgpu_mmio_remap { 706 u32 reg_offset; 707 resource_size_t bus_addr; 708 }; 709 710 /* Define the HW IP blocks will be used in driver , add more if necessary */ 711 enum amd_hw_ip_block_type { 712 GC_HWIP = 1, 713 HDP_HWIP, 714 SDMA0_HWIP, 715 SDMA1_HWIP, 716 SDMA2_HWIP, 717 SDMA3_HWIP, 718 SDMA4_HWIP, 719 SDMA5_HWIP, 720 SDMA6_HWIP, 721 SDMA7_HWIP, 722 LSDMA_HWIP, 723 MMHUB_HWIP, 724 ATHUB_HWIP, 725 NBIO_HWIP, 726 MP0_HWIP, 727 MP1_HWIP, 728 UVD_HWIP, 729 VCN_HWIP = UVD_HWIP, 730 JPEG_HWIP = VCN_HWIP, 731 VCN1_HWIP, 732 VCE_HWIP, 733 VPE_HWIP, 734 DF_HWIP, 735 DCE_HWIP, 736 OSSSYS_HWIP, 737 SMUIO_HWIP, 738 PWR_HWIP, 739 NBIF_HWIP, 740 THM_HWIP, 741 CLK_HWIP, 742 UMC_HWIP, 743 RSMU_HWIP, 744 XGMI_HWIP, 745 DCI_HWIP, 746 PCIE_HWIP, 747 ISP_HWIP, 748 MAX_HWIP 749 }; 750 751 #define HWIP_MAX_INSTANCE 44 752 753 #define HW_ID_MAX 300 754 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 755 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 756 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 757 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 758 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 759 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 760 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 761 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 762 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 763 764 struct amdgpu_ip_map_info { 765 /* Map of logical to actual dev instances/mask */ 766 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 767 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 768 enum amd_hw_ip_block_type block, 769 int8_t inst); 770 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 771 enum amd_hw_ip_block_type block, 772 uint32_t mask); 773 }; 774 775 struct amd_powerplay { 776 void *pp_handle; 777 const struct amd_pm_funcs *pp_funcs; 778 }; 779 780 struct ip_discovery_top; 781 782 /* polaris10 kickers */ 783 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 784 ((rid == 0xE3) || \ 785 (rid == 0xE4) || \ 786 (rid == 0xE5) || \ 787 (rid == 0xE7) || \ 788 (rid == 0xEF))) || \ 789 ((did == 0x6FDF) && \ 790 ((rid == 0xE7) || \ 791 (rid == 0xEF) || \ 792 (rid == 0xFF)))) 793 794 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 795 ((rid == 0xE1) || \ 796 (rid == 0xF7))) 797 798 /* polaris11 kickers */ 799 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 800 ((rid == 0xE0) || \ 801 (rid == 0xE5))) || \ 802 ((did == 0x67FF) && \ 803 ((rid == 0xCF) || \ 804 (rid == 0xEF) || \ 805 (rid == 0xFF)))) 806 807 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 808 ((rid == 0xE2))) 809 810 /* polaris12 kickers */ 811 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 812 ((rid == 0xC0) || \ 813 (rid == 0xC1) || \ 814 (rid == 0xC3) || \ 815 (rid == 0xC7))) || \ 816 ((did == 0x6981) && \ 817 ((rid == 0x00) || \ 818 (rid == 0x01) || \ 819 (rid == 0x10)))) 820 821 struct amdgpu_mqd_prop { 822 uint64_t mqd_gpu_addr; 823 uint64_t hqd_base_gpu_addr; 824 uint64_t rptr_gpu_addr; 825 uint64_t wptr_gpu_addr; 826 uint32_t queue_size; 827 bool use_doorbell; 828 uint32_t doorbell_index; 829 uint64_t eop_gpu_addr; 830 uint32_t hqd_pipe_priority; 831 uint32_t hqd_queue_priority; 832 bool allow_tunneling; 833 bool hqd_active; 834 uint64_t shadow_addr; 835 uint64_t gds_bkup_addr; 836 uint64_t csa_addr; 837 uint64_t fence_address; 838 }; 839 840 struct amdgpu_mqd { 841 unsigned mqd_size; 842 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 843 struct amdgpu_mqd_prop *p); 844 }; 845 846 struct amdgpu_pcie_reset_ctx { 847 bool in_link_reset; 848 bool occurs_dpc; 849 bool audio_suspended; 850 }; 851 852 /* 853 * Custom Init levels could be defined for different situations where a full 854 * initialization of all hardware blocks are not expected. Sample cases are 855 * custom init sequences after resume after S0i3/S3, reset on initialization, 856 * partial reset of blocks etc. Presently, this defines only two levels. Levels 857 * are described in corresponding struct definitions - amdgpu_init_default, 858 * amdgpu_init_minimal_xgmi. 859 */ 860 enum amdgpu_init_lvl_id { 861 AMDGPU_INIT_LEVEL_DEFAULT, 862 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 863 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 864 }; 865 866 struct amdgpu_init_level { 867 enum amdgpu_init_lvl_id level; 868 uint32_t hwini_ip_block_mask; 869 }; 870 871 #define AMDGPU_RESET_MAGIC_NUM 64 872 #define AMDGPU_MAX_DF_PERFMONS 4 873 struct amdgpu_reset_domain; 874 struct amdgpu_fru_info; 875 876 enum amdgpu_enforce_isolation_mode { 877 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 878 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 879 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 880 }; 881 882 883 /* 884 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 885 */ 886 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 887 888 struct amdgpu_device { 889 struct device *dev; 890 struct pci_dev *pdev; 891 struct drm_device ddev; 892 893 #ifdef CONFIG_DRM_AMD_ACP 894 struct amdgpu_acp acp; 895 #endif 896 struct amdgpu_hive_info *hive; 897 struct amdgpu_xcp_mgr *xcp_mgr; 898 /* ASIC */ 899 enum amd_asic_type asic_type; 900 uint32_t family; 901 uint32_t rev_id; 902 uint32_t external_rev_id; 903 unsigned long flags; 904 unsigned long apu_flags; 905 int usec_timeout; 906 const struct amdgpu_asic_funcs *asic_funcs; 907 bool shutdown; 908 bool need_swiotlb; 909 bool accel_working; 910 struct notifier_block acpi_nb; 911 struct notifier_block pm_nb; 912 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 913 struct debugfs_blob_wrapper debugfs_vbios_blob; 914 struct debugfs_blob_wrapper debugfs_discovery_blob; 915 struct mutex srbm_mutex; 916 /* GRBM index mutex. Protects concurrent access to GRBM index */ 917 struct mutex grbm_idx_mutex; 918 struct dev_pm_domain vga_pm_domain; 919 bool have_disp_power_ref; 920 bool have_atomics_support; 921 922 /* BIOS */ 923 bool is_atom_fw; 924 uint8_t *bios; 925 uint32_t bios_size; 926 uint32_t bios_scratch_reg_offset; 927 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 928 929 /* Register/doorbell mmio */ 930 resource_size_t rmmio_base; 931 resource_size_t rmmio_size; 932 void __iomem *rmmio; 933 /* protects concurrent MM_INDEX/DATA based register access */ 934 spinlock_t mmio_idx_lock; 935 struct amdgpu_mmio_remap rmmio_remap; 936 /* protects concurrent SMC based register access */ 937 spinlock_t smc_idx_lock; 938 amdgpu_rreg_t smc_rreg; 939 amdgpu_wreg_t smc_wreg; 940 /* protects concurrent PCIE register access */ 941 spinlock_t pcie_idx_lock; 942 amdgpu_rreg_t pcie_rreg; 943 amdgpu_wreg_t pcie_wreg; 944 amdgpu_rreg_t pciep_rreg; 945 amdgpu_wreg_t pciep_wreg; 946 amdgpu_rreg_ext_t pcie_rreg_ext; 947 amdgpu_wreg_ext_t pcie_wreg_ext; 948 amdgpu_rreg64_t pcie_rreg64; 949 amdgpu_wreg64_t pcie_wreg64; 950 amdgpu_rreg64_ext_t pcie_rreg64_ext; 951 amdgpu_wreg64_ext_t pcie_wreg64_ext; 952 /* protects concurrent UVD register access */ 953 spinlock_t uvd_ctx_idx_lock; 954 amdgpu_rreg_t uvd_ctx_rreg; 955 amdgpu_wreg_t uvd_ctx_wreg; 956 /* protects concurrent DIDT register access */ 957 spinlock_t didt_idx_lock; 958 amdgpu_rreg_t didt_rreg; 959 amdgpu_wreg_t didt_wreg; 960 /* protects concurrent gc_cac register access */ 961 spinlock_t gc_cac_idx_lock; 962 amdgpu_rreg_t gc_cac_rreg; 963 amdgpu_wreg_t gc_cac_wreg; 964 /* protects concurrent se_cac register access */ 965 spinlock_t se_cac_idx_lock; 966 amdgpu_rreg_t se_cac_rreg; 967 amdgpu_wreg_t se_cac_wreg; 968 /* protects concurrent ENDPOINT (audio) register access */ 969 spinlock_t audio_endpt_idx_lock; 970 amdgpu_block_rreg_t audio_endpt_rreg; 971 amdgpu_block_wreg_t audio_endpt_wreg; 972 struct amdgpu_doorbell doorbell; 973 974 /* clock/pll info */ 975 struct amdgpu_clock clock; 976 977 /* MC */ 978 struct amdgpu_gmc gmc; 979 struct amdgpu_gart gart; 980 dma_addr_t dummy_page_addr; 981 struct amdgpu_vm_manager vm_manager; 982 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 983 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 984 985 /* memory management */ 986 struct amdgpu_mman mman; 987 struct amdgpu_mem_scratch mem_scratch; 988 struct amdgpu_wb wb; 989 atomic64_t num_bytes_moved; 990 atomic64_t num_evictions; 991 atomic64_t num_vram_cpu_page_faults; 992 atomic_t gpu_reset_counter; 993 atomic_t vram_lost_counter; 994 995 /* data for buffer migration throttling */ 996 struct { 997 spinlock_t lock; 998 s64 last_update_us; 999 s64 accum_us; /* accumulated microseconds */ 1000 s64 accum_us_vis; /* for visible VRAM */ 1001 u32 log2_max_MBps; 1002 } mm_stats; 1003 1004 /* display */ 1005 bool enable_virtual_display; 1006 struct amdgpu_vkms_output *amdgpu_vkms_output; 1007 struct amdgpu_mode_info mode_info; 1008 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1009 struct delayed_work hotplug_work; 1010 struct amdgpu_irq_src crtc_irq; 1011 struct amdgpu_irq_src vline0_irq; 1012 struct amdgpu_irq_src vupdate_irq; 1013 struct amdgpu_irq_src pageflip_irq; 1014 struct amdgpu_irq_src hpd_irq; 1015 struct amdgpu_irq_src dmub_trace_irq; 1016 struct amdgpu_irq_src dmub_outbox_irq; 1017 1018 /* rings */ 1019 u64 fence_context; 1020 unsigned num_rings; 1021 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1022 struct dma_fence __rcu *gang_submit; 1023 bool ib_pool_ready; 1024 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1025 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1026 1027 /* interrupts */ 1028 struct amdgpu_irq irq; 1029 1030 /* powerplay */ 1031 struct amd_powerplay powerplay; 1032 struct amdgpu_pm pm; 1033 u64 cg_flags; 1034 u32 pg_flags; 1035 1036 /* nbio */ 1037 struct amdgpu_nbio nbio; 1038 1039 /* hdp */ 1040 struct amdgpu_hdp hdp; 1041 1042 /* smuio */ 1043 struct amdgpu_smuio smuio; 1044 1045 /* mmhub */ 1046 struct amdgpu_mmhub mmhub; 1047 1048 /* gfxhub */ 1049 struct amdgpu_gfxhub gfxhub; 1050 1051 /* gfx */ 1052 struct amdgpu_gfx gfx; 1053 1054 /* sdma */ 1055 struct amdgpu_sdma sdma; 1056 1057 /* lsdma */ 1058 struct amdgpu_lsdma lsdma; 1059 1060 /* uvd */ 1061 struct amdgpu_uvd uvd; 1062 1063 /* vce */ 1064 struct amdgpu_vce vce; 1065 1066 /* vcn */ 1067 struct amdgpu_vcn vcn; 1068 1069 /* jpeg */ 1070 struct amdgpu_jpeg jpeg; 1071 1072 /* vpe */ 1073 struct amdgpu_vpe vpe; 1074 1075 /* umsch */ 1076 struct amdgpu_umsch_mm umsch_mm; 1077 bool enable_umsch_mm; 1078 1079 /* firmwares */ 1080 struct amdgpu_firmware firmware; 1081 1082 /* PSP */ 1083 struct psp_context psp; 1084 1085 /* GDS */ 1086 struct amdgpu_gds gds; 1087 1088 /* for userq and VM fences */ 1089 struct amdgpu_seq64 seq64; 1090 1091 /* KFD */ 1092 struct amdgpu_kfd_dev kfd; 1093 1094 /* UMC */ 1095 struct amdgpu_umc umc; 1096 1097 /* display related functionality */ 1098 struct amdgpu_display_manager dm; 1099 1100 #if defined(CONFIG_DRM_AMD_ISP) 1101 /* isp */ 1102 struct amdgpu_isp isp; 1103 #endif 1104 1105 /* mes */ 1106 bool enable_mes; 1107 bool enable_mes_kiq; 1108 bool enable_uni_mes; 1109 struct amdgpu_mes mes; 1110 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1111 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1112 1113 /* xarray used to retrieve the user queue fence driver reference 1114 * in the EOP interrupt handler to signal the particular user 1115 * queue fence. 1116 */ 1117 struct xarray userq_xa; 1118 1119 /* df */ 1120 struct amdgpu_df df; 1121 1122 /* MCA */ 1123 struct amdgpu_mca mca; 1124 1125 /* ACA */ 1126 struct amdgpu_aca aca; 1127 1128 /* CPER */ 1129 struct amdgpu_cper cper; 1130 1131 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1132 uint32_t harvest_ip_mask; 1133 int num_ip_blocks; 1134 struct mutex mn_lock; 1135 DECLARE_HASHTABLE(mn_hash, 7); 1136 1137 /* tracking pinned memory */ 1138 atomic64_t vram_pin_size; 1139 atomic64_t visible_pin_size; 1140 atomic64_t gart_pin_size; 1141 1142 /* soc15 register offset based on ip, instance and segment */ 1143 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1144 struct amdgpu_ip_map_info ip_map; 1145 1146 /* delayed work_func for deferring clockgating during resume */ 1147 struct delayed_work delayed_init_work; 1148 1149 struct amdgpu_virt virt; 1150 1151 /* record hw reset is performed */ 1152 bool has_hw_reset; 1153 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1154 1155 /* s3/s4 mask */ 1156 bool in_suspend; 1157 bool in_s3; 1158 bool in_s4; 1159 bool in_s0ix; 1160 suspend_state_t last_suspend_state; 1161 1162 enum pp_mp1_state mp1_state; 1163 struct amdgpu_doorbell_index doorbell_index; 1164 1165 struct mutex notifier_lock; 1166 1167 int asic_reset_res; 1168 struct work_struct xgmi_reset_work; 1169 struct list_head reset_list; 1170 1171 long gfx_timeout; 1172 long sdma_timeout; 1173 long video_timeout; 1174 long compute_timeout; 1175 long psp_timeout; 1176 1177 uint64_t unique_id; 1178 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1179 1180 /* enable runtime pm on the device */ 1181 bool in_runpm; 1182 bool has_pr3; 1183 1184 bool ucode_sysfs_en; 1185 1186 struct amdgpu_fru_info *fru_info; 1187 atomic_t throttling_logging_enabled; 1188 struct ratelimit_state throttling_logging_rs; 1189 uint32_t ras_hw_enabled; 1190 uint32_t ras_enabled; 1191 bool ras_default_ecc_enabled; 1192 1193 bool no_hw_access; 1194 struct pci_saved_state *pci_state; 1195 pci_channel_state_t pci_channel_state; 1196 1197 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1198 1199 /* Track auto wait count on s_barrier settings */ 1200 bool barrier_has_auto_waitcnt; 1201 1202 struct amdgpu_reset_control *reset_cntl; 1203 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1204 1205 bool ram_is_direct_mapped; 1206 1207 struct list_head ras_list; 1208 1209 struct ip_discovery_top *ip_top; 1210 1211 struct amdgpu_reset_domain *reset_domain; 1212 1213 struct mutex benchmark_mutex; 1214 1215 bool scpm_enabled; 1216 uint32_t scpm_status; 1217 1218 struct work_struct reset_work; 1219 1220 bool dc_enabled; 1221 /* Mask of active clusters */ 1222 uint32_t aid_mask; 1223 1224 /* Debug */ 1225 bool debug_vm; 1226 bool debug_largebar; 1227 bool debug_disable_soft_recovery; 1228 bool debug_use_vram_fw_buf; 1229 bool debug_enable_ras_aca; 1230 bool debug_exp_resets; 1231 bool debug_disable_gpu_ring_reset; 1232 1233 /* Protection for the following isolation structure */ 1234 struct mutex enforce_isolation_mutex; 1235 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1236 struct amdgpu_isolation { 1237 void *owner; 1238 struct dma_fence *spearhead; 1239 struct amdgpu_sync active; 1240 struct amdgpu_sync prev; 1241 } isolation[MAX_XCP]; 1242 1243 struct amdgpu_init_level *init_lvl; 1244 1245 /* This flag is used to determine how VRAM allocations are handled for APUs 1246 * in KFD: VRAM or GTT. 1247 */ 1248 bool apu_prefer_gtt; 1249 1250 struct list_head userq_mgr_list; 1251 struct mutex userq_mutex; 1252 }; 1253 1254 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1255 uint8_t ip, uint8_t inst) 1256 { 1257 /* This considers only major/minor/rev and ignores 1258 * subrevision/variant fields. 1259 */ 1260 return adev->ip_versions[ip][inst] & ~0xFFU; 1261 } 1262 1263 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1264 uint8_t ip, uint8_t inst) 1265 { 1266 /* This returns full version - major/minor/rev/variant/subrevision */ 1267 return adev->ip_versions[ip][inst]; 1268 } 1269 1270 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1271 { 1272 return container_of(ddev, struct amdgpu_device, ddev); 1273 } 1274 1275 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1276 { 1277 return &adev->ddev; 1278 } 1279 1280 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1281 { 1282 return container_of(bdev, struct amdgpu_device, mman.bdev); 1283 } 1284 1285 int amdgpu_device_init(struct amdgpu_device *adev, 1286 uint32_t flags); 1287 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1288 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1289 1290 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1291 1292 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1293 void *buf, size_t size, bool write); 1294 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1295 void *buf, size_t size, bool write); 1296 1297 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1298 void *buf, size_t size, bool write); 1299 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1300 uint32_t inst, uint32_t reg_addr, char reg_name[], 1301 uint32_t expected_value, uint32_t mask); 1302 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1303 uint32_t reg, uint32_t acc_flags); 1304 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1305 u64 reg_addr); 1306 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1307 uint32_t reg, uint32_t acc_flags, 1308 uint32_t xcc_id); 1309 void amdgpu_device_wreg(struct amdgpu_device *adev, 1310 uint32_t reg, uint32_t v, 1311 uint32_t acc_flags); 1312 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1313 u64 reg_addr, u32 reg_data); 1314 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1315 uint32_t reg, uint32_t v, 1316 uint32_t acc_flags, 1317 uint32_t xcc_id); 1318 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1319 uint32_t reg, uint32_t v, uint32_t xcc_id); 1320 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1321 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1322 1323 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1324 u32 reg_addr); 1325 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1326 u32 reg_addr); 1327 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1328 u64 reg_addr); 1329 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1330 u32 reg_addr, u32 reg_data); 1331 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1332 u32 reg_addr, u64 reg_data); 1333 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1334 u64 reg_addr, u64 reg_data); 1335 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1336 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1337 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1338 1339 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1340 1341 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1342 struct amdgpu_reset_context *reset_context); 1343 1344 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1345 struct amdgpu_reset_context *reset_context); 1346 1347 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1348 1349 int emu_soc_asic_init(struct amdgpu_device *adev); 1350 1351 /* 1352 * Registers read & write functions. 1353 */ 1354 #define AMDGPU_REGS_NO_KIQ (1<<1) 1355 #define AMDGPU_REGS_RLC (1<<2) 1356 1357 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1358 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1359 1360 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1361 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1362 1363 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1364 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1365 1366 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1367 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1368 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1369 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1370 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1371 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1372 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1373 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1374 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1375 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1376 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1377 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1378 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1379 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1380 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1381 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1382 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1383 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1384 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1385 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1386 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1387 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1388 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1389 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1390 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1391 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1392 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1393 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1394 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1395 #define WREG32_P(reg, val, mask) \ 1396 do { \ 1397 uint32_t tmp_ = RREG32(reg); \ 1398 tmp_ &= (mask); \ 1399 tmp_ |= ((val) & ~(mask)); \ 1400 WREG32(reg, tmp_); \ 1401 } while (0) 1402 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1403 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1404 #define WREG32_PLL_P(reg, val, mask) \ 1405 do { \ 1406 uint32_t tmp_ = RREG32_PLL(reg); \ 1407 tmp_ &= (mask); \ 1408 tmp_ |= ((val) & ~(mask)); \ 1409 WREG32_PLL(reg, tmp_); \ 1410 } while (0) 1411 1412 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1413 do { \ 1414 u32 tmp = RREG32_SMC(_Reg); \ 1415 tmp &= (_Mask); \ 1416 tmp |= ((_Val) & ~(_Mask)); \ 1417 WREG32_SMC(_Reg, tmp); \ 1418 } while (0) 1419 1420 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1421 1422 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1423 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1424 1425 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1426 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1427 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1428 1429 #define REG_GET_FIELD(value, reg, field) \ 1430 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1431 1432 #define WREG32_FIELD(reg, field, val) \ 1433 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1434 1435 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1436 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1437 1438 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1439 /* 1440 * BIOS helpers. 1441 */ 1442 #define RBIOS8(i) (adev->bios[i]) 1443 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1444 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1445 1446 /* 1447 * ASICs macro. 1448 */ 1449 #define amdgpu_asic_set_vga_state(adev, state) \ 1450 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1451 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1452 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1453 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1454 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1455 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1456 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1457 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1458 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1459 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1460 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1461 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1462 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1463 #define amdgpu_asic_flush_hdp(adev, r) \ 1464 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1465 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1466 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1467 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1468 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1469 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1470 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1471 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1472 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1473 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1474 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1475 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1476 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1477 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1478 1479 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1480 1481 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1482 #define for_each_inst(i, inst_mask) \ 1483 for (i = ffs(inst_mask); i-- != 0; \ 1484 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1485 1486 /* Common functions */ 1487 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1488 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1489 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1490 struct amdgpu_job *job, 1491 struct amdgpu_reset_context *reset_context); 1492 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1493 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1494 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1495 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1496 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1497 1498 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1499 u64 num_vis_bytes); 1500 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1501 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1502 const u32 *registers, 1503 const u32 array_size); 1504 1505 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1506 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1507 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1508 bool amdgpu_device_supports_px(struct drm_device *dev); 1509 bool amdgpu_device_supports_boco(struct drm_device *dev); 1510 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1511 int amdgpu_device_supports_baco(struct drm_device *dev); 1512 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1513 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1514 struct amdgpu_device *peer_adev); 1515 int amdgpu_device_baco_enter(struct drm_device *dev); 1516 int amdgpu_device_baco_exit(struct drm_device *dev); 1517 1518 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1519 struct amdgpu_ring *ring); 1520 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1521 struct amdgpu_ring *ring); 1522 1523 void amdgpu_device_halt(struct amdgpu_device *adev); 1524 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1525 u32 reg); 1526 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1527 u32 reg, u32 v); 1528 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1529 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1530 struct dma_fence *gang); 1531 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1532 struct amdgpu_ring *ring, 1533 struct amdgpu_job *job); 1534 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1535 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1536 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1537 1538 /* atpx handler */ 1539 #if defined(CONFIG_VGA_SWITCHEROO) 1540 void amdgpu_register_atpx_handler(void); 1541 void amdgpu_unregister_atpx_handler(void); 1542 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1543 bool amdgpu_is_atpx_hybrid(void); 1544 bool amdgpu_has_atpx(void); 1545 #else 1546 static inline void amdgpu_register_atpx_handler(void) {} 1547 static inline void amdgpu_unregister_atpx_handler(void) {} 1548 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1549 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1550 static inline bool amdgpu_has_atpx(void) { return false; } 1551 #endif 1552 1553 /* 1554 * KMS 1555 */ 1556 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1557 extern const int amdgpu_max_kms_ioctl; 1558 1559 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1560 void amdgpu_driver_unload_kms(struct drm_device *dev); 1561 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1562 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1563 struct drm_file *file_priv); 1564 void amdgpu_driver_release_kms(struct drm_device *dev); 1565 1566 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1567 int amdgpu_device_prepare(struct drm_device *dev); 1568 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1569 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1570 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1571 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1572 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1573 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1574 struct drm_file *filp); 1575 1576 /* 1577 * functions used by amdgpu_encoder.c 1578 */ 1579 struct amdgpu_afmt_acr { 1580 u32 clock; 1581 1582 int n_32khz; 1583 int cts_32khz; 1584 1585 int n_44_1khz; 1586 int cts_44_1khz; 1587 1588 int n_48khz; 1589 int cts_48khz; 1590 1591 }; 1592 1593 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1594 1595 /* amdgpu_acpi.c */ 1596 1597 struct amdgpu_numa_info { 1598 uint64_t size; 1599 int pxm; 1600 int nid; 1601 }; 1602 1603 /* ATCS Device/Driver State */ 1604 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1605 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1606 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1607 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1608 1609 #if defined(CONFIG_ACPI) 1610 int amdgpu_acpi_init(struct amdgpu_device *adev); 1611 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1612 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1613 bool amdgpu_acpi_is_power_shift_control_supported(void); 1614 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1615 u8 perf_req, bool advertise); 1616 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1617 u8 dev_state, bool drv_state); 1618 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1619 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1620 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1621 u64 *tmr_size); 1622 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1623 struct amdgpu_numa_info *numa_info); 1624 1625 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1626 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1627 void amdgpu_acpi_detect(void); 1628 void amdgpu_acpi_release(void); 1629 #else 1630 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1631 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1632 u64 *tmr_offset, u64 *tmr_size) 1633 { 1634 return -EINVAL; 1635 } 1636 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1637 int xcc_id, 1638 struct amdgpu_numa_info *numa_info) 1639 { 1640 return -EINVAL; 1641 } 1642 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1643 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1644 static inline void amdgpu_acpi_detect(void) { } 1645 static inline void amdgpu_acpi_release(void) { } 1646 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1647 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1648 u8 dev_state, bool drv_state) { return 0; } 1649 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1650 enum amdgpu_ss ss_state) { return 0; } 1651 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1652 #endif 1653 1654 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1655 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1656 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1657 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1658 #else 1659 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1660 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1661 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1662 #endif 1663 1664 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1665 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1666 1667 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1668 pci_channel_state_t state); 1669 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1670 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1671 void amdgpu_pci_resume(struct pci_dev *pdev); 1672 1673 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1674 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1675 1676 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1677 1678 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1679 enum amd_clockgating_state state); 1680 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1681 enum amd_powergating_state state); 1682 1683 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1684 { 1685 return amdgpu_gpu_recovery != 0 && 1686 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1687 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1688 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1689 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1690 } 1691 1692 #include "amdgpu_object.h" 1693 1694 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1695 { 1696 return adev->gmc.tmz_enabled; 1697 } 1698 1699 int amdgpu_in_reset(struct amdgpu_device *adev); 1700 1701 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1702 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1703 extern const struct attribute_group amdgpu_flash_attr_group; 1704 1705 void amdgpu_set_init_level(struct amdgpu_device *adev, 1706 enum amdgpu_init_lvl_id lvl); 1707 #endif 1708