1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_module.h> 59 #include <drm/ttm/ttm_execbuf_util.h> 60 61 #include <drm/amdgpu_drm.h> 62 #include <drm/drm_gem.h> 63 #include <drm/drm_ioctl.h> 64 #include <drm/gpu_scheduler.h> 65 66 #include <kgd_kfd_interface.h> 67 #include "dm_pp_interface.h" 68 #include "kgd_pp_interface.h" 69 70 #include "amd_shared.h" 71 #include "amdgpu_mode.h" 72 #include "amdgpu_ih.h" 73 #include "amdgpu_irq.h" 74 #include "amdgpu_ucode.h" 75 #include "amdgpu_ttm.h" 76 #include "amdgpu_psp.h" 77 #include "amdgpu_gds.h" 78 #include "amdgpu_sync.h" 79 #include "amdgpu_ring.h" 80 #include "amdgpu_vm.h" 81 #include "amdgpu_dpm.h" 82 #include "amdgpu_acp.h" 83 #include "amdgpu_uvd.h" 84 #include "amdgpu_vce.h" 85 #include "amdgpu_vcn.h" 86 #include "amdgpu_jpeg.h" 87 #include "amdgpu_mn.h" 88 #include "amdgpu_gmc.h" 89 #include "amdgpu_gfx.h" 90 #include "amdgpu_sdma.h" 91 #include "amdgpu_nbio.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 110 #define MAX_GPU_INSTANCE 16 111 112 struct amdgpu_gpu_instance 113 { 114 struct amdgpu_device *adev; 115 int mgpu_fan_enabled; 116 }; 117 118 struct amdgpu_mgpu_info 119 { 120 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 121 struct mutex mutex; 122 uint32_t num_gpu; 123 uint32_t num_dgpu; 124 uint32_t num_apu; 125 }; 126 127 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 128 129 /* 130 * Modules parameters. 131 */ 132 extern int amdgpu_modeset; 133 extern int amdgpu_vram_limit; 134 extern int amdgpu_vis_vram_limit; 135 extern int amdgpu_gart_size; 136 extern int amdgpu_gtt_size; 137 extern int amdgpu_moverate; 138 extern int amdgpu_benchmarking; 139 extern int amdgpu_testing; 140 extern int amdgpu_audio; 141 extern int amdgpu_disp_priority; 142 extern int amdgpu_hw_i2c; 143 extern int amdgpu_pcie_gen2; 144 extern int amdgpu_msi; 145 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 146 extern int amdgpu_dpm; 147 extern int amdgpu_fw_load_type; 148 extern int amdgpu_aspm; 149 extern int amdgpu_runtime_pm; 150 extern uint amdgpu_ip_block_mask; 151 extern int amdgpu_bapm; 152 extern int amdgpu_deep_color; 153 extern int amdgpu_vm_size; 154 extern int amdgpu_vm_block_size; 155 extern int amdgpu_vm_fragment_size; 156 extern int amdgpu_vm_fault_stop; 157 extern int amdgpu_vm_debug; 158 extern int amdgpu_vm_update_mode; 159 extern int amdgpu_exp_hw_support; 160 extern int amdgpu_dc; 161 extern int amdgpu_sched_jobs; 162 extern int amdgpu_sched_hw_submission; 163 extern uint amdgpu_pcie_gen_cap; 164 extern uint amdgpu_pcie_lane_cap; 165 extern uint amdgpu_cg_mask; 166 extern uint amdgpu_pg_mask; 167 extern uint amdgpu_sdma_phase_quantum; 168 extern char *amdgpu_disable_cu; 169 extern char *amdgpu_virtual_display; 170 extern uint amdgpu_pp_feature_mask; 171 extern uint amdgpu_force_long_training; 172 extern int amdgpu_job_hang_limit; 173 extern int amdgpu_lbpw; 174 extern int amdgpu_compute_multipipe; 175 extern int amdgpu_gpu_recovery; 176 extern int amdgpu_emu_mode; 177 extern uint amdgpu_smu_memory_pool_size; 178 extern uint amdgpu_dc_feature_mask; 179 extern uint amdgpu_dc_debug_mask; 180 extern uint amdgpu_dm_abm_level; 181 extern struct amdgpu_mgpu_info mgpu_info; 182 extern int amdgpu_ras_enable; 183 extern uint amdgpu_ras_mask; 184 extern int amdgpu_bad_page_threshold; 185 extern int amdgpu_async_gfx_ring; 186 extern int amdgpu_mcbp; 187 extern int amdgpu_discovery; 188 extern int amdgpu_mes; 189 extern int amdgpu_noretry; 190 extern int amdgpu_force_asic_type; 191 #ifdef CONFIG_HSA_AMD 192 extern int sched_policy; 193 extern bool debug_evictions; 194 extern bool no_system_mem_limit; 195 #else 196 static const int sched_policy = KFD_SCHED_POLICY_HWS; 197 static const bool debug_evictions; /* = false */ 198 static const bool no_system_mem_limit; 199 #endif 200 201 extern int amdgpu_tmz; 202 extern int amdgpu_reset_method; 203 204 #ifdef CONFIG_DRM_AMDGPU_SI 205 extern int amdgpu_si_support; 206 #endif 207 #ifdef CONFIG_DRM_AMDGPU_CIK 208 extern int amdgpu_cik_support; 209 #endif 210 extern int amdgpu_num_kcq; 211 212 #define AMDGPU_VM_MAX_NUM_CTX 4096 213 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 214 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 215 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 216 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 217 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 218 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 219 #define AMDGPUFB_CONN_LIMIT 4 220 #define AMDGPU_BIOS_NUM_SCRATCH 16 221 222 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 223 224 /* hard reset data */ 225 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 226 227 /* reset flags */ 228 #define AMDGPU_RESET_GFX (1 << 0) 229 #define AMDGPU_RESET_COMPUTE (1 << 1) 230 #define AMDGPU_RESET_DMA (1 << 2) 231 #define AMDGPU_RESET_CP (1 << 3) 232 #define AMDGPU_RESET_GRBM (1 << 4) 233 #define AMDGPU_RESET_DMA1 (1 << 5) 234 #define AMDGPU_RESET_RLC (1 << 6) 235 #define AMDGPU_RESET_SEM (1 << 7) 236 #define AMDGPU_RESET_IH (1 << 8) 237 #define AMDGPU_RESET_VMC (1 << 9) 238 #define AMDGPU_RESET_MC (1 << 10) 239 #define AMDGPU_RESET_DISPLAY (1 << 11) 240 #define AMDGPU_RESET_UVD (1 << 12) 241 #define AMDGPU_RESET_VCE (1 << 13) 242 #define AMDGPU_RESET_VCE1 (1 << 14) 243 244 /* max cursor sizes (in pixels) */ 245 #define CIK_CURSOR_WIDTH 128 246 #define CIK_CURSOR_HEIGHT 128 247 248 struct amdgpu_device; 249 struct amdgpu_ib; 250 struct amdgpu_cs_parser; 251 struct amdgpu_job; 252 struct amdgpu_irq_src; 253 struct amdgpu_fpriv; 254 struct amdgpu_bo_va_mapping; 255 struct amdgpu_atif; 256 struct kfd_vm_fault_info; 257 struct amdgpu_hive_info; 258 259 enum amdgpu_cp_irq { 260 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 261 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 262 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 263 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 264 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 265 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 266 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 267 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 268 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 269 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 270 271 AMDGPU_CP_IRQ_LAST 272 }; 273 274 enum amdgpu_thermal_irq { 275 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 276 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 277 278 AMDGPU_THERMAL_IRQ_LAST 279 }; 280 281 enum amdgpu_kiq_irq { 282 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 283 AMDGPU_CP_KIQ_IRQ_LAST 284 }; 285 286 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 287 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 288 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 289 290 int amdgpu_device_ip_set_clockgating_state(void *dev, 291 enum amd_ip_block_type block_type, 292 enum amd_clockgating_state state); 293 int amdgpu_device_ip_set_powergating_state(void *dev, 294 enum amd_ip_block_type block_type, 295 enum amd_powergating_state state); 296 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 297 u32 *flags); 298 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 299 enum amd_ip_block_type block_type); 300 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 301 enum amd_ip_block_type block_type); 302 303 #define AMDGPU_MAX_IP_NUM 16 304 305 struct amdgpu_ip_block_status { 306 bool valid; 307 bool sw; 308 bool hw; 309 bool late_initialized; 310 bool hang; 311 }; 312 313 struct amdgpu_ip_block_version { 314 const enum amd_ip_block_type type; 315 const u32 major; 316 const u32 minor; 317 const u32 rev; 318 const struct amd_ip_funcs *funcs; 319 }; 320 321 #define HW_REV(_Major, _Minor, _Rev) \ 322 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 323 324 struct amdgpu_ip_block { 325 struct amdgpu_ip_block_status status; 326 const struct amdgpu_ip_block_version *version; 327 }; 328 329 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 330 enum amd_ip_block_type type, 331 u32 major, u32 minor); 332 333 struct amdgpu_ip_block * 334 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 335 enum amd_ip_block_type type); 336 337 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 338 const struct amdgpu_ip_block_version *ip_block_version); 339 340 /* 341 * BIOS. 342 */ 343 bool amdgpu_get_bios(struct amdgpu_device *adev); 344 bool amdgpu_read_bios(struct amdgpu_device *adev); 345 346 /* 347 * Clocks 348 */ 349 350 #define AMDGPU_MAX_PPLL 3 351 352 struct amdgpu_clock { 353 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 354 struct amdgpu_pll spll; 355 struct amdgpu_pll mpll; 356 /* 10 Khz units */ 357 uint32_t default_mclk; 358 uint32_t default_sclk; 359 uint32_t default_dispclk; 360 uint32_t current_dispclk; 361 uint32_t dp_extclk; 362 uint32_t max_pixel_clock; 363 }; 364 365 /* sub-allocation manager, it has to be protected by another lock. 366 * By conception this is an helper for other part of the driver 367 * like the indirect buffer or semaphore, which both have their 368 * locking. 369 * 370 * Principe is simple, we keep a list of sub allocation in offset 371 * order (first entry has offset == 0, last entry has the highest 372 * offset). 373 * 374 * When allocating new object we first check if there is room at 375 * the end total_size - (last_object_offset + last_object_size) >= 376 * alloc_size. If so we allocate new object there. 377 * 378 * When there is not enough room at the end, we start waiting for 379 * each sub object until we reach object_offset+object_size >= 380 * alloc_size, this object then become the sub object we return. 381 * 382 * Alignment can't be bigger than page size. 383 * 384 * Hole are not considered for allocation to keep things simple. 385 * Assumption is that there won't be hole (all object on same 386 * alignment). 387 */ 388 389 #define AMDGPU_SA_NUM_FENCE_LISTS 32 390 391 struct amdgpu_sa_manager { 392 wait_queue_head_t wq; 393 struct amdgpu_bo *bo; 394 struct list_head *hole; 395 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 396 struct list_head olist; 397 unsigned size; 398 uint64_t gpu_addr; 399 void *cpu_ptr; 400 uint32_t domain; 401 uint32_t align; 402 }; 403 404 /* sub-allocation buffer */ 405 struct amdgpu_sa_bo { 406 struct list_head olist; 407 struct list_head flist; 408 struct amdgpu_sa_manager *manager; 409 unsigned soffset; 410 unsigned eoffset; 411 struct dma_fence *fence; 412 }; 413 414 int amdgpu_fence_slab_init(void); 415 void amdgpu_fence_slab_fini(void); 416 417 /* 418 * IRQS. 419 */ 420 421 struct amdgpu_flip_work { 422 struct delayed_work flip_work; 423 struct work_struct unpin_work; 424 struct amdgpu_device *adev; 425 int crtc_id; 426 u32 target_vblank; 427 uint64_t base; 428 struct drm_pending_vblank_event *event; 429 struct amdgpu_bo *old_abo; 430 struct dma_fence *excl; 431 unsigned shared_count; 432 struct dma_fence **shared; 433 struct dma_fence_cb cb; 434 bool async; 435 }; 436 437 438 /* 439 * CP & rings. 440 */ 441 442 struct amdgpu_ib { 443 struct amdgpu_sa_bo *sa_bo; 444 uint32_t length_dw; 445 uint64_t gpu_addr; 446 uint32_t *ptr; 447 uint32_t flags; 448 }; 449 450 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 451 452 /* 453 * file private structure 454 */ 455 456 struct amdgpu_fpriv { 457 struct amdgpu_vm vm; 458 struct amdgpu_bo_va *prt_va; 459 struct amdgpu_bo_va *csa_va; 460 struct mutex bo_list_lock; 461 struct idr bo_list_handles; 462 struct amdgpu_ctx_mgr ctx_mgr; 463 }; 464 465 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 466 467 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 468 unsigned size, 469 enum amdgpu_ib_pool_type pool, 470 struct amdgpu_ib *ib); 471 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 472 struct dma_fence *f); 473 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 474 struct amdgpu_ib *ibs, struct amdgpu_job *job, 475 struct dma_fence **f); 476 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 477 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 478 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 479 480 /* 481 * CS. 482 */ 483 struct amdgpu_cs_chunk { 484 uint32_t chunk_id; 485 uint32_t length_dw; 486 void *kdata; 487 }; 488 489 struct amdgpu_cs_post_dep { 490 struct drm_syncobj *syncobj; 491 struct dma_fence_chain *chain; 492 u64 point; 493 }; 494 495 struct amdgpu_cs_parser { 496 struct amdgpu_device *adev; 497 struct drm_file *filp; 498 struct amdgpu_ctx *ctx; 499 500 /* chunks */ 501 unsigned nchunks; 502 struct amdgpu_cs_chunk *chunks; 503 504 /* scheduler job object */ 505 struct amdgpu_job *job; 506 struct drm_sched_entity *entity; 507 508 /* buffer objects */ 509 struct ww_acquire_ctx ticket; 510 struct amdgpu_bo_list *bo_list; 511 struct amdgpu_mn *mn; 512 struct amdgpu_bo_list_entry vm_pd; 513 struct list_head validated; 514 struct dma_fence *fence; 515 uint64_t bytes_moved_threshold; 516 uint64_t bytes_moved_vis_threshold; 517 uint64_t bytes_moved; 518 uint64_t bytes_moved_vis; 519 520 /* user fence */ 521 struct amdgpu_bo_list_entry uf_entry; 522 523 unsigned num_post_deps; 524 struct amdgpu_cs_post_dep *post_deps; 525 }; 526 527 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 528 uint32_t ib_idx, int idx) 529 { 530 return p->job->ibs[ib_idx].ptr[idx]; 531 } 532 533 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 534 uint32_t ib_idx, int idx, 535 uint32_t value) 536 { 537 p->job->ibs[ib_idx].ptr[idx] = value; 538 } 539 540 /* 541 * Writeback 542 */ 543 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 544 545 struct amdgpu_wb { 546 struct amdgpu_bo *wb_obj; 547 volatile uint32_t *wb; 548 uint64_t gpu_addr; 549 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 550 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 551 }; 552 553 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 554 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 555 556 /* 557 * Benchmarking 558 */ 559 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 560 561 562 /* 563 * Testing 564 */ 565 void amdgpu_test_moves(struct amdgpu_device *adev); 566 567 /* 568 * ASIC specific register table accessible by UMD 569 */ 570 struct amdgpu_allowed_register_entry { 571 uint32_t reg_offset; 572 bool grbm_indexed; 573 }; 574 575 enum amd_reset_method { 576 AMD_RESET_METHOD_LEGACY = 0, 577 AMD_RESET_METHOD_MODE0, 578 AMD_RESET_METHOD_MODE1, 579 AMD_RESET_METHOD_MODE2, 580 AMD_RESET_METHOD_BACO 581 }; 582 583 /* 584 * ASIC specific functions. 585 */ 586 struct amdgpu_asic_funcs { 587 bool (*read_disabled_bios)(struct amdgpu_device *adev); 588 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 589 u8 *bios, u32 length_bytes); 590 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 591 u32 sh_num, u32 reg_offset, u32 *value); 592 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 593 int (*reset)(struct amdgpu_device *adev); 594 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 595 /* get the reference clock */ 596 u32 (*get_xclk)(struct amdgpu_device *adev); 597 /* MM block clocks */ 598 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 599 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 600 /* static power management */ 601 int (*get_pcie_lanes)(struct amdgpu_device *adev); 602 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 603 /* get config memsize register */ 604 u32 (*get_config_memsize)(struct amdgpu_device *adev); 605 /* flush hdp write queue */ 606 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 607 /* invalidate hdp read cache */ 608 void (*invalidate_hdp)(struct amdgpu_device *adev, 609 struct amdgpu_ring *ring); 610 void (*reset_hdp_ras_error_count)(struct amdgpu_device *adev); 611 /* check if the asic needs a full reset of if soft reset will work */ 612 bool (*need_full_reset)(struct amdgpu_device *adev); 613 /* initialize doorbell layout for specific asic*/ 614 void (*init_doorbell_index)(struct amdgpu_device *adev); 615 /* PCIe bandwidth usage */ 616 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 617 uint64_t *count1); 618 /* do we need to reset the asic at init time (e.g., kexec) */ 619 bool (*need_reset_on_init)(struct amdgpu_device *adev); 620 /* PCIe replay counter */ 621 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 622 /* device supports BACO */ 623 bool (*supports_baco)(struct amdgpu_device *adev); 624 /* pre asic_init quirks */ 625 void (*pre_asic_init)(struct amdgpu_device *adev); 626 /* enter/exit umd stable pstate */ 627 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 628 }; 629 630 /* 631 * IOCTL. 632 */ 633 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 634 struct drm_file *filp); 635 636 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 637 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 638 struct drm_file *filp); 639 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 640 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 641 struct drm_file *filp); 642 643 /* VRAM scratch page for HDP bug, default vram page */ 644 struct amdgpu_vram_scratch { 645 struct amdgpu_bo *robj; 646 volatile uint32_t *ptr; 647 u64 gpu_addr; 648 }; 649 650 /* 651 * ACPI 652 */ 653 struct amdgpu_atcs_functions { 654 bool get_ext_state; 655 bool pcie_perf_req; 656 bool pcie_dev_rdy; 657 bool pcie_bus_width; 658 }; 659 660 struct amdgpu_atcs { 661 struct amdgpu_atcs_functions functions; 662 }; 663 664 /* 665 * CGS 666 */ 667 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 668 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 669 670 /* 671 * Core structure, functions and helpers. 672 */ 673 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 674 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 675 676 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 677 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 678 679 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 680 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 681 682 struct amdgpu_mmio_remap { 683 u32 reg_offset; 684 resource_size_t bus_addr; 685 }; 686 687 /* Define the HW IP blocks will be used in driver , add more if necessary */ 688 enum amd_hw_ip_block_type { 689 GC_HWIP = 1, 690 HDP_HWIP, 691 SDMA0_HWIP, 692 SDMA1_HWIP, 693 SDMA2_HWIP, 694 SDMA3_HWIP, 695 SDMA4_HWIP, 696 SDMA5_HWIP, 697 SDMA6_HWIP, 698 SDMA7_HWIP, 699 MMHUB_HWIP, 700 ATHUB_HWIP, 701 NBIO_HWIP, 702 MP0_HWIP, 703 MP1_HWIP, 704 UVD_HWIP, 705 VCN_HWIP = UVD_HWIP, 706 JPEG_HWIP = VCN_HWIP, 707 VCE_HWIP, 708 DF_HWIP, 709 DCE_HWIP, 710 OSSSYS_HWIP, 711 SMUIO_HWIP, 712 PWR_HWIP, 713 NBIF_HWIP, 714 THM_HWIP, 715 CLK_HWIP, 716 UMC_HWIP, 717 RSMU_HWIP, 718 MAX_HWIP 719 }; 720 721 #define HWIP_MAX_INSTANCE 8 722 723 struct amd_powerplay { 724 void *pp_handle; 725 const struct amd_pm_funcs *pp_funcs; 726 }; 727 728 /* polaris10 kickers */ 729 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 730 ((rid == 0xE3) || \ 731 (rid == 0xE4) || \ 732 (rid == 0xE5) || \ 733 (rid == 0xE7) || \ 734 (rid == 0xEF))) || \ 735 ((did == 0x6FDF) && \ 736 ((rid == 0xE7) || \ 737 (rid == 0xEF) || \ 738 (rid == 0xFF)))) 739 740 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 741 ((rid == 0xE1) || \ 742 (rid == 0xF7))) 743 744 /* polaris11 kickers */ 745 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 746 ((rid == 0xE0) || \ 747 (rid == 0xE5))) || \ 748 ((did == 0x67FF) && \ 749 ((rid == 0xCF) || \ 750 (rid == 0xEF) || \ 751 (rid == 0xFF)))) 752 753 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 754 ((rid == 0xE2))) 755 756 /* polaris12 kickers */ 757 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 758 ((rid == 0xC0) || \ 759 (rid == 0xC1) || \ 760 (rid == 0xC3) || \ 761 (rid == 0xC7))) || \ 762 ((did == 0x6981) && \ 763 ((rid == 0x00) || \ 764 (rid == 0x01) || \ 765 (rid == 0x10)))) 766 767 #define AMDGPU_RESET_MAGIC_NUM 64 768 #define AMDGPU_MAX_DF_PERFMONS 4 769 struct amdgpu_device { 770 struct device *dev; 771 struct pci_dev *pdev; 772 struct drm_device ddev; 773 774 #ifdef CONFIG_DRM_AMD_ACP 775 struct amdgpu_acp acp; 776 #endif 777 struct amdgpu_hive_info *hive; 778 /* ASIC */ 779 enum amd_asic_type asic_type; 780 uint32_t family; 781 uint32_t rev_id; 782 uint32_t external_rev_id; 783 unsigned long flags; 784 unsigned long apu_flags; 785 int usec_timeout; 786 const struct amdgpu_asic_funcs *asic_funcs; 787 bool shutdown; 788 bool need_swiotlb; 789 bool accel_working; 790 struct notifier_block acpi_nb; 791 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 792 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 793 unsigned debugfs_count; 794 #if defined(CONFIG_DEBUG_FS) 795 struct dentry *debugfs_preempt; 796 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 797 #endif 798 struct amdgpu_atif *atif; 799 struct amdgpu_atcs atcs; 800 struct mutex srbm_mutex; 801 /* GRBM index mutex. Protects concurrent access to GRBM index */ 802 struct mutex grbm_idx_mutex; 803 struct dev_pm_domain vga_pm_domain; 804 bool have_disp_power_ref; 805 bool have_atomics_support; 806 807 /* BIOS */ 808 bool is_atom_fw; 809 uint8_t *bios; 810 uint32_t bios_size; 811 uint32_t bios_scratch_reg_offset; 812 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 813 814 /* Register/doorbell mmio */ 815 resource_size_t rmmio_base; 816 resource_size_t rmmio_size; 817 void __iomem *rmmio; 818 /* protects concurrent MM_INDEX/DATA based register access */ 819 spinlock_t mmio_idx_lock; 820 struct amdgpu_mmio_remap rmmio_remap; 821 /* protects concurrent SMC based register access */ 822 spinlock_t smc_idx_lock; 823 amdgpu_rreg_t smc_rreg; 824 amdgpu_wreg_t smc_wreg; 825 /* protects concurrent PCIE register access */ 826 spinlock_t pcie_idx_lock; 827 amdgpu_rreg_t pcie_rreg; 828 amdgpu_wreg_t pcie_wreg; 829 amdgpu_rreg_t pciep_rreg; 830 amdgpu_wreg_t pciep_wreg; 831 amdgpu_rreg64_t pcie_rreg64; 832 amdgpu_wreg64_t pcie_wreg64; 833 /* protects concurrent UVD register access */ 834 spinlock_t uvd_ctx_idx_lock; 835 amdgpu_rreg_t uvd_ctx_rreg; 836 amdgpu_wreg_t uvd_ctx_wreg; 837 /* protects concurrent DIDT register access */ 838 spinlock_t didt_idx_lock; 839 amdgpu_rreg_t didt_rreg; 840 amdgpu_wreg_t didt_wreg; 841 /* protects concurrent gc_cac register access */ 842 spinlock_t gc_cac_idx_lock; 843 amdgpu_rreg_t gc_cac_rreg; 844 amdgpu_wreg_t gc_cac_wreg; 845 /* protects concurrent se_cac register access */ 846 spinlock_t se_cac_idx_lock; 847 amdgpu_rreg_t se_cac_rreg; 848 amdgpu_wreg_t se_cac_wreg; 849 /* protects concurrent ENDPOINT (audio) register access */ 850 spinlock_t audio_endpt_idx_lock; 851 amdgpu_block_rreg_t audio_endpt_rreg; 852 amdgpu_block_wreg_t audio_endpt_wreg; 853 void __iomem *rio_mem; 854 resource_size_t rio_mem_size; 855 struct amdgpu_doorbell doorbell; 856 857 /* clock/pll info */ 858 struct amdgpu_clock clock; 859 860 /* MC */ 861 struct amdgpu_gmc gmc; 862 struct amdgpu_gart gart; 863 dma_addr_t dummy_page_addr; 864 struct amdgpu_vm_manager vm_manager; 865 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 866 unsigned num_vmhubs; 867 868 /* memory management */ 869 struct amdgpu_mman mman; 870 struct amdgpu_vram_scratch vram_scratch; 871 struct amdgpu_wb wb; 872 atomic64_t num_bytes_moved; 873 atomic64_t num_evictions; 874 atomic64_t num_vram_cpu_page_faults; 875 atomic_t gpu_reset_counter; 876 atomic_t vram_lost_counter; 877 878 /* data for buffer migration throttling */ 879 struct { 880 spinlock_t lock; 881 s64 last_update_us; 882 s64 accum_us; /* accumulated microseconds */ 883 s64 accum_us_vis; /* for visible VRAM */ 884 u32 log2_max_MBps; 885 } mm_stats; 886 887 /* display */ 888 bool enable_virtual_display; 889 struct amdgpu_mode_info mode_info; 890 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 891 struct work_struct hotplug_work; 892 struct amdgpu_irq_src crtc_irq; 893 struct amdgpu_irq_src vupdate_irq; 894 struct amdgpu_irq_src pageflip_irq; 895 struct amdgpu_irq_src hpd_irq; 896 897 /* rings */ 898 u64 fence_context; 899 unsigned num_rings; 900 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 901 bool ib_pool_ready; 902 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 903 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 904 905 /* interrupts */ 906 struct amdgpu_irq irq; 907 908 /* powerplay */ 909 struct amd_powerplay powerplay; 910 bool pp_force_state_enabled; 911 912 /* smu */ 913 struct smu_context smu; 914 915 /* dpm */ 916 struct amdgpu_pm pm; 917 u32 cg_flags; 918 u32 pg_flags; 919 920 /* nbio */ 921 struct amdgpu_nbio nbio; 922 923 /* mmhub */ 924 struct amdgpu_mmhub mmhub; 925 926 /* gfxhub */ 927 struct amdgpu_gfxhub gfxhub; 928 929 /* gfx */ 930 struct amdgpu_gfx gfx; 931 932 /* sdma */ 933 struct amdgpu_sdma sdma; 934 935 /* uvd */ 936 struct amdgpu_uvd uvd; 937 938 /* vce */ 939 struct amdgpu_vce vce; 940 941 /* vcn */ 942 struct amdgpu_vcn vcn; 943 944 /* jpeg */ 945 struct amdgpu_jpeg jpeg; 946 947 /* firmwares */ 948 struct amdgpu_firmware firmware; 949 950 /* PSP */ 951 struct psp_context psp; 952 953 /* GDS */ 954 struct amdgpu_gds gds; 955 956 /* KFD */ 957 struct amdgpu_kfd_dev kfd; 958 959 /* UMC */ 960 struct amdgpu_umc umc; 961 962 /* display related functionality */ 963 struct amdgpu_display_manager dm; 964 965 /* mes */ 966 bool enable_mes; 967 struct amdgpu_mes mes; 968 969 /* df */ 970 struct amdgpu_df df; 971 972 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 973 int num_ip_blocks; 974 struct mutex mn_lock; 975 DECLARE_HASHTABLE(mn_hash, 7); 976 977 /* tracking pinned memory */ 978 atomic64_t vram_pin_size; 979 atomic64_t visible_pin_size; 980 atomic64_t gart_pin_size; 981 982 /* soc15 register offset based on ip, instance and segment */ 983 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 984 985 /* delayed work_func for deferring clockgating during resume */ 986 struct delayed_work delayed_init_work; 987 988 struct amdgpu_virt virt; 989 990 /* link all shadow bo */ 991 struct list_head shadow_list; 992 struct mutex shadow_list_lock; 993 994 /* record hw reset is performed */ 995 bool has_hw_reset; 996 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 997 998 /* s3/s4 mask */ 999 bool in_suspend; 1000 bool in_hibernate; 1001 1002 atomic_t in_gpu_reset; 1003 enum pp_mp1_state mp1_state; 1004 struct rw_semaphore reset_sem; 1005 struct amdgpu_doorbell_index doorbell_index; 1006 1007 struct mutex notifier_lock; 1008 1009 int asic_reset_res; 1010 struct work_struct xgmi_reset_work; 1011 1012 long gfx_timeout; 1013 long sdma_timeout; 1014 long video_timeout; 1015 long compute_timeout; 1016 1017 uint64_t unique_id; 1018 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1019 1020 /* enable runtime pm on the device */ 1021 bool runpm; 1022 bool in_runpm; 1023 1024 bool pm_sysfs_en; 1025 bool ucode_sysfs_en; 1026 1027 /* Chip product information */ 1028 char product_number[16]; 1029 char product_name[32]; 1030 char serial[20]; 1031 1032 struct amdgpu_autodump autodump; 1033 1034 atomic_t throttling_logging_enabled; 1035 struct ratelimit_state throttling_logging_rs; 1036 uint32_t ras_features; 1037 1038 bool in_pci_err_recovery; 1039 struct pci_saved_state *pci_state; 1040 }; 1041 1042 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1043 { 1044 return container_of(ddev, struct amdgpu_device, ddev); 1045 } 1046 1047 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1048 { 1049 return &adev->ddev; 1050 } 1051 1052 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1053 { 1054 return container_of(bdev, struct amdgpu_device, mman.bdev); 1055 } 1056 1057 int amdgpu_device_init(struct amdgpu_device *adev, 1058 uint32_t flags); 1059 void amdgpu_device_fini(struct amdgpu_device *adev); 1060 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1061 1062 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1063 uint32_t *buf, size_t size, bool write); 1064 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1065 uint32_t reg, uint32_t acc_flags); 1066 void amdgpu_device_wreg(struct amdgpu_device *adev, 1067 uint32_t reg, uint32_t v, 1068 uint32_t acc_flags); 1069 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1070 uint32_t reg, uint32_t v); 1071 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1072 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1073 1074 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1075 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1076 1077 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1078 u32 pcie_index, u32 pcie_data, 1079 u32 reg_addr); 1080 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1081 u32 pcie_index, u32 pcie_data, 1082 u32 reg_addr); 1083 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1084 u32 pcie_index, u32 pcie_data, 1085 u32 reg_addr, u32 reg_data); 1086 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1087 u32 pcie_index, u32 pcie_data, 1088 u32 reg_addr, u64 reg_data); 1089 1090 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1091 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1092 1093 int emu_soc_asic_init(struct amdgpu_device *adev); 1094 1095 /* 1096 * Registers read & write functions. 1097 */ 1098 #define AMDGPU_REGS_NO_KIQ (1<<1) 1099 1100 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1101 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1102 1103 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1104 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1105 1106 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1107 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1108 1109 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1110 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1111 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1112 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1113 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1114 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1115 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1116 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1117 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1118 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1119 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1120 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1121 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1122 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1123 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1124 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1125 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1126 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1127 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1128 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1129 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1130 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1131 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1132 #define WREG32_P(reg, val, mask) \ 1133 do { \ 1134 uint32_t tmp_ = RREG32(reg); \ 1135 tmp_ &= (mask); \ 1136 tmp_ |= ((val) & ~(mask)); \ 1137 WREG32(reg, tmp_); \ 1138 } while (0) 1139 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1140 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1141 #define WREG32_PLL_P(reg, val, mask) \ 1142 do { \ 1143 uint32_t tmp_ = RREG32_PLL(reg); \ 1144 tmp_ &= (mask); \ 1145 tmp_ |= ((val) & ~(mask)); \ 1146 WREG32_PLL(reg, tmp_); \ 1147 } while (0) 1148 1149 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1150 do { \ 1151 u32 tmp = RREG32_SMC(_Reg); \ 1152 tmp &= (_Mask); \ 1153 tmp |= ((_Val) & ~(_Mask)); \ 1154 WREG32_SMC(_Reg, tmp); \ 1155 } while (0) 1156 1157 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1158 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1159 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1160 1161 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1162 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1163 1164 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1165 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1166 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1167 1168 #define REG_GET_FIELD(value, reg, field) \ 1169 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1170 1171 #define WREG32_FIELD(reg, field, val) \ 1172 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1173 1174 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1175 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1176 1177 /* 1178 * BIOS helpers. 1179 */ 1180 #define RBIOS8(i) (adev->bios[i]) 1181 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1182 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1183 1184 /* 1185 * ASICs macro. 1186 */ 1187 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1188 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1189 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1190 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1191 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1192 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1193 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1194 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1195 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1196 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1197 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1198 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1199 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1200 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1201 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1202 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1203 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1204 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1205 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1206 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1207 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1208 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1209 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1210 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1211 1212 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1213 1214 /* Common functions */ 1215 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1216 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1217 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1218 struct amdgpu_job* job); 1219 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1220 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1221 1222 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1223 u64 num_vis_bytes); 1224 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1225 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1226 const u32 *registers, 1227 const u32 array_size); 1228 1229 bool amdgpu_device_supports_boco(struct drm_device *dev); 1230 bool amdgpu_device_supports_baco(struct drm_device *dev); 1231 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1232 struct amdgpu_device *peer_adev); 1233 int amdgpu_device_baco_enter(struct drm_device *dev); 1234 int amdgpu_device_baco_exit(struct drm_device *dev); 1235 1236 /* atpx handler */ 1237 #if defined(CONFIG_VGA_SWITCHEROO) 1238 void amdgpu_register_atpx_handler(void); 1239 void amdgpu_unregister_atpx_handler(void); 1240 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1241 bool amdgpu_is_atpx_hybrid(void); 1242 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1243 bool amdgpu_has_atpx(void); 1244 #else 1245 static inline void amdgpu_register_atpx_handler(void) {} 1246 static inline void amdgpu_unregister_atpx_handler(void) {} 1247 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1248 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1249 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1250 static inline bool amdgpu_has_atpx(void) { return false; } 1251 #endif 1252 1253 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1254 void *amdgpu_atpx_get_dhandle(void); 1255 #else 1256 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1257 #endif 1258 1259 /* 1260 * KMS 1261 */ 1262 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1263 extern const int amdgpu_max_kms_ioctl; 1264 1265 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1266 void amdgpu_driver_unload_kms(struct drm_device *dev); 1267 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1268 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1269 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1270 struct drm_file *file_priv); 1271 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1272 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1273 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1274 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1275 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1276 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1277 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1278 unsigned long arg); 1279 1280 /* 1281 * functions used by amdgpu_encoder.c 1282 */ 1283 struct amdgpu_afmt_acr { 1284 u32 clock; 1285 1286 int n_32khz; 1287 int cts_32khz; 1288 1289 int n_44_1khz; 1290 int cts_44_1khz; 1291 1292 int n_48khz; 1293 int cts_48khz; 1294 1295 }; 1296 1297 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1298 1299 /* amdgpu_acpi.c */ 1300 #if defined(CONFIG_ACPI) 1301 int amdgpu_acpi_init(struct amdgpu_device *adev); 1302 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1303 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1304 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1305 u8 perf_req, bool advertise); 1306 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1307 1308 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1309 struct amdgpu_dm_backlight_caps *caps); 1310 #else 1311 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1312 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1313 #endif 1314 1315 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1316 uint64_t addr, struct amdgpu_bo **bo, 1317 struct amdgpu_bo_va_mapping **mapping); 1318 1319 #if defined(CONFIG_DRM_AMD_DC) 1320 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1321 #else 1322 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1323 #endif 1324 1325 1326 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1327 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1328 1329 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1330 pci_channel_state_t state); 1331 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1332 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1333 void amdgpu_pci_resume(struct pci_dev *pdev); 1334 1335 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1336 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1337 1338 #include "amdgpu_object.h" 1339 1340 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1341 { 1342 return adev->gmc.tmz_enabled; 1343 } 1344 1345 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1346 { 1347 return atomic_read(&adev->in_gpu_reset); 1348 } 1349 #endif 1350