1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 #if defined(CONFIG_DRM_AMD_ISP) 116 #include "amdgpu_isp.h" 117 #endif 118 119 #define MAX_GPU_INSTANCE 64 120 121 struct amdgpu_gpu_instance { 122 struct amdgpu_device *adev; 123 int mgpu_fan_enabled; 124 }; 125 126 struct amdgpu_mgpu_info { 127 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 128 struct mutex mutex; 129 uint32_t num_gpu; 130 uint32_t num_dgpu; 131 uint32_t num_apu; 132 133 /* delayed reset_func for XGMI configuration if necessary */ 134 struct delayed_work delayed_reset_work; 135 bool pending_reset; 136 }; 137 138 enum amdgpu_ss { 139 AMDGPU_SS_DRV_LOAD, 140 AMDGPU_SS_DEV_D0, 141 AMDGPU_SS_DEV_D3, 142 AMDGPU_SS_DRV_UNLOAD 143 }; 144 145 struct amdgpu_hwip_reg_entry { 146 u32 hwip; 147 u32 inst; 148 u32 seg; 149 u32 reg_offset; 150 const char *reg_name; 151 }; 152 153 struct amdgpu_watchdog_timer { 154 bool timeout_fatal_disable; 155 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 156 }; 157 158 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 159 160 /* 161 * Modules parameters. 162 */ 163 extern int amdgpu_modeset; 164 extern unsigned int amdgpu_vram_limit; 165 extern int amdgpu_vis_vram_limit; 166 extern int amdgpu_gart_size; 167 extern int amdgpu_gtt_size; 168 extern int amdgpu_moverate; 169 extern int amdgpu_audio; 170 extern int amdgpu_disp_priority; 171 extern int amdgpu_hw_i2c; 172 extern int amdgpu_pcie_gen2; 173 extern int amdgpu_msi; 174 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 175 extern int amdgpu_dpm; 176 extern int amdgpu_fw_load_type; 177 extern int amdgpu_aspm; 178 extern int amdgpu_runtime_pm; 179 extern uint amdgpu_ip_block_mask; 180 extern int amdgpu_bapm; 181 extern int amdgpu_deep_color; 182 extern int amdgpu_vm_size; 183 extern int amdgpu_vm_block_size; 184 extern int amdgpu_vm_fragment_size; 185 extern int amdgpu_vm_fault_stop; 186 extern int amdgpu_vm_debug; 187 extern int amdgpu_vm_update_mode; 188 extern int amdgpu_exp_hw_support; 189 extern int amdgpu_dc; 190 extern int amdgpu_sched_jobs; 191 extern int amdgpu_sched_hw_submission; 192 extern uint amdgpu_pcie_gen_cap; 193 extern uint amdgpu_pcie_lane_cap; 194 extern u64 amdgpu_cg_mask; 195 extern uint amdgpu_pg_mask; 196 extern uint amdgpu_sdma_phase_quantum; 197 extern char *amdgpu_disable_cu; 198 extern char *amdgpu_virtual_display; 199 extern uint amdgpu_pp_feature_mask; 200 extern uint amdgpu_force_long_training; 201 extern int amdgpu_lbpw; 202 extern int amdgpu_compute_multipipe; 203 extern int amdgpu_gpu_recovery; 204 extern int amdgpu_emu_mode; 205 extern uint amdgpu_smu_memory_pool_size; 206 extern int amdgpu_smu_pptable_id; 207 extern uint amdgpu_dc_feature_mask; 208 extern uint amdgpu_freesync_vid_mode; 209 extern uint amdgpu_dc_debug_mask; 210 extern uint amdgpu_dc_visual_confirm; 211 extern int amdgpu_dm_abm_level; 212 extern int amdgpu_backlight; 213 extern int amdgpu_damage_clips; 214 extern struct amdgpu_mgpu_info mgpu_info; 215 extern int amdgpu_ras_enable; 216 extern uint amdgpu_ras_mask; 217 extern int amdgpu_bad_page_threshold; 218 extern bool amdgpu_ignore_bad_page_threshold; 219 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 220 extern int amdgpu_async_gfx_ring; 221 extern int amdgpu_mcbp; 222 extern int amdgpu_discovery; 223 extern int amdgpu_mes; 224 extern int amdgpu_mes_log_enable; 225 extern int amdgpu_mes_kiq; 226 extern int amdgpu_uni_mes; 227 extern int amdgpu_noretry; 228 extern int amdgpu_force_asic_type; 229 extern int amdgpu_smartshift_bias; 230 extern int amdgpu_use_xgmi_p2p; 231 extern int amdgpu_mtype_local; 232 extern bool enforce_isolation; 233 #ifdef CONFIG_HSA_AMD 234 extern int sched_policy; 235 extern bool debug_evictions; 236 extern bool no_system_mem_limit; 237 extern int halt_if_hws_hang; 238 #else 239 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 240 static const bool __maybe_unused debug_evictions; /* = false */ 241 static const bool __maybe_unused no_system_mem_limit; 242 static const int __maybe_unused halt_if_hws_hang; 243 #endif 244 #ifdef CONFIG_HSA_AMD_P2P 245 extern bool pcie_p2p; 246 #endif 247 248 extern int amdgpu_tmz; 249 extern int amdgpu_reset_method; 250 251 #ifdef CONFIG_DRM_AMDGPU_SI 252 extern int amdgpu_si_support; 253 #endif 254 #ifdef CONFIG_DRM_AMDGPU_CIK 255 extern int amdgpu_cik_support; 256 #endif 257 extern int amdgpu_num_kcq; 258 259 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 260 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 261 extern int amdgpu_vcnfw_log; 262 extern int amdgpu_sg_display; 263 extern int amdgpu_umsch_mm; 264 extern int amdgpu_seamless; 265 extern int amdgpu_umsch_mm_fwlog; 266 267 extern int amdgpu_user_partt_mode; 268 extern int amdgpu_agp; 269 270 extern int amdgpu_wbrf; 271 272 #define AMDGPU_VM_MAX_NUM_CTX 4096 273 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 274 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 275 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 276 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 277 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 278 #define AMDGPUFB_CONN_LIMIT 4 279 #define AMDGPU_BIOS_NUM_SCRATCH 16 280 281 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 282 283 /* hard reset data */ 284 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 285 286 /* reset flags */ 287 #define AMDGPU_RESET_GFX (1 << 0) 288 #define AMDGPU_RESET_COMPUTE (1 << 1) 289 #define AMDGPU_RESET_DMA (1 << 2) 290 #define AMDGPU_RESET_CP (1 << 3) 291 #define AMDGPU_RESET_GRBM (1 << 4) 292 #define AMDGPU_RESET_DMA1 (1 << 5) 293 #define AMDGPU_RESET_RLC (1 << 6) 294 #define AMDGPU_RESET_SEM (1 << 7) 295 #define AMDGPU_RESET_IH (1 << 8) 296 #define AMDGPU_RESET_VMC (1 << 9) 297 #define AMDGPU_RESET_MC (1 << 10) 298 #define AMDGPU_RESET_DISPLAY (1 << 11) 299 #define AMDGPU_RESET_UVD (1 << 12) 300 #define AMDGPU_RESET_VCE (1 << 13) 301 #define AMDGPU_RESET_VCE1 (1 << 14) 302 303 /* max cursor sizes (in pixels) */ 304 #define CIK_CURSOR_WIDTH 128 305 #define CIK_CURSOR_HEIGHT 128 306 307 /* smart shift bias level limits */ 308 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 309 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 310 311 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 312 #define AMDGPU_SWCTF_EXTRA_DELAY 50 313 314 struct amdgpu_xcp_mgr; 315 struct amdgpu_device; 316 struct amdgpu_irq_src; 317 struct amdgpu_fpriv; 318 struct amdgpu_bo_va_mapping; 319 struct kfd_vm_fault_info; 320 struct amdgpu_hive_info; 321 struct amdgpu_reset_context; 322 struct amdgpu_reset_control; 323 324 enum amdgpu_cp_irq { 325 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 326 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 327 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 328 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 329 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 330 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 331 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 332 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 333 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 334 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 335 336 AMDGPU_CP_IRQ_LAST 337 }; 338 339 enum amdgpu_thermal_irq { 340 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 341 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 342 343 AMDGPU_THERMAL_IRQ_LAST 344 }; 345 346 enum amdgpu_kiq_irq { 347 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 348 AMDGPU_CP_KIQ_IRQ_LAST 349 }; 350 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 351 #define MAX_KIQ_REG_WAIT (amdgpu_sriov_vf(adev) ? 50000 : 5000) /* in usecs, extend for VF */ 352 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 353 #define MAX_KIQ_REG_TRY 1000 354 355 int amdgpu_device_ip_set_clockgating_state(void *dev, 356 enum amd_ip_block_type block_type, 357 enum amd_clockgating_state state); 358 int amdgpu_device_ip_set_powergating_state(void *dev, 359 enum amd_ip_block_type block_type, 360 enum amd_powergating_state state); 361 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 362 u64 *flags); 363 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 364 enum amd_ip_block_type block_type); 365 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 366 enum amd_ip_block_type block_type); 367 368 #define AMDGPU_MAX_IP_NUM 16 369 370 struct amdgpu_ip_block_status { 371 bool valid; 372 bool sw; 373 bool hw; 374 bool late_initialized; 375 bool hang; 376 }; 377 378 struct amdgpu_ip_block_version { 379 const enum amd_ip_block_type type; 380 const u32 major; 381 const u32 minor; 382 const u32 rev; 383 const struct amd_ip_funcs *funcs; 384 }; 385 386 struct amdgpu_ip_block { 387 struct amdgpu_ip_block_status status; 388 const struct amdgpu_ip_block_version *version; 389 }; 390 391 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 392 enum amd_ip_block_type type, 393 u32 major, u32 minor); 394 395 struct amdgpu_ip_block * 396 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 397 enum amd_ip_block_type type); 398 399 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 400 const struct amdgpu_ip_block_version *ip_block_version); 401 402 /* 403 * BIOS. 404 */ 405 bool amdgpu_get_bios(struct amdgpu_device *adev); 406 bool amdgpu_read_bios(struct amdgpu_device *adev); 407 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 408 u8 *bios, u32 length_bytes); 409 /* 410 * Clocks 411 */ 412 413 #define AMDGPU_MAX_PPLL 3 414 415 struct amdgpu_clock { 416 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 417 struct amdgpu_pll spll; 418 struct amdgpu_pll mpll; 419 /* 10 Khz units */ 420 uint32_t default_mclk; 421 uint32_t default_sclk; 422 uint32_t default_dispclk; 423 uint32_t current_dispclk; 424 uint32_t dp_extclk; 425 uint32_t max_pixel_clock; 426 }; 427 428 /* sub-allocation manager, it has to be protected by another lock. 429 * By conception this is an helper for other part of the driver 430 * like the indirect buffer or semaphore, which both have their 431 * locking. 432 * 433 * Principe is simple, we keep a list of sub allocation in offset 434 * order (first entry has offset == 0, last entry has the highest 435 * offset). 436 * 437 * When allocating new object we first check if there is room at 438 * the end total_size - (last_object_offset + last_object_size) >= 439 * alloc_size. If so we allocate new object there. 440 * 441 * When there is not enough room at the end, we start waiting for 442 * each sub object until we reach object_offset+object_size >= 443 * alloc_size, this object then become the sub object we return. 444 * 445 * Alignment can't be bigger than page size. 446 * 447 * Hole are not considered for allocation to keep things simple. 448 * Assumption is that there won't be hole (all object on same 449 * alignment). 450 */ 451 452 struct amdgpu_sa_manager { 453 struct drm_suballoc_manager base; 454 struct amdgpu_bo *bo; 455 uint64_t gpu_addr; 456 void *cpu_ptr; 457 }; 458 459 int amdgpu_fence_slab_init(void); 460 void amdgpu_fence_slab_fini(void); 461 462 /* 463 * IRQS. 464 */ 465 466 struct amdgpu_flip_work { 467 struct delayed_work flip_work; 468 struct work_struct unpin_work; 469 struct amdgpu_device *adev; 470 int crtc_id; 471 u32 target_vblank; 472 uint64_t base; 473 struct drm_pending_vblank_event *event; 474 struct amdgpu_bo *old_abo; 475 unsigned shared_count; 476 struct dma_fence **shared; 477 struct dma_fence_cb cb; 478 bool async; 479 }; 480 481 482 /* 483 * file private structure 484 */ 485 486 struct amdgpu_fpriv { 487 struct amdgpu_vm vm; 488 struct amdgpu_bo_va *prt_va; 489 struct amdgpu_bo_va *csa_va; 490 struct amdgpu_bo_va *seq64_va; 491 struct mutex bo_list_lock; 492 struct idr bo_list_handles; 493 struct amdgpu_ctx_mgr ctx_mgr; 494 /** GPU partition selection */ 495 uint32_t xcp_id; 496 }; 497 498 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 499 500 /* 501 * Writeback 502 */ 503 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 504 505 struct amdgpu_wb { 506 struct amdgpu_bo *wb_obj; 507 volatile uint32_t *wb; 508 uint64_t gpu_addr; 509 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 510 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 511 spinlock_t lock; 512 }; 513 514 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 515 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 516 517 /* 518 * Benchmarking 519 */ 520 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 521 522 /* 523 * ASIC specific register table accessible by UMD 524 */ 525 struct amdgpu_allowed_register_entry { 526 uint32_t reg_offset; 527 bool grbm_indexed; 528 }; 529 530 /** 531 * enum amd_reset_method - Methods for resetting AMD GPU devices 532 * 533 * @AMD_RESET_METHOD_NONE: The device will not be reset. 534 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 535 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 536 * any device. 537 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 538 * individually. Suitable only for some discrete GPU, not 539 * available for all ASICs. 540 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 541 * are reset depends on the ASIC. Notably doesn't reset IPs 542 * shared with the CPU on APUs or the memory controllers (so 543 * VRAM is not lost). Not available on all ASICs. 544 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 545 * but without powering off the PCI bus. Suitable only for 546 * discrete GPUs. 547 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 548 * and does a secondary bus reset or FLR, depending on what the 549 * underlying hardware supports. 550 * 551 * Methods available for AMD GPU driver for resetting the device. Not all 552 * methods are suitable for every device. User can override the method using 553 * module parameter `reset_method`. 554 */ 555 enum amd_reset_method { 556 AMD_RESET_METHOD_NONE = -1, 557 AMD_RESET_METHOD_LEGACY = 0, 558 AMD_RESET_METHOD_MODE0, 559 AMD_RESET_METHOD_MODE1, 560 AMD_RESET_METHOD_MODE2, 561 AMD_RESET_METHOD_BACO, 562 AMD_RESET_METHOD_PCI, 563 }; 564 565 struct amdgpu_video_codec_info { 566 u32 codec_type; 567 u32 max_width; 568 u32 max_height; 569 u32 max_pixels_per_frame; 570 u32 max_level; 571 }; 572 573 #define codec_info_build(type, width, height, level) \ 574 .codec_type = type,\ 575 .max_width = width,\ 576 .max_height = height,\ 577 .max_pixels_per_frame = height * width,\ 578 .max_level = level, 579 580 struct amdgpu_video_codecs { 581 const u32 codec_count; 582 const struct amdgpu_video_codec_info *codec_array; 583 }; 584 585 /* 586 * ASIC specific functions. 587 */ 588 struct amdgpu_asic_funcs { 589 bool (*read_disabled_bios)(struct amdgpu_device *adev); 590 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 591 u8 *bios, u32 length_bytes); 592 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 593 u32 sh_num, u32 reg_offset, u32 *value); 594 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 595 int (*reset)(struct amdgpu_device *adev); 596 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 597 /* get the reference clock */ 598 u32 (*get_xclk)(struct amdgpu_device *adev); 599 /* MM block clocks */ 600 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 601 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 602 /* static power management */ 603 int (*get_pcie_lanes)(struct amdgpu_device *adev); 604 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 605 /* get config memsize register */ 606 u32 (*get_config_memsize)(struct amdgpu_device *adev); 607 /* flush hdp write queue */ 608 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 609 /* invalidate hdp read cache */ 610 void (*invalidate_hdp)(struct amdgpu_device *adev, 611 struct amdgpu_ring *ring); 612 /* check if the asic needs a full reset of if soft reset will work */ 613 bool (*need_full_reset)(struct amdgpu_device *adev); 614 /* initialize doorbell layout for specific asic*/ 615 void (*init_doorbell_index)(struct amdgpu_device *adev); 616 /* PCIe bandwidth usage */ 617 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 618 uint64_t *count1); 619 /* do we need to reset the asic at init time (e.g., kexec) */ 620 bool (*need_reset_on_init)(struct amdgpu_device *adev); 621 /* PCIe replay counter */ 622 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 623 /* device supports BACO */ 624 int (*supports_baco)(struct amdgpu_device *adev); 625 /* pre asic_init quirks */ 626 void (*pre_asic_init)(struct amdgpu_device *adev); 627 /* enter/exit umd stable pstate */ 628 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 629 /* query video codecs */ 630 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 631 const struct amdgpu_video_codecs **codecs); 632 /* encode "> 32bits" smn addressing */ 633 u64 (*encode_ext_smn_addressing)(int ext_id); 634 635 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 636 enum amdgpu_reg_state reg_state, void *buf, 637 size_t max_size); 638 }; 639 640 /* 641 * IOCTL. 642 */ 643 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 644 struct drm_file *filp); 645 646 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 647 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 648 struct drm_file *filp); 649 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 650 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 651 struct drm_file *filp); 652 653 /* VRAM scratch page for HDP bug, default vram page */ 654 struct amdgpu_mem_scratch { 655 struct amdgpu_bo *robj; 656 volatile uint32_t *ptr; 657 u64 gpu_addr; 658 }; 659 660 /* 661 * CGS 662 */ 663 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 664 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 665 666 /* 667 * Core structure, functions and helpers. 668 */ 669 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 670 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 671 672 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 673 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 674 675 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 676 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 677 678 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 679 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 680 681 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 682 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 683 684 struct amdgpu_mmio_remap { 685 u32 reg_offset; 686 resource_size_t bus_addr; 687 }; 688 689 /* Define the HW IP blocks will be used in driver , add more if necessary */ 690 enum amd_hw_ip_block_type { 691 GC_HWIP = 1, 692 HDP_HWIP, 693 SDMA0_HWIP, 694 SDMA1_HWIP, 695 SDMA2_HWIP, 696 SDMA3_HWIP, 697 SDMA4_HWIP, 698 SDMA5_HWIP, 699 SDMA6_HWIP, 700 SDMA7_HWIP, 701 LSDMA_HWIP, 702 MMHUB_HWIP, 703 ATHUB_HWIP, 704 NBIO_HWIP, 705 MP0_HWIP, 706 MP1_HWIP, 707 UVD_HWIP, 708 VCN_HWIP = UVD_HWIP, 709 JPEG_HWIP = VCN_HWIP, 710 VCN1_HWIP, 711 VCE_HWIP, 712 VPE_HWIP, 713 DF_HWIP, 714 DCE_HWIP, 715 OSSSYS_HWIP, 716 SMUIO_HWIP, 717 PWR_HWIP, 718 NBIF_HWIP, 719 THM_HWIP, 720 CLK_HWIP, 721 UMC_HWIP, 722 RSMU_HWIP, 723 XGMI_HWIP, 724 DCI_HWIP, 725 PCIE_HWIP, 726 ISP_HWIP, 727 MAX_HWIP 728 }; 729 730 #define HWIP_MAX_INSTANCE 44 731 732 #define HW_ID_MAX 300 733 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 734 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 735 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 736 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 737 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 738 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 739 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 740 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 741 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 742 743 struct amdgpu_ip_map_info { 744 /* Map of logical to actual dev instances/mask */ 745 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 746 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 747 enum amd_hw_ip_block_type block, 748 int8_t inst); 749 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 750 enum amd_hw_ip_block_type block, 751 uint32_t mask); 752 }; 753 754 struct amd_powerplay { 755 void *pp_handle; 756 const struct amd_pm_funcs *pp_funcs; 757 }; 758 759 struct ip_discovery_top; 760 761 /* polaris10 kickers */ 762 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 763 ((rid == 0xE3) || \ 764 (rid == 0xE4) || \ 765 (rid == 0xE5) || \ 766 (rid == 0xE7) || \ 767 (rid == 0xEF))) || \ 768 ((did == 0x6FDF) && \ 769 ((rid == 0xE7) || \ 770 (rid == 0xEF) || \ 771 (rid == 0xFF)))) 772 773 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 774 ((rid == 0xE1) || \ 775 (rid == 0xF7))) 776 777 /* polaris11 kickers */ 778 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 779 ((rid == 0xE0) || \ 780 (rid == 0xE5))) || \ 781 ((did == 0x67FF) && \ 782 ((rid == 0xCF) || \ 783 (rid == 0xEF) || \ 784 (rid == 0xFF)))) 785 786 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 787 ((rid == 0xE2))) 788 789 /* polaris12 kickers */ 790 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 791 ((rid == 0xC0) || \ 792 (rid == 0xC1) || \ 793 (rid == 0xC3) || \ 794 (rid == 0xC7))) || \ 795 ((did == 0x6981) && \ 796 ((rid == 0x00) || \ 797 (rid == 0x01) || \ 798 (rid == 0x10)))) 799 800 struct amdgpu_mqd_prop { 801 uint64_t mqd_gpu_addr; 802 uint64_t hqd_base_gpu_addr; 803 uint64_t rptr_gpu_addr; 804 uint64_t wptr_gpu_addr; 805 uint32_t queue_size; 806 bool use_doorbell; 807 uint32_t doorbell_index; 808 uint64_t eop_gpu_addr; 809 uint32_t hqd_pipe_priority; 810 uint32_t hqd_queue_priority; 811 bool allow_tunneling; 812 bool hqd_active; 813 }; 814 815 struct amdgpu_mqd { 816 unsigned mqd_size; 817 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 818 struct amdgpu_mqd_prop *p); 819 }; 820 821 #define AMDGPU_RESET_MAGIC_NUM 64 822 #define AMDGPU_MAX_DF_PERFMONS 4 823 struct amdgpu_reset_domain; 824 struct amdgpu_fru_info; 825 826 struct amdgpu_reset_info { 827 /* reset dump register */ 828 u32 *reset_dump_reg_list; 829 u32 *reset_dump_reg_value; 830 int num_regs; 831 832 #ifdef CONFIG_DEV_COREDUMP 833 struct amdgpu_coredump_info *coredump_info; 834 #endif 835 }; 836 837 /* 838 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 839 */ 840 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 841 842 struct amdgpu_device { 843 struct device *dev; 844 struct pci_dev *pdev; 845 struct drm_device ddev; 846 847 #ifdef CONFIG_DRM_AMD_ACP 848 struct amdgpu_acp acp; 849 #endif 850 struct amdgpu_hive_info *hive; 851 struct amdgpu_xcp_mgr *xcp_mgr; 852 /* ASIC */ 853 enum amd_asic_type asic_type; 854 uint32_t family; 855 uint32_t rev_id; 856 uint32_t external_rev_id; 857 unsigned long flags; 858 unsigned long apu_flags; 859 int usec_timeout; 860 const struct amdgpu_asic_funcs *asic_funcs; 861 bool shutdown; 862 bool need_swiotlb; 863 bool accel_working; 864 struct notifier_block acpi_nb; 865 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 866 struct debugfs_blob_wrapper debugfs_vbios_blob; 867 struct debugfs_blob_wrapper debugfs_discovery_blob; 868 struct mutex srbm_mutex; 869 /* GRBM index mutex. Protects concurrent access to GRBM index */ 870 struct mutex grbm_idx_mutex; 871 struct dev_pm_domain vga_pm_domain; 872 bool have_disp_power_ref; 873 bool have_atomics_support; 874 875 /* BIOS */ 876 bool is_atom_fw; 877 uint8_t *bios; 878 uint32_t bios_size; 879 uint32_t bios_scratch_reg_offset; 880 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 881 882 /* Register/doorbell mmio */ 883 resource_size_t rmmio_base; 884 resource_size_t rmmio_size; 885 void __iomem *rmmio; 886 /* protects concurrent MM_INDEX/DATA based register access */ 887 spinlock_t mmio_idx_lock; 888 struct amdgpu_mmio_remap rmmio_remap; 889 /* protects concurrent SMC based register access */ 890 spinlock_t smc_idx_lock; 891 amdgpu_rreg_t smc_rreg; 892 amdgpu_wreg_t smc_wreg; 893 /* protects concurrent PCIE register access */ 894 spinlock_t pcie_idx_lock; 895 amdgpu_rreg_t pcie_rreg; 896 amdgpu_wreg_t pcie_wreg; 897 amdgpu_rreg_t pciep_rreg; 898 amdgpu_wreg_t pciep_wreg; 899 amdgpu_rreg_ext_t pcie_rreg_ext; 900 amdgpu_wreg_ext_t pcie_wreg_ext; 901 amdgpu_rreg64_t pcie_rreg64; 902 amdgpu_wreg64_t pcie_wreg64; 903 amdgpu_rreg64_ext_t pcie_rreg64_ext; 904 amdgpu_wreg64_ext_t pcie_wreg64_ext; 905 /* protects concurrent UVD register access */ 906 spinlock_t uvd_ctx_idx_lock; 907 amdgpu_rreg_t uvd_ctx_rreg; 908 amdgpu_wreg_t uvd_ctx_wreg; 909 /* protects concurrent DIDT register access */ 910 spinlock_t didt_idx_lock; 911 amdgpu_rreg_t didt_rreg; 912 amdgpu_wreg_t didt_wreg; 913 /* protects concurrent gc_cac register access */ 914 spinlock_t gc_cac_idx_lock; 915 amdgpu_rreg_t gc_cac_rreg; 916 amdgpu_wreg_t gc_cac_wreg; 917 /* protects concurrent se_cac register access */ 918 spinlock_t se_cac_idx_lock; 919 amdgpu_rreg_t se_cac_rreg; 920 amdgpu_wreg_t se_cac_wreg; 921 /* protects concurrent ENDPOINT (audio) register access */ 922 spinlock_t audio_endpt_idx_lock; 923 amdgpu_block_rreg_t audio_endpt_rreg; 924 amdgpu_block_wreg_t audio_endpt_wreg; 925 struct amdgpu_doorbell doorbell; 926 927 /* clock/pll info */ 928 struct amdgpu_clock clock; 929 930 /* MC */ 931 struct amdgpu_gmc gmc; 932 struct amdgpu_gart gart; 933 dma_addr_t dummy_page_addr; 934 struct amdgpu_vm_manager vm_manager; 935 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 936 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 937 938 /* memory management */ 939 struct amdgpu_mman mman; 940 struct amdgpu_mem_scratch mem_scratch; 941 struct amdgpu_wb wb; 942 atomic64_t num_bytes_moved; 943 atomic64_t num_evictions; 944 atomic64_t num_vram_cpu_page_faults; 945 atomic_t gpu_reset_counter; 946 atomic_t vram_lost_counter; 947 948 /* data for buffer migration throttling */ 949 struct { 950 spinlock_t lock; 951 s64 last_update_us; 952 s64 accum_us; /* accumulated microseconds */ 953 s64 accum_us_vis; /* for visible VRAM */ 954 u32 log2_max_MBps; 955 } mm_stats; 956 957 /* display */ 958 bool enable_virtual_display; 959 struct amdgpu_vkms_output *amdgpu_vkms_output; 960 struct amdgpu_mode_info mode_info; 961 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 962 struct delayed_work hotplug_work; 963 struct amdgpu_irq_src crtc_irq; 964 struct amdgpu_irq_src vline0_irq; 965 struct amdgpu_irq_src vupdate_irq; 966 struct amdgpu_irq_src pageflip_irq; 967 struct amdgpu_irq_src hpd_irq; 968 struct amdgpu_irq_src dmub_trace_irq; 969 struct amdgpu_irq_src dmub_outbox_irq; 970 971 /* rings */ 972 u64 fence_context; 973 unsigned num_rings; 974 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 975 struct dma_fence __rcu *gang_submit; 976 bool ib_pool_ready; 977 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 978 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 979 980 /* interrupts */ 981 struct amdgpu_irq irq; 982 983 /* powerplay */ 984 struct amd_powerplay powerplay; 985 struct amdgpu_pm pm; 986 u64 cg_flags; 987 u32 pg_flags; 988 989 /* nbio */ 990 struct amdgpu_nbio nbio; 991 992 /* hdp */ 993 struct amdgpu_hdp hdp; 994 995 /* smuio */ 996 struct amdgpu_smuio smuio; 997 998 /* mmhub */ 999 struct amdgpu_mmhub mmhub; 1000 1001 /* gfxhub */ 1002 struct amdgpu_gfxhub gfxhub; 1003 1004 /* gfx */ 1005 struct amdgpu_gfx gfx; 1006 1007 /* sdma */ 1008 struct amdgpu_sdma sdma; 1009 1010 /* lsdma */ 1011 struct amdgpu_lsdma lsdma; 1012 1013 /* uvd */ 1014 struct amdgpu_uvd uvd; 1015 1016 /* vce */ 1017 struct amdgpu_vce vce; 1018 1019 /* vcn */ 1020 struct amdgpu_vcn vcn; 1021 1022 /* jpeg */ 1023 struct amdgpu_jpeg jpeg; 1024 1025 /* vpe */ 1026 struct amdgpu_vpe vpe; 1027 1028 /* umsch */ 1029 struct amdgpu_umsch_mm umsch_mm; 1030 bool enable_umsch_mm; 1031 1032 /* firmwares */ 1033 struct amdgpu_firmware firmware; 1034 1035 /* PSP */ 1036 struct psp_context psp; 1037 1038 /* GDS */ 1039 struct amdgpu_gds gds; 1040 1041 /* for userq and VM fences */ 1042 struct amdgpu_seq64 seq64; 1043 1044 /* KFD */ 1045 struct amdgpu_kfd_dev kfd; 1046 1047 /* UMC */ 1048 struct amdgpu_umc umc; 1049 1050 /* display related functionality */ 1051 struct amdgpu_display_manager dm; 1052 1053 #if defined(CONFIG_DRM_AMD_ISP) 1054 /* isp */ 1055 struct amdgpu_isp isp; 1056 #endif 1057 1058 /* mes */ 1059 bool enable_mes; 1060 bool enable_mes_kiq; 1061 bool enable_uni_mes; 1062 struct amdgpu_mes mes; 1063 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1064 1065 /* df */ 1066 struct amdgpu_df df; 1067 1068 /* MCA */ 1069 struct amdgpu_mca mca; 1070 1071 /* ACA */ 1072 struct amdgpu_aca aca; 1073 1074 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1075 uint32_t harvest_ip_mask; 1076 int num_ip_blocks; 1077 struct mutex mn_lock; 1078 DECLARE_HASHTABLE(mn_hash, 7); 1079 1080 /* tracking pinned memory */ 1081 atomic64_t vram_pin_size; 1082 atomic64_t visible_pin_size; 1083 atomic64_t gart_pin_size; 1084 1085 /* soc15 register offset based on ip, instance and segment */ 1086 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1087 struct amdgpu_ip_map_info ip_map; 1088 1089 /* delayed work_func for deferring clockgating during resume */ 1090 struct delayed_work delayed_init_work; 1091 1092 struct amdgpu_virt virt; 1093 1094 /* link all shadow bo */ 1095 struct list_head shadow_list; 1096 struct mutex shadow_list_lock; 1097 1098 /* record hw reset is performed */ 1099 bool has_hw_reset; 1100 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1101 1102 /* s3/s4 mask */ 1103 bool in_suspend; 1104 bool in_s3; 1105 bool in_s4; 1106 bool in_s0ix; 1107 /* indicate amdgpu suspension status */ 1108 bool suspend_complete; 1109 1110 enum pp_mp1_state mp1_state; 1111 struct amdgpu_doorbell_index doorbell_index; 1112 1113 struct mutex notifier_lock; 1114 1115 int asic_reset_res; 1116 struct work_struct xgmi_reset_work; 1117 struct list_head reset_list; 1118 1119 long gfx_timeout; 1120 long sdma_timeout; 1121 long video_timeout; 1122 long compute_timeout; 1123 long psp_timeout; 1124 1125 uint64_t unique_id; 1126 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1127 1128 /* enable runtime pm on the device */ 1129 bool in_runpm; 1130 bool has_pr3; 1131 1132 bool ucode_sysfs_en; 1133 1134 struct amdgpu_fru_info *fru_info; 1135 atomic_t throttling_logging_enabled; 1136 struct ratelimit_state throttling_logging_rs; 1137 uint32_t ras_hw_enabled; 1138 uint32_t ras_enabled; 1139 1140 bool no_hw_access; 1141 struct pci_saved_state *pci_state; 1142 pci_channel_state_t pci_channel_state; 1143 1144 /* Track auto wait count on s_barrier settings */ 1145 bool barrier_has_auto_waitcnt; 1146 1147 struct amdgpu_reset_control *reset_cntl; 1148 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1149 1150 bool ram_is_direct_mapped; 1151 1152 struct list_head ras_list; 1153 1154 struct ip_discovery_top *ip_top; 1155 1156 struct amdgpu_reset_domain *reset_domain; 1157 1158 struct mutex benchmark_mutex; 1159 1160 struct amdgpu_reset_info reset_info; 1161 1162 bool scpm_enabled; 1163 uint32_t scpm_status; 1164 1165 struct work_struct reset_work; 1166 1167 bool job_hang; 1168 bool dc_enabled; 1169 /* Mask of active clusters */ 1170 uint32_t aid_mask; 1171 1172 /* Debug */ 1173 bool debug_vm; 1174 bool debug_largebar; 1175 bool debug_disable_soft_recovery; 1176 bool debug_use_vram_fw_buf; 1177 bool debug_enable_ras_aca; 1178 }; 1179 1180 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1181 uint8_t ip, uint8_t inst) 1182 { 1183 /* This considers only major/minor/rev and ignores 1184 * subrevision/variant fields. 1185 */ 1186 return adev->ip_versions[ip][inst] & ~0xFFU; 1187 } 1188 1189 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1190 uint8_t ip, uint8_t inst) 1191 { 1192 /* This returns full version - major/minor/rev/variant/subrevision */ 1193 return adev->ip_versions[ip][inst]; 1194 } 1195 1196 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1197 { 1198 return container_of(ddev, struct amdgpu_device, ddev); 1199 } 1200 1201 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1202 { 1203 return &adev->ddev; 1204 } 1205 1206 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1207 { 1208 return container_of(bdev, struct amdgpu_device, mman.bdev); 1209 } 1210 1211 int amdgpu_device_init(struct amdgpu_device *adev, 1212 uint32_t flags); 1213 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1214 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1215 1216 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1217 1218 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1219 void *buf, size_t size, bool write); 1220 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1221 void *buf, size_t size, bool write); 1222 1223 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1224 void *buf, size_t size, bool write); 1225 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1226 uint32_t inst, uint32_t reg_addr, char reg_name[], 1227 uint32_t expected_value, uint32_t mask); 1228 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1229 uint32_t reg, uint32_t acc_flags); 1230 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1231 u64 reg_addr); 1232 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1233 uint32_t reg, uint32_t acc_flags, 1234 uint32_t xcc_id); 1235 void amdgpu_device_wreg(struct amdgpu_device *adev, 1236 uint32_t reg, uint32_t v, 1237 uint32_t acc_flags); 1238 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1239 u64 reg_addr, u32 reg_data); 1240 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1241 uint32_t reg, uint32_t v, 1242 uint32_t acc_flags, 1243 uint32_t xcc_id); 1244 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1245 uint32_t reg, uint32_t v, uint32_t xcc_id); 1246 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1247 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1248 1249 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1250 u32 reg_addr); 1251 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1252 u32 reg_addr); 1253 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1254 u64 reg_addr); 1255 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1256 u32 reg_addr, u32 reg_data); 1257 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1258 u32 reg_addr, u64 reg_data); 1259 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1260 u64 reg_addr, u64 reg_data); 1261 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1262 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1263 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1264 1265 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1266 1267 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1268 struct amdgpu_reset_context *reset_context); 1269 1270 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1271 struct amdgpu_reset_context *reset_context); 1272 1273 int emu_soc_asic_init(struct amdgpu_device *adev); 1274 1275 /* 1276 * Registers read & write functions. 1277 */ 1278 #define AMDGPU_REGS_NO_KIQ (1<<1) 1279 #define AMDGPU_REGS_RLC (1<<2) 1280 1281 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1282 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1283 1284 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1285 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1286 1287 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1288 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1289 1290 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1291 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1292 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1293 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1294 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1295 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1296 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1297 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1298 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1299 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1300 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1301 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1302 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1303 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1304 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1305 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1306 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1307 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1308 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1309 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1310 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1311 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1312 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1313 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1314 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1315 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1316 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1317 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1318 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1319 #define WREG32_P(reg, val, mask) \ 1320 do { \ 1321 uint32_t tmp_ = RREG32(reg); \ 1322 tmp_ &= (mask); \ 1323 tmp_ |= ((val) & ~(mask)); \ 1324 WREG32(reg, tmp_); \ 1325 } while (0) 1326 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1327 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1328 #define WREG32_PLL_P(reg, val, mask) \ 1329 do { \ 1330 uint32_t tmp_ = RREG32_PLL(reg); \ 1331 tmp_ &= (mask); \ 1332 tmp_ |= ((val) & ~(mask)); \ 1333 WREG32_PLL(reg, tmp_); \ 1334 } while (0) 1335 1336 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1337 do { \ 1338 u32 tmp = RREG32_SMC(_Reg); \ 1339 tmp &= (_Mask); \ 1340 tmp |= ((_Val) & ~(_Mask)); \ 1341 WREG32_SMC(_Reg, tmp); \ 1342 } while (0) 1343 1344 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1345 1346 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1347 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1348 1349 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1350 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1351 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1352 1353 #define REG_GET_FIELD(value, reg, field) \ 1354 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1355 1356 #define WREG32_FIELD(reg, field, val) \ 1357 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1358 1359 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1360 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1361 1362 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1363 /* 1364 * BIOS helpers. 1365 */ 1366 #define RBIOS8(i) (adev->bios[i]) 1367 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1368 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1369 1370 /* 1371 * ASICs macro. 1372 */ 1373 #define amdgpu_asic_set_vga_state(adev, state) \ 1374 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1375 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1376 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1377 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1378 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1379 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1380 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1381 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1382 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1383 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1384 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1385 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1386 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1387 #define amdgpu_asic_flush_hdp(adev, r) \ 1388 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1389 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1390 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1391 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1392 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1393 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1394 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1395 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1396 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1397 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1398 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1399 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1400 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1401 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1402 1403 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1404 1405 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1406 #define for_each_inst(i, inst_mask) \ 1407 for (i = ffs(inst_mask); i-- != 0; \ 1408 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1409 1410 /* Common functions */ 1411 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1412 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1413 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1414 struct amdgpu_job *job, 1415 struct amdgpu_reset_context *reset_context); 1416 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1417 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1418 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1419 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1420 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1421 1422 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1423 u64 num_vis_bytes); 1424 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1425 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1426 const u32 *registers, 1427 const u32 array_size); 1428 1429 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1430 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1431 bool amdgpu_device_supports_px(struct drm_device *dev); 1432 bool amdgpu_device_supports_boco(struct drm_device *dev); 1433 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1434 int amdgpu_device_supports_baco(struct drm_device *dev); 1435 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1436 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1437 struct amdgpu_device *peer_adev); 1438 int amdgpu_device_baco_enter(struct drm_device *dev); 1439 int amdgpu_device_baco_exit(struct drm_device *dev); 1440 1441 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1442 struct amdgpu_ring *ring); 1443 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1444 struct amdgpu_ring *ring); 1445 1446 void amdgpu_device_halt(struct amdgpu_device *adev); 1447 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1448 u32 reg); 1449 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1450 u32 reg, u32 v); 1451 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1452 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1453 struct dma_fence *gang); 1454 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1455 1456 /* atpx handler */ 1457 #if defined(CONFIG_VGA_SWITCHEROO) 1458 void amdgpu_register_atpx_handler(void); 1459 void amdgpu_unregister_atpx_handler(void); 1460 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1461 bool amdgpu_is_atpx_hybrid(void); 1462 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1463 bool amdgpu_has_atpx(void); 1464 #else 1465 static inline void amdgpu_register_atpx_handler(void) {} 1466 static inline void amdgpu_unregister_atpx_handler(void) {} 1467 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1468 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1469 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1470 static inline bool amdgpu_has_atpx(void) { return false; } 1471 #endif 1472 1473 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1474 void *amdgpu_atpx_get_dhandle(void); 1475 #else 1476 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1477 #endif 1478 1479 /* 1480 * KMS 1481 */ 1482 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1483 extern const int amdgpu_max_kms_ioctl; 1484 1485 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1486 void amdgpu_driver_unload_kms(struct drm_device *dev); 1487 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1488 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1489 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1490 struct drm_file *file_priv); 1491 void amdgpu_driver_release_kms(struct drm_device *dev); 1492 1493 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1494 int amdgpu_device_prepare(struct drm_device *dev); 1495 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1496 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1497 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1498 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1499 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1500 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1501 struct drm_file *filp); 1502 1503 /* 1504 * functions used by amdgpu_encoder.c 1505 */ 1506 struct amdgpu_afmt_acr { 1507 u32 clock; 1508 1509 int n_32khz; 1510 int cts_32khz; 1511 1512 int n_44_1khz; 1513 int cts_44_1khz; 1514 1515 int n_48khz; 1516 int cts_48khz; 1517 1518 }; 1519 1520 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1521 1522 /* amdgpu_acpi.c */ 1523 1524 struct amdgpu_numa_info { 1525 uint64_t size; 1526 int pxm; 1527 int nid; 1528 }; 1529 1530 /* ATCS Device/Driver State */ 1531 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1532 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1533 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1534 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1535 1536 #if defined(CONFIG_ACPI) 1537 int amdgpu_acpi_init(struct amdgpu_device *adev); 1538 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1539 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1540 bool amdgpu_acpi_is_power_shift_control_supported(void); 1541 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1542 u8 perf_req, bool advertise); 1543 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1544 u8 dev_state, bool drv_state); 1545 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1546 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1547 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1548 u64 *tmr_size); 1549 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1550 struct amdgpu_numa_info *numa_info); 1551 1552 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1553 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1554 void amdgpu_acpi_detect(void); 1555 void amdgpu_acpi_release(void); 1556 #else 1557 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1558 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1559 u64 *tmr_offset, u64 *tmr_size) 1560 { 1561 return -EINVAL; 1562 } 1563 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1564 int xcc_id, 1565 struct amdgpu_numa_info *numa_info) 1566 { 1567 return -EINVAL; 1568 } 1569 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1570 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1571 static inline void amdgpu_acpi_detect(void) { } 1572 static inline void amdgpu_acpi_release(void) { } 1573 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1574 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1575 u8 dev_state, bool drv_state) { return 0; } 1576 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1577 enum amdgpu_ss ss_state) { return 0; } 1578 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1579 #endif 1580 1581 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1582 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1583 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1584 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1585 #else 1586 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1587 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1588 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1589 #endif 1590 1591 #if defined(CONFIG_DRM_AMD_DC) 1592 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1593 #else 1594 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1595 #endif 1596 1597 1598 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1599 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1600 1601 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1602 pci_channel_state_t state); 1603 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1604 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1605 void amdgpu_pci_resume(struct pci_dev *pdev); 1606 1607 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1608 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1609 1610 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1611 1612 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1613 enum amd_clockgating_state state); 1614 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1615 enum amd_powergating_state state); 1616 1617 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1618 { 1619 return amdgpu_gpu_recovery != 0 && 1620 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1621 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1622 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1623 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1624 } 1625 1626 #include "amdgpu_object.h" 1627 1628 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1629 { 1630 return adev->gmc.tmz_enabled; 1631 } 1632 1633 int amdgpu_in_reset(struct amdgpu_device *adev); 1634 1635 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1636 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1637 extern const struct attribute_group amdgpu_flash_attr_group; 1638 1639 #endif 1640