1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_fdinfo.h" 111 112 #define MAX_GPU_INSTANCE 16 113 114 struct amdgpu_gpu_instance 115 { 116 struct amdgpu_device *adev; 117 int mgpu_fan_enabled; 118 }; 119 120 struct amdgpu_mgpu_info 121 { 122 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 123 struct mutex mutex; 124 uint32_t num_gpu; 125 uint32_t num_dgpu; 126 uint32_t num_apu; 127 128 /* delayed reset_func for XGMI configuration if necessary */ 129 struct delayed_work delayed_reset_work; 130 bool pending_reset; 131 }; 132 133 struct amdgpu_watchdog_timer 134 { 135 bool timeout_fatal_disable; 136 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 137 }; 138 139 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 140 141 /* 142 * Modules parameters. 143 */ 144 extern int amdgpu_modeset; 145 extern int amdgpu_vram_limit; 146 extern int amdgpu_vis_vram_limit; 147 extern int amdgpu_gart_size; 148 extern int amdgpu_gtt_size; 149 extern int amdgpu_moverate; 150 extern int amdgpu_benchmarking; 151 extern int amdgpu_testing; 152 extern int amdgpu_audio; 153 extern int amdgpu_disp_priority; 154 extern int amdgpu_hw_i2c; 155 extern int amdgpu_pcie_gen2; 156 extern int amdgpu_msi; 157 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 158 extern int amdgpu_dpm; 159 extern int amdgpu_fw_load_type; 160 extern int amdgpu_aspm; 161 extern int amdgpu_runtime_pm; 162 extern uint amdgpu_ip_block_mask; 163 extern int amdgpu_bapm; 164 extern int amdgpu_deep_color; 165 extern int amdgpu_vm_size; 166 extern int amdgpu_vm_block_size; 167 extern int amdgpu_vm_fragment_size; 168 extern int amdgpu_vm_fault_stop; 169 extern int amdgpu_vm_debug; 170 extern int amdgpu_vm_update_mode; 171 extern int amdgpu_exp_hw_support; 172 extern int amdgpu_dc; 173 extern int amdgpu_sched_jobs; 174 extern int amdgpu_sched_hw_submission; 175 extern uint amdgpu_pcie_gen_cap; 176 extern uint amdgpu_pcie_lane_cap; 177 extern uint amdgpu_cg_mask; 178 extern uint amdgpu_pg_mask; 179 extern uint amdgpu_sdma_phase_quantum; 180 extern char *amdgpu_disable_cu; 181 extern char *amdgpu_virtual_display; 182 extern uint amdgpu_pp_feature_mask; 183 extern uint amdgpu_force_long_training; 184 extern int amdgpu_job_hang_limit; 185 extern int amdgpu_lbpw; 186 extern int amdgpu_compute_multipipe; 187 extern int amdgpu_gpu_recovery; 188 extern int amdgpu_emu_mode; 189 extern uint amdgpu_smu_memory_pool_size; 190 extern int amdgpu_smu_pptable_id; 191 extern uint amdgpu_dc_feature_mask; 192 extern uint amdgpu_freesync_vid_mode; 193 extern uint amdgpu_dc_debug_mask; 194 extern uint amdgpu_dm_abm_level; 195 extern int amdgpu_backlight; 196 extern struct amdgpu_mgpu_info mgpu_info; 197 extern int amdgpu_ras_enable; 198 extern uint amdgpu_ras_mask; 199 extern int amdgpu_bad_page_threshold; 200 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 201 extern int amdgpu_async_gfx_ring; 202 extern int amdgpu_mcbp; 203 extern int amdgpu_discovery; 204 extern int amdgpu_mes; 205 extern int amdgpu_noretry; 206 extern int amdgpu_force_asic_type; 207 #ifdef CONFIG_HSA_AMD 208 extern int sched_policy; 209 extern bool debug_evictions; 210 extern bool no_system_mem_limit; 211 #else 212 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 213 static const bool __maybe_unused debug_evictions; /* = false */ 214 static const bool __maybe_unused no_system_mem_limit; 215 #endif 216 217 extern int amdgpu_tmz; 218 extern int amdgpu_reset_method; 219 220 #ifdef CONFIG_DRM_AMDGPU_SI 221 extern int amdgpu_si_support; 222 #endif 223 #ifdef CONFIG_DRM_AMDGPU_CIK 224 extern int amdgpu_cik_support; 225 #endif 226 extern int amdgpu_num_kcq; 227 228 #define AMDGPU_VM_MAX_NUM_CTX 4096 229 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 230 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 231 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 232 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 233 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 234 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 235 #define AMDGPUFB_CONN_LIMIT 4 236 #define AMDGPU_BIOS_NUM_SCRATCH 16 237 238 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 239 240 /* hard reset data */ 241 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 242 243 /* reset flags */ 244 #define AMDGPU_RESET_GFX (1 << 0) 245 #define AMDGPU_RESET_COMPUTE (1 << 1) 246 #define AMDGPU_RESET_DMA (1 << 2) 247 #define AMDGPU_RESET_CP (1 << 3) 248 #define AMDGPU_RESET_GRBM (1 << 4) 249 #define AMDGPU_RESET_DMA1 (1 << 5) 250 #define AMDGPU_RESET_RLC (1 << 6) 251 #define AMDGPU_RESET_SEM (1 << 7) 252 #define AMDGPU_RESET_IH (1 << 8) 253 #define AMDGPU_RESET_VMC (1 << 9) 254 #define AMDGPU_RESET_MC (1 << 10) 255 #define AMDGPU_RESET_DISPLAY (1 << 11) 256 #define AMDGPU_RESET_UVD (1 << 12) 257 #define AMDGPU_RESET_VCE (1 << 13) 258 #define AMDGPU_RESET_VCE1 (1 << 14) 259 260 /* max cursor sizes (in pixels) */ 261 #define CIK_CURSOR_WIDTH 128 262 #define CIK_CURSOR_HEIGHT 128 263 264 struct amdgpu_device; 265 struct amdgpu_ib; 266 struct amdgpu_cs_parser; 267 struct amdgpu_job; 268 struct amdgpu_irq_src; 269 struct amdgpu_fpriv; 270 struct amdgpu_bo_va_mapping; 271 struct amdgpu_atif; 272 struct kfd_vm_fault_info; 273 struct amdgpu_hive_info; 274 struct amdgpu_reset_context; 275 struct amdgpu_reset_control; 276 277 enum amdgpu_cp_irq { 278 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 279 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 280 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 281 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 282 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 283 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 284 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 285 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 286 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 287 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 288 289 AMDGPU_CP_IRQ_LAST 290 }; 291 292 enum amdgpu_thermal_irq { 293 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 294 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 295 296 AMDGPU_THERMAL_IRQ_LAST 297 }; 298 299 enum amdgpu_kiq_irq { 300 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 301 AMDGPU_CP_KIQ_IRQ_LAST 302 }; 303 304 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 305 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 306 #define MAX_KIQ_REG_TRY 1000 307 308 int amdgpu_device_ip_set_clockgating_state(void *dev, 309 enum amd_ip_block_type block_type, 310 enum amd_clockgating_state state); 311 int amdgpu_device_ip_set_powergating_state(void *dev, 312 enum amd_ip_block_type block_type, 313 enum amd_powergating_state state); 314 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 315 u32 *flags); 316 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 317 enum amd_ip_block_type block_type); 318 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 319 enum amd_ip_block_type block_type); 320 321 #define AMDGPU_MAX_IP_NUM 16 322 323 struct amdgpu_ip_block_status { 324 bool valid; 325 bool sw; 326 bool hw; 327 bool late_initialized; 328 bool hang; 329 }; 330 331 struct amdgpu_ip_block_version { 332 const enum amd_ip_block_type type; 333 const u32 major; 334 const u32 minor; 335 const u32 rev; 336 const struct amd_ip_funcs *funcs; 337 }; 338 339 #define HW_REV(_Major, _Minor, _Rev) \ 340 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 341 342 struct amdgpu_ip_block { 343 struct amdgpu_ip_block_status status; 344 const struct amdgpu_ip_block_version *version; 345 }; 346 347 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 348 enum amd_ip_block_type type, 349 u32 major, u32 minor); 350 351 struct amdgpu_ip_block * 352 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 353 enum amd_ip_block_type type); 354 355 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 356 const struct amdgpu_ip_block_version *ip_block_version); 357 358 /* 359 * BIOS. 360 */ 361 bool amdgpu_get_bios(struct amdgpu_device *adev); 362 bool amdgpu_read_bios(struct amdgpu_device *adev); 363 364 /* 365 * Clocks 366 */ 367 368 #define AMDGPU_MAX_PPLL 3 369 370 struct amdgpu_clock { 371 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 372 struct amdgpu_pll spll; 373 struct amdgpu_pll mpll; 374 /* 10 Khz units */ 375 uint32_t default_mclk; 376 uint32_t default_sclk; 377 uint32_t default_dispclk; 378 uint32_t current_dispclk; 379 uint32_t dp_extclk; 380 uint32_t max_pixel_clock; 381 }; 382 383 /* sub-allocation manager, it has to be protected by another lock. 384 * By conception this is an helper for other part of the driver 385 * like the indirect buffer or semaphore, which both have their 386 * locking. 387 * 388 * Principe is simple, we keep a list of sub allocation in offset 389 * order (first entry has offset == 0, last entry has the highest 390 * offset). 391 * 392 * When allocating new object we first check if there is room at 393 * the end total_size - (last_object_offset + last_object_size) >= 394 * alloc_size. If so we allocate new object there. 395 * 396 * When there is not enough room at the end, we start waiting for 397 * each sub object until we reach object_offset+object_size >= 398 * alloc_size, this object then become the sub object we return. 399 * 400 * Alignment can't be bigger than page size. 401 * 402 * Hole are not considered for allocation to keep things simple. 403 * Assumption is that there won't be hole (all object on same 404 * alignment). 405 */ 406 407 #define AMDGPU_SA_NUM_FENCE_LISTS 32 408 409 struct amdgpu_sa_manager { 410 wait_queue_head_t wq; 411 struct amdgpu_bo *bo; 412 struct list_head *hole; 413 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 414 struct list_head olist; 415 unsigned size; 416 uint64_t gpu_addr; 417 void *cpu_ptr; 418 uint32_t domain; 419 uint32_t align; 420 }; 421 422 /* sub-allocation buffer */ 423 struct amdgpu_sa_bo { 424 struct list_head olist; 425 struct list_head flist; 426 struct amdgpu_sa_manager *manager; 427 unsigned soffset; 428 unsigned eoffset; 429 struct dma_fence *fence; 430 }; 431 432 int amdgpu_fence_slab_init(void); 433 void amdgpu_fence_slab_fini(void); 434 435 /* 436 * IRQS. 437 */ 438 439 struct amdgpu_flip_work { 440 struct delayed_work flip_work; 441 struct work_struct unpin_work; 442 struct amdgpu_device *adev; 443 int crtc_id; 444 u32 target_vblank; 445 uint64_t base; 446 struct drm_pending_vblank_event *event; 447 struct amdgpu_bo *old_abo; 448 struct dma_fence *excl; 449 unsigned shared_count; 450 struct dma_fence **shared; 451 struct dma_fence_cb cb; 452 bool async; 453 }; 454 455 456 /* 457 * CP & rings. 458 */ 459 460 struct amdgpu_ib { 461 struct amdgpu_sa_bo *sa_bo; 462 uint32_t length_dw; 463 uint64_t gpu_addr; 464 uint32_t *ptr; 465 uint32_t flags; 466 }; 467 468 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 469 470 /* 471 * file private structure 472 */ 473 474 struct amdgpu_fpriv { 475 struct amdgpu_vm vm; 476 struct amdgpu_bo_va *prt_va; 477 struct amdgpu_bo_va *csa_va; 478 struct mutex bo_list_lock; 479 struct idr bo_list_handles; 480 struct amdgpu_ctx_mgr ctx_mgr; 481 }; 482 483 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 484 485 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 486 unsigned size, 487 enum amdgpu_ib_pool_type pool, 488 struct amdgpu_ib *ib); 489 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 490 struct dma_fence *f); 491 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 492 struct amdgpu_ib *ibs, struct amdgpu_job *job, 493 struct dma_fence **f); 494 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 495 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 496 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 497 498 /* 499 * CS. 500 */ 501 struct amdgpu_cs_chunk { 502 uint32_t chunk_id; 503 uint32_t length_dw; 504 void *kdata; 505 }; 506 507 struct amdgpu_cs_post_dep { 508 struct drm_syncobj *syncobj; 509 struct dma_fence_chain *chain; 510 u64 point; 511 }; 512 513 struct amdgpu_cs_parser { 514 struct amdgpu_device *adev; 515 struct drm_file *filp; 516 struct amdgpu_ctx *ctx; 517 518 /* chunks */ 519 unsigned nchunks; 520 struct amdgpu_cs_chunk *chunks; 521 522 /* scheduler job object */ 523 struct amdgpu_job *job; 524 struct drm_sched_entity *entity; 525 526 /* buffer objects */ 527 struct ww_acquire_ctx ticket; 528 struct amdgpu_bo_list *bo_list; 529 struct amdgpu_mn *mn; 530 struct amdgpu_bo_list_entry vm_pd; 531 struct list_head validated; 532 struct dma_fence *fence; 533 uint64_t bytes_moved_threshold; 534 uint64_t bytes_moved_vis_threshold; 535 uint64_t bytes_moved; 536 uint64_t bytes_moved_vis; 537 538 /* user fence */ 539 struct amdgpu_bo_list_entry uf_entry; 540 541 unsigned num_post_deps; 542 struct amdgpu_cs_post_dep *post_deps; 543 }; 544 545 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 546 uint32_t ib_idx, int idx) 547 { 548 return p->job->ibs[ib_idx].ptr[idx]; 549 } 550 551 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 552 uint32_t ib_idx, int idx, 553 uint32_t value) 554 { 555 p->job->ibs[ib_idx].ptr[idx] = value; 556 } 557 558 /* 559 * Writeback 560 */ 561 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 562 563 struct amdgpu_wb { 564 struct amdgpu_bo *wb_obj; 565 volatile uint32_t *wb; 566 uint64_t gpu_addr; 567 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 568 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 569 }; 570 571 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 572 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 573 574 /* 575 * Benchmarking 576 */ 577 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 578 579 580 /* 581 * Testing 582 */ 583 void amdgpu_test_moves(struct amdgpu_device *adev); 584 585 /* 586 * ASIC specific register table accessible by UMD 587 */ 588 struct amdgpu_allowed_register_entry { 589 uint32_t reg_offset; 590 bool grbm_indexed; 591 }; 592 593 enum amd_reset_method { 594 AMD_RESET_METHOD_NONE = -1, 595 AMD_RESET_METHOD_LEGACY = 0, 596 AMD_RESET_METHOD_MODE0, 597 AMD_RESET_METHOD_MODE1, 598 AMD_RESET_METHOD_MODE2, 599 AMD_RESET_METHOD_BACO, 600 AMD_RESET_METHOD_PCI, 601 }; 602 603 struct amdgpu_video_codec_info { 604 u32 codec_type; 605 u32 max_width; 606 u32 max_height; 607 u32 max_pixels_per_frame; 608 u32 max_level; 609 }; 610 611 struct amdgpu_video_codecs { 612 const u32 codec_count; 613 const struct amdgpu_video_codec_info *codec_array; 614 }; 615 616 /* 617 * ASIC specific functions. 618 */ 619 struct amdgpu_asic_funcs { 620 bool (*read_disabled_bios)(struct amdgpu_device *adev); 621 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 622 u8 *bios, u32 length_bytes); 623 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 624 u32 sh_num, u32 reg_offset, u32 *value); 625 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 626 int (*reset)(struct amdgpu_device *adev); 627 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 628 /* get the reference clock */ 629 u32 (*get_xclk)(struct amdgpu_device *adev); 630 /* MM block clocks */ 631 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 632 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 633 /* static power management */ 634 int (*get_pcie_lanes)(struct amdgpu_device *adev); 635 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 636 /* get config memsize register */ 637 u32 (*get_config_memsize)(struct amdgpu_device *adev); 638 /* flush hdp write queue */ 639 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 640 /* invalidate hdp read cache */ 641 void (*invalidate_hdp)(struct amdgpu_device *adev, 642 struct amdgpu_ring *ring); 643 /* check if the asic needs a full reset of if soft reset will work */ 644 bool (*need_full_reset)(struct amdgpu_device *adev); 645 /* initialize doorbell layout for specific asic*/ 646 void (*init_doorbell_index)(struct amdgpu_device *adev); 647 /* PCIe bandwidth usage */ 648 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 649 uint64_t *count1); 650 /* do we need to reset the asic at init time (e.g., kexec) */ 651 bool (*need_reset_on_init)(struct amdgpu_device *adev); 652 /* PCIe replay counter */ 653 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 654 /* device supports BACO */ 655 bool (*supports_baco)(struct amdgpu_device *adev); 656 /* pre asic_init quirks */ 657 void (*pre_asic_init)(struct amdgpu_device *adev); 658 /* enter/exit umd stable pstate */ 659 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 660 /* query video codecs */ 661 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 662 const struct amdgpu_video_codecs **codecs); 663 }; 664 665 /* 666 * IOCTL. 667 */ 668 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 669 struct drm_file *filp); 670 671 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 672 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 673 struct drm_file *filp); 674 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 675 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 676 struct drm_file *filp); 677 678 /* VRAM scratch page for HDP bug, default vram page */ 679 struct amdgpu_vram_scratch { 680 struct amdgpu_bo *robj; 681 volatile uint32_t *ptr; 682 u64 gpu_addr; 683 }; 684 685 /* 686 * ACPI 687 */ 688 struct amdgpu_atcs_functions { 689 bool get_ext_state; 690 bool pcie_perf_req; 691 bool pcie_dev_rdy; 692 bool pcie_bus_width; 693 }; 694 695 struct amdgpu_atcs { 696 struct amdgpu_atcs_functions functions; 697 }; 698 699 /* 700 * CGS 701 */ 702 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 703 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 704 705 /* 706 * Core structure, functions and helpers. 707 */ 708 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 709 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 710 711 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 712 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 713 714 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 715 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 716 717 struct amdgpu_mmio_remap { 718 u32 reg_offset; 719 resource_size_t bus_addr; 720 }; 721 722 /* Define the HW IP blocks will be used in driver , add more if necessary */ 723 enum amd_hw_ip_block_type { 724 GC_HWIP = 1, 725 HDP_HWIP, 726 SDMA0_HWIP, 727 SDMA1_HWIP, 728 SDMA2_HWIP, 729 SDMA3_HWIP, 730 SDMA4_HWIP, 731 SDMA5_HWIP, 732 SDMA6_HWIP, 733 SDMA7_HWIP, 734 MMHUB_HWIP, 735 ATHUB_HWIP, 736 NBIO_HWIP, 737 MP0_HWIP, 738 MP1_HWIP, 739 UVD_HWIP, 740 VCN_HWIP = UVD_HWIP, 741 JPEG_HWIP = VCN_HWIP, 742 VCE_HWIP, 743 DF_HWIP, 744 DCE_HWIP, 745 OSSSYS_HWIP, 746 SMUIO_HWIP, 747 PWR_HWIP, 748 NBIF_HWIP, 749 THM_HWIP, 750 CLK_HWIP, 751 UMC_HWIP, 752 RSMU_HWIP, 753 MAX_HWIP 754 }; 755 756 #define HWIP_MAX_INSTANCE 8 757 758 struct amd_powerplay { 759 void *pp_handle; 760 const struct amd_pm_funcs *pp_funcs; 761 }; 762 763 /* polaris10 kickers */ 764 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 765 ((rid == 0xE3) || \ 766 (rid == 0xE4) || \ 767 (rid == 0xE5) || \ 768 (rid == 0xE7) || \ 769 (rid == 0xEF))) || \ 770 ((did == 0x6FDF) && \ 771 ((rid == 0xE7) || \ 772 (rid == 0xEF) || \ 773 (rid == 0xFF)))) 774 775 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 776 ((rid == 0xE1) || \ 777 (rid == 0xF7))) 778 779 /* polaris11 kickers */ 780 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 781 ((rid == 0xE0) || \ 782 (rid == 0xE5))) || \ 783 ((did == 0x67FF) && \ 784 ((rid == 0xCF) || \ 785 (rid == 0xEF) || \ 786 (rid == 0xFF)))) 787 788 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 789 ((rid == 0xE2))) 790 791 /* polaris12 kickers */ 792 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 793 ((rid == 0xC0) || \ 794 (rid == 0xC1) || \ 795 (rid == 0xC3) || \ 796 (rid == 0xC7))) || \ 797 ((did == 0x6981) && \ 798 ((rid == 0x00) || \ 799 (rid == 0x01) || \ 800 (rid == 0x10)))) 801 802 #define AMDGPU_RESET_MAGIC_NUM 64 803 #define AMDGPU_MAX_DF_PERFMONS 4 804 struct amdgpu_device { 805 struct device *dev; 806 struct pci_dev *pdev; 807 struct drm_device ddev; 808 809 #ifdef CONFIG_DRM_AMD_ACP 810 struct amdgpu_acp acp; 811 #endif 812 struct amdgpu_hive_info *hive; 813 /* ASIC */ 814 enum amd_asic_type asic_type; 815 uint32_t family; 816 uint32_t rev_id; 817 uint32_t external_rev_id; 818 unsigned long flags; 819 unsigned long apu_flags; 820 int usec_timeout; 821 const struct amdgpu_asic_funcs *asic_funcs; 822 bool shutdown; 823 bool need_swiotlb; 824 bool accel_working; 825 struct notifier_block acpi_nb; 826 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 827 struct debugfs_blob_wrapper debugfs_vbios_blob; 828 struct amdgpu_atif *atif; 829 struct amdgpu_atcs atcs; 830 struct mutex srbm_mutex; 831 /* GRBM index mutex. Protects concurrent access to GRBM index */ 832 struct mutex grbm_idx_mutex; 833 struct dev_pm_domain vga_pm_domain; 834 bool have_disp_power_ref; 835 bool have_atomics_support; 836 837 /* BIOS */ 838 bool is_atom_fw; 839 uint8_t *bios; 840 uint32_t bios_size; 841 uint32_t bios_scratch_reg_offset; 842 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 843 844 /* Register/doorbell mmio */ 845 resource_size_t rmmio_base; 846 resource_size_t rmmio_size; 847 void __iomem *rmmio; 848 /* protects concurrent MM_INDEX/DATA based register access */ 849 spinlock_t mmio_idx_lock; 850 struct amdgpu_mmio_remap rmmio_remap; 851 /* protects concurrent SMC based register access */ 852 spinlock_t smc_idx_lock; 853 amdgpu_rreg_t smc_rreg; 854 amdgpu_wreg_t smc_wreg; 855 /* protects concurrent PCIE register access */ 856 spinlock_t pcie_idx_lock; 857 amdgpu_rreg_t pcie_rreg; 858 amdgpu_wreg_t pcie_wreg; 859 amdgpu_rreg_t pciep_rreg; 860 amdgpu_wreg_t pciep_wreg; 861 amdgpu_rreg64_t pcie_rreg64; 862 amdgpu_wreg64_t pcie_wreg64; 863 /* protects concurrent UVD register access */ 864 spinlock_t uvd_ctx_idx_lock; 865 amdgpu_rreg_t uvd_ctx_rreg; 866 amdgpu_wreg_t uvd_ctx_wreg; 867 /* protects concurrent DIDT register access */ 868 spinlock_t didt_idx_lock; 869 amdgpu_rreg_t didt_rreg; 870 amdgpu_wreg_t didt_wreg; 871 /* protects concurrent gc_cac register access */ 872 spinlock_t gc_cac_idx_lock; 873 amdgpu_rreg_t gc_cac_rreg; 874 amdgpu_wreg_t gc_cac_wreg; 875 /* protects concurrent se_cac register access */ 876 spinlock_t se_cac_idx_lock; 877 amdgpu_rreg_t se_cac_rreg; 878 amdgpu_wreg_t se_cac_wreg; 879 /* protects concurrent ENDPOINT (audio) register access */ 880 spinlock_t audio_endpt_idx_lock; 881 amdgpu_block_rreg_t audio_endpt_rreg; 882 amdgpu_block_wreg_t audio_endpt_wreg; 883 struct amdgpu_doorbell doorbell; 884 885 /* clock/pll info */ 886 struct amdgpu_clock clock; 887 888 /* MC */ 889 struct amdgpu_gmc gmc; 890 struct amdgpu_gart gart; 891 dma_addr_t dummy_page_addr; 892 struct amdgpu_vm_manager vm_manager; 893 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 894 unsigned num_vmhubs; 895 896 /* memory management */ 897 struct amdgpu_mman mman; 898 struct amdgpu_vram_scratch vram_scratch; 899 struct amdgpu_wb wb; 900 atomic64_t num_bytes_moved; 901 atomic64_t num_evictions; 902 atomic64_t num_vram_cpu_page_faults; 903 atomic_t gpu_reset_counter; 904 atomic_t vram_lost_counter; 905 906 /* data for buffer migration throttling */ 907 struct { 908 spinlock_t lock; 909 s64 last_update_us; 910 s64 accum_us; /* accumulated microseconds */ 911 s64 accum_us_vis; /* for visible VRAM */ 912 u32 log2_max_MBps; 913 } mm_stats; 914 915 /* display */ 916 bool enable_virtual_display; 917 struct amdgpu_mode_info mode_info; 918 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 919 struct work_struct hotplug_work; 920 struct amdgpu_irq_src crtc_irq; 921 struct amdgpu_irq_src vline0_irq; 922 struct amdgpu_irq_src vupdate_irq; 923 struct amdgpu_irq_src pageflip_irq; 924 struct amdgpu_irq_src hpd_irq; 925 struct amdgpu_irq_src dmub_trace_irq; 926 struct amdgpu_irq_src dmub_outbox_irq; 927 928 /* rings */ 929 u64 fence_context; 930 unsigned num_rings; 931 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 932 bool ib_pool_ready; 933 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 934 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 935 936 /* interrupts */ 937 struct amdgpu_irq irq; 938 939 /* powerplay */ 940 struct amd_powerplay powerplay; 941 bool pp_force_state_enabled; 942 943 /* smu */ 944 struct smu_context smu; 945 946 /* dpm */ 947 struct amdgpu_pm pm; 948 u32 cg_flags; 949 u32 pg_flags; 950 951 /* nbio */ 952 struct amdgpu_nbio nbio; 953 954 /* hdp */ 955 struct amdgpu_hdp hdp; 956 957 /* smuio */ 958 struct amdgpu_smuio smuio; 959 960 /* mmhub */ 961 struct amdgpu_mmhub mmhub; 962 963 /* gfxhub */ 964 struct amdgpu_gfxhub gfxhub; 965 966 /* gfx */ 967 struct amdgpu_gfx gfx; 968 969 /* sdma */ 970 struct amdgpu_sdma sdma; 971 972 /* uvd */ 973 struct amdgpu_uvd uvd; 974 975 /* vce */ 976 struct amdgpu_vce vce; 977 978 /* vcn */ 979 struct amdgpu_vcn vcn; 980 981 /* jpeg */ 982 struct amdgpu_jpeg jpeg; 983 984 /* firmwares */ 985 struct amdgpu_firmware firmware; 986 987 /* PSP */ 988 struct psp_context psp; 989 990 /* GDS */ 991 struct amdgpu_gds gds; 992 993 /* KFD */ 994 struct amdgpu_kfd_dev kfd; 995 996 /* UMC */ 997 struct amdgpu_umc umc; 998 999 /* display related functionality */ 1000 struct amdgpu_display_manager dm; 1001 1002 /* mes */ 1003 bool enable_mes; 1004 struct amdgpu_mes mes; 1005 1006 /* df */ 1007 struct amdgpu_df df; 1008 1009 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1010 uint32_t harvest_ip_mask; 1011 int num_ip_blocks; 1012 struct mutex mn_lock; 1013 DECLARE_HASHTABLE(mn_hash, 7); 1014 1015 /* tracking pinned memory */ 1016 atomic64_t vram_pin_size; 1017 atomic64_t visible_pin_size; 1018 atomic64_t gart_pin_size; 1019 1020 /* soc15 register offset based on ip, instance and segment */ 1021 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1022 1023 /* delayed work_func for deferring clockgating during resume */ 1024 struct delayed_work delayed_init_work; 1025 1026 struct amdgpu_virt virt; 1027 1028 /* link all shadow bo */ 1029 struct list_head shadow_list; 1030 struct mutex shadow_list_lock; 1031 1032 /* record hw reset is performed */ 1033 bool has_hw_reset; 1034 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1035 1036 /* s3/s4 mask */ 1037 bool in_suspend; 1038 bool in_s3; 1039 bool in_s4; 1040 bool in_s0ix; 1041 1042 atomic_t in_gpu_reset; 1043 enum pp_mp1_state mp1_state; 1044 struct rw_semaphore reset_sem; 1045 struct amdgpu_doorbell_index doorbell_index; 1046 1047 struct mutex notifier_lock; 1048 1049 int asic_reset_res; 1050 struct work_struct xgmi_reset_work; 1051 struct list_head reset_list; 1052 1053 long gfx_timeout; 1054 long sdma_timeout; 1055 long video_timeout; 1056 long compute_timeout; 1057 1058 uint64_t unique_id; 1059 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1060 1061 /* enable runtime pm on the device */ 1062 bool runpm; 1063 bool in_runpm; 1064 bool has_pr3; 1065 1066 bool pm_sysfs_en; 1067 bool ucode_sysfs_en; 1068 1069 /* Chip product information */ 1070 char product_number[16]; 1071 char product_name[32]; 1072 char serial[20]; 1073 1074 struct amdgpu_autodump autodump; 1075 1076 atomic_t throttling_logging_enabled; 1077 struct ratelimit_state throttling_logging_rs; 1078 uint32_t ras_hw_enabled; 1079 uint32_t ras_enabled; 1080 1081 bool no_hw_access; 1082 struct pci_saved_state *pci_state; 1083 1084 struct amdgpu_reset_control *reset_cntl; 1085 }; 1086 1087 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1088 { 1089 return container_of(ddev, struct amdgpu_device, ddev); 1090 } 1091 1092 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1093 { 1094 return &adev->ddev; 1095 } 1096 1097 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1098 { 1099 return container_of(bdev, struct amdgpu_device, mman.bdev); 1100 } 1101 1102 int amdgpu_device_init(struct amdgpu_device *adev, 1103 uint32_t flags); 1104 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1105 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1106 1107 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1108 1109 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1110 uint32_t *buf, size_t size, bool write); 1111 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1112 uint32_t reg, uint32_t acc_flags); 1113 void amdgpu_device_wreg(struct amdgpu_device *adev, 1114 uint32_t reg, uint32_t v, 1115 uint32_t acc_flags); 1116 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1117 uint32_t reg, uint32_t v); 1118 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1119 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1120 1121 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1122 u32 pcie_index, u32 pcie_data, 1123 u32 reg_addr); 1124 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1125 u32 pcie_index, u32 pcie_data, 1126 u32 reg_addr); 1127 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1128 u32 pcie_index, u32 pcie_data, 1129 u32 reg_addr, u32 reg_data); 1130 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1131 u32 pcie_index, u32 pcie_data, 1132 u32 reg_addr, u64 reg_data); 1133 1134 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1135 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1136 1137 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1138 struct amdgpu_reset_context *reset_context); 1139 1140 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1141 struct amdgpu_reset_context *reset_context); 1142 1143 int emu_soc_asic_init(struct amdgpu_device *adev); 1144 1145 /* 1146 * Registers read & write functions. 1147 */ 1148 #define AMDGPU_REGS_NO_KIQ (1<<1) 1149 1150 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1151 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1152 1153 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1154 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1155 1156 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1157 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1158 1159 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1160 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1161 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1162 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1163 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1164 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1165 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1166 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1167 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1168 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1169 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1170 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1171 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1172 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1173 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1174 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1175 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1176 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1177 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1178 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1179 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1180 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1181 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1182 #define WREG32_P(reg, val, mask) \ 1183 do { \ 1184 uint32_t tmp_ = RREG32(reg); \ 1185 tmp_ &= (mask); \ 1186 tmp_ |= ((val) & ~(mask)); \ 1187 WREG32(reg, tmp_); \ 1188 } while (0) 1189 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1190 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1191 #define WREG32_PLL_P(reg, val, mask) \ 1192 do { \ 1193 uint32_t tmp_ = RREG32_PLL(reg); \ 1194 tmp_ &= (mask); \ 1195 tmp_ |= ((val) & ~(mask)); \ 1196 WREG32_PLL(reg, tmp_); \ 1197 } while (0) 1198 1199 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1200 do { \ 1201 u32 tmp = RREG32_SMC(_Reg); \ 1202 tmp &= (_Mask); \ 1203 tmp |= ((_Val) & ~(_Mask)); \ 1204 WREG32_SMC(_Reg, tmp); \ 1205 } while (0) 1206 1207 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1208 1209 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1210 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1211 1212 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1213 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1214 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1215 1216 #define REG_GET_FIELD(value, reg, field) \ 1217 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1218 1219 #define WREG32_FIELD(reg, field, val) \ 1220 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1221 1222 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1223 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1224 1225 /* 1226 * BIOS helpers. 1227 */ 1228 #define RBIOS8(i) (adev->bios[i]) 1229 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1230 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1231 1232 /* 1233 * ASICs macro. 1234 */ 1235 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1236 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1237 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1238 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1239 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1240 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1241 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1242 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1243 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1244 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1245 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1246 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1247 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1248 #define amdgpu_asic_flush_hdp(adev, r) \ 1249 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1250 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1251 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1252 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1253 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1254 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1255 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1256 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1257 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1258 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1259 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1260 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1261 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1262 1263 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1264 1265 /* Common functions */ 1266 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1267 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1268 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1269 struct amdgpu_job* job); 1270 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1271 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1272 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1273 1274 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1275 u64 num_vis_bytes); 1276 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1277 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1278 const u32 *registers, 1279 const u32 array_size); 1280 1281 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1282 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1283 bool amdgpu_device_supports_px(struct drm_device *dev); 1284 bool amdgpu_device_supports_boco(struct drm_device *dev); 1285 bool amdgpu_device_supports_baco(struct drm_device *dev); 1286 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1287 struct amdgpu_device *peer_adev); 1288 int amdgpu_device_baco_enter(struct drm_device *dev); 1289 int amdgpu_device_baco_exit(struct drm_device *dev); 1290 1291 /* atpx handler */ 1292 #if defined(CONFIG_VGA_SWITCHEROO) 1293 void amdgpu_register_atpx_handler(void); 1294 void amdgpu_unregister_atpx_handler(void); 1295 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1296 bool amdgpu_is_atpx_hybrid(void); 1297 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1298 bool amdgpu_has_atpx(void); 1299 #else 1300 static inline void amdgpu_register_atpx_handler(void) {} 1301 static inline void amdgpu_unregister_atpx_handler(void) {} 1302 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1303 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1304 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1305 static inline bool amdgpu_has_atpx(void) { return false; } 1306 #endif 1307 1308 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1309 void *amdgpu_atpx_get_dhandle(void); 1310 #else 1311 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1312 #endif 1313 1314 /* 1315 * KMS 1316 */ 1317 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1318 extern const int amdgpu_max_kms_ioctl; 1319 1320 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1321 void amdgpu_driver_unload_kms(struct drm_device *dev); 1322 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1323 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1324 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1325 struct drm_file *file_priv); 1326 void amdgpu_driver_release_kms(struct drm_device *dev); 1327 1328 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1329 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1330 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1331 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1332 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1333 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1334 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1335 unsigned long arg); 1336 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1337 struct drm_file *filp); 1338 1339 /* 1340 * functions used by amdgpu_encoder.c 1341 */ 1342 struct amdgpu_afmt_acr { 1343 u32 clock; 1344 1345 int n_32khz; 1346 int cts_32khz; 1347 1348 int n_44_1khz; 1349 int cts_44_1khz; 1350 1351 int n_48khz; 1352 int cts_48khz; 1353 1354 }; 1355 1356 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1357 1358 /* amdgpu_acpi.c */ 1359 #if defined(CONFIG_ACPI) 1360 int amdgpu_acpi_init(struct amdgpu_device *adev); 1361 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1362 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1363 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1364 u8 perf_req, bool advertise); 1365 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1366 1367 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1368 struct amdgpu_dm_backlight_caps *caps); 1369 bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); 1370 #else 1371 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1372 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1373 static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } 1374 #endif 1375 1376 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1377 uint64_t addr, struct amdgpu_bo **bo, 1378 struct amdgpu_bo_va_mapping **mapping); 1379 1380 #if defined(CONFIG_DRM_AMD_DC) 1381 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1382 #else 1383 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1384 #endif 1385 1386 1387 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1388 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1389 1390 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1391 pci_channel_state_t state); 1392 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1393 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1394 void amdgpu_pci_resume(struct pci_dev *pdev); 1395 1396 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1397 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1398 1399 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1400 1401 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1402 enum amd_clockgating_state state); 1403 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1404 enum amd_powergating_state state); 1405 1406 #include "amdgpu_object.h" 1407 1408 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1409 { 1410 return adev->gmc.tmz_enabled; 1411 } 1412 1413 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1414 { 1415 return atomic_read(&adev->in_gpu_reset); 1416 } 1417 #endif 1418