1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_cper.h" 113 #include "amdgpu_xcp.h" 114 #include "amdgpu_seq64.h" 115 #include "amdgpu_reg_state.h" 116 #include "amdgpu_userq.h" 117 #include "amdgpu_eviction_fence.h" 118 #if defined(CONFIG_DRM_AMD_ISP) 119 #include "amdgpu_isp.h" 120 #endif 121 122 #define MAX_GPU_INSTANCE 64 123 124 #define GFX_SLICE_PERIOD_MS 250 125 126 struct amdgpu_gpu_instance { 127 struct amdgpu_device *adev; 128 int mgpu_fan_enabled; 129 }; 130 131 struct amdgpu_mgpu_info { 132 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 133 struct mutex mutex; 134 uint32_t num_gpu; 135 uint32_t num_dgpu; 136 uint32_t num_apu; 137 }; 138 139 enum amdgpu_ss { 140 AMDGPU_SS_DRV_LOAD, 141 AMDGPU_SS_DEV_D0, 142 AMDGPU_SS_DEV_D3, 143 AMDGPU_SS_DRV_UNLOAD 144 }; 145 146 struct amdgpu_hwip_reg_entry { 147 u32 hwip; 148 u32 inst; 149 u32 seg; 150 u32 reg_offset; 151 const char *reg_name; 152 }; 153 154 struct amdgpu_watchdog_timer { 155 bool timeout_fatal_disable; 156 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 157 }; 158 159 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 160 161 /* 162 * Modules parameters. 163 */ 164 extern int amdgpu_modeset; 165 extern unsigned int amdgpu_vram_limit; 166 extern int amdgpu_vis_vram_limit; 167 extern int amdgpu_gart_size; 168 extern int amdgpu_gtt_size; 169 extern int amdgpu_moverate; 170 extern int amdgpu_audio; 171 extern int amdgpu_disp_priority; 172 extern int amdgpu_hw_i2c; 173 extern int amdgpu_pcie_gen2; 174 extern int amdgpu_msi; 175 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 176 extern int amdgpu_dpm; 177 extern int amdgpu_fw_load_type; 178 extern int amdgpu_aspm; 179 extern int amdgpu_runtime_pm; 180 extern uint amdgpu_ip_block_mask; 181 extern int amdgpu_bapm; 182 extern int amdgpu_deep_color; 183 extern int amdgpu_vm_size; 184 extern int amdgpu_vm_block_size; 185 extern int amdgpu_vm_fragment_size; 186 extern int amdgpu_vm_fault_stop; 187 extern int amdgpu_vm_debug; 188 extern int amdgpu_vm_update_mode; 189 extern int amdgpu_exp_hw_support; 190 extern int amdgpu_dc; 191 extern int amdgpu_sched_jobs; 192 extern int amdgpu_sched_hw_submission; 193 extern uint amdgpu_pcie_gen_cap; 194 extern uint amdgpu_pcie_lane_cap; 195 extern u64 amdgpu_cg_mask; 196 extern uint amdgpu_pg_mask; 197 extern uint amdgpu_sdma_phase_quantum; 198 extern char *amdgpu_disable_cu; 199 extern char *amdgpu_virtual_display; 200 extern uint amdgpu_pp_feature_mask; 201 extern uint amdgpu_force_long_training; 202 extern int amdgpu_lbpw; 203 extern int amdgpu_compute_multipipe; 204 extern int amdgpu_gpu_recovery; 205 extern int amdgpu_emu_mode; 206 extern uint amdgpu_smu_memory_pool_size; 207 extern int amdgpu_smu_pptable_id; 208 extern uint amdgpu_dc_feature_mask; 209 extern uint amdgpu_freesync_vid_mode; 210 extern uint amdgpu_dc_debug_mask; 211 extern uint amdgpu_dc_visual_confirm; 212 extern int amdgpu_dm_abm_level; 213 extern int amdgpu_backlight; 214 extern int amdgpu_damage_clips; 215 extern struct amdgpu_mgpu_info mgpu_info; 216 extern int amdgpu_ras_enable; 217 extern uint amdgpu_ras_mask; 218 extern int amdgpu_bad_page_threshold; 219 extern bool amdgpu_ignore_bad_page_threshold; 220 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 221 extern int amdgpu_async_gfx_ring; 222 extern int amdgpu_mcbp; 223 extern int amdgpu_discovery; 224 extern int amdgpu_mes; 225 extern int amdgpu_mes_log_enable; 226 extern int amdgpu_mes_kiq; 227 extern int amdgpu_uni_mes; 228 extern int amdgpu_noretry; 229 extern int amdgpu_force_asic_type; 230 extern int amdgpu_smartshift_bias; 231 extern int amdgpu_use_xgmi_p2p; 232 extern int amdgpu_mtype_local; 233 extern int amdgpu_enforce_isolation; 234 #ifdef CONFIG_HSA_AMD 235 extern int sched_policy; 236 extern bool debug_evictions; 237 extern bool no_system_mem_limit; 238 extern int halt_if_hws_hang; 239 extern uint amdgpu_svm_default_granularity; 240 #else 241 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 242 static const bool __maybe_unused debug_evictions; /* = false */ 243 static const bool __maybe_unused no_system_mem_limit; 244 static const int __maybe_unused halt_if_hws_hang; 245 #endif 246 #ifdef CONFIG_HSA_AMD_P2P 247 extern bool pcie_p2p; 248 #endif 249 250 extern int amdgpu_tmz; 251 extern int amdgpu_reset_method; 252 253 #ifdef CONFIG_DRM_AMDGPU_SI 254 extern int amdgpu_si_support; 255 #endif 256 #ifdef CONFIG_DRM_AMDGPU_CIK 257 extern int amdgpu_cik_support; 258 #endif 259 extern int amdgpu_num_kcq; 260 261 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 262 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 263 extern int amdgpu_vcnfw_log; 264 extern int amdgpu_sg_display; 265 extern int amdgpu_umsch_mm; 266 extern int amdgpu_seamless; 267 extern int amdgpu_umsch_mm_fwlog; 268 269 extern int amdgpu_user_partt_mode; 270 extern int amdgpu_agp; 271 extern int amdgpu_rebar; 272 273 extern int amdgpu_wbrf; 274 extern int amdgpu_user_queue; 275 276 #define AMDGPU_VM_MAX_NUM_CTX 4096 277 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 278 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 279 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 280 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 281 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 282 #define AMDGPUFB_CONN_LIMIT 4 283 #define AMDGPU_BIOS_NUM_SCRATCH 16 284 285 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 286 287 /* hard reset data */ 288 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 289 290 /* reset flags */ 291 #define AMDGPU_RESET_GFX (1 << 0) 292 #define AMDGPU_RESET_COMPUTE (1 << 1) 293 #define AMDGPU_RESET_DMA (1 << 2) 294 #define AMDGPU_RESET_CP (1 << 3) 295 #define AMDGPU_RESET_GRBM (1 << 4) 296 #define AMDGPU_RESET_DMA1 (1 << 5) 297 #define AMDGPU_RESET_RLC (1 << 6) 298 #define AMDGPU_RESET_SEM (1 << 7) 299 #define AMDGPU_RESET_IH (1 << 8) 300 #define AMDGPU_RESET_VMC (1 << 9) 301 #define AMDGPU_RESET_MC (1 << 10) 302 #define AMDGPU_RESET_DISPLAY (1 << 11) 303 #define AMDGPU_RESET_UVD (1 << 12) 304 #define AMDGPU_RESET_VCE (1 << 13) 305 #define AMDGPU_RESET_VCE1 (1 << 14) 306 307 /* reset mask */ 308 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 309 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 310 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 311 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 312 313 /* max cursor sizes (in pixels) */ 314 #define CIK_CURSOR_WIDTH 128 315 #define CIK_CURSOR_HEIGHT 128 316 317 /* smart shift bias level limits */ 318 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 319 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 320 321 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 322 #define AMDGPU_SWCTF_EXTRA_DELAY 50 323 324 struct amdgpu_xcp_mgr; 325 struct amdgpu_device; 326 struct amdgpu_irq_src; 327 struct amdgpu_fpriv; 328 struct amdgpu_bo_va_mapping; 329 struct kfd_vm_fault_info; 330 struct amdgpu_hive_info; 331 struct amdgpu_reset_context; 332 struct amdgpu_reset_control; 333 334 enum amdgpu_cp_irq { 335 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 336 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 337 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 345 346 AMDGPU_CP_IRQ_LAST 347 }; 348 349 enum amdgpu_thermal_irq { 350 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 351 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 352 353 AMDGPU_THERMAL_IRQ_LAST 354 }; 355 356 enum amdgpu_kiq_irq { 357 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 358 AMDGPU_CP_KIQ_IRQ_LAST 359 }; 360 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 361 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 362 #define MAX_KIQ_REG_TRY 1000 363 364 int amdgpu_device_ip_set_clockgating_state(void *dev, 365 enum amd_ip_block_type block_type, 366 enum amd_clockgating_state state); 367 int amdgpu_device_ip_set_powergating_state(void *dev, 368 enum amd_ip_block_type block_type, 369 enum amd_powergating_state state); 370 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 371 u64 *flags); 372 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 373 enum amd_ip_block_type block_type); 374 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 375 enum amd_ip_block_type block_type); 376 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 377 378 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 379 380 #define AMDGPU_MAX_IP_NUM 16 381 382 struct amdgpu_ip_block_status { 383 bool valid; 384 bool sw; 385 bool hw; 386 bool late_initialized; 387 bool hang; 388 }; 389 390 struct amdgpu_ip_block_version { 391 const enum amd_ip_block_type type; 392 const u32 major; 393 const u32 minor; 394 const u32 rev; 395 const struct amd_ip_funcs *funcs; 396 }; 397 398 struct amdgpu_ip_block { 399 struct amdgpu_ip_block_status status; 400 const struct amdgpu_ip_block_version *version; 401 struct amdgpu_device *adev; 402 }; 403 404 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 405 enum amd_ip_block_type type, 406 u32 major, u32 minor); 407 408 struct amdgpu_ip_block * 409 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 410 enum amd_ip_block_type type); 411 412 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 413 const struct amdgpu_ip_block_version *ip_block_version); 414 415 /* 416 * BIOS. 417 */ 418 bool amdgpu_get_bios(struct amdgpu_device *adev); 419 bool amdgpu_read_bios(struct amdgpu_device *adev); 420 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 421 u8 *bios, u32 length_bytes); 422 void amdgpu_bios_release(struct amdgpu_device *adev); 423 /* 424 * Clocks 425 */ 426 427 #define AMDGPU_MAX_PPLL 3 428 429 struct amdgpu_clock { 430 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 431 struct amdgpu_pll spll; 432 struct amdgpu_pll mpll; 433 /* 10 Khz units */ 434 uint32_t default_mclk; 435 uint32_t default_sclk; 436 uint32_t default_dispclk; 437 uint32_t current_dispclk; 438 uint32_t dp_extclk; 439 uint32_t max_pixel_clock; 440 }; 441 442 /* sub-allocation manager, it has to be protected by another lock. 443 * By conception this is an helper for other part of the driver 444 * like the indirect buffer or semaphore, which both have their 445 * locking. 446 * 447 * Principe is simple, we keep a list of sub allocation in offset 448 * order (first entry has offset == 0, last entry has the highest 449 * offset). 450 * 451 * When allocating new object we first check if there is room at 452 * the end total_size - (last_object_offset + last_object_size) >= 453 * alloc_size. If so we allocate new object there. 454 * 455 * When there is not enough room at the end, we start waiting for 456 * each sub object until we reach object_offset+object_size >= 457 * alloc_size, this object then become the sub object we return. 458 * 459 * Alignment can't be bigger than page size. 460 * 461 * Hole are not considered for allocation to keep things simple. 462 * Assumption is that there won't be hole (all object on same 463 * alignment). 464 */ 465 466 struct amdgpu_sa_manager { 467 struct drm_suballoc_manager base; 468 struct amdgpu_bo *bo; 469 uint64_t gpu_addr; 470 void *cpu_ptr; 471 }; 472 473 /* 474 * IRQS. 475 */ 476 477 struct amdgpu_flip_work { 478 struct delayed_work flip_work; 479 struct work_struct unpin_work; 480 struct amdgpu_device *adev; 481 int crtc_id; 482 u32 target_vblank; 483 uint64_t base; 484 struct drm_pending_vblank_event *event; 485 struct amdgpu_bo *old_abo; 486 unsigned shared_count; 487 struct dma_fence **shared; 488 struct dma_fence_cb cb; 489 bool async; 490 }; 491 492 /* 493 * file private structure 494 */ 495 496 struct amdgpu_fpriv { 497 struct amdgpu_vm vm; 498 struct amdgpu_bo_va *prt_va; 499 struct amdgpu_bo_va *csa_va; 500 struct amdgpu_bo_va *seq64_va; 501 struct mutex bo_list_lock; 502 struct idr bo_list_handles; 503 struct amdgpu_ctx_mgr ctx_mgr; 504 struct amdgpu_userq_mgr userq_mgr; 505 506 /* Eviction fence infra */ 507 struct amdgpu_eviction_fence_mgr evf_mgr; 508 509 /** GPU partition selection */ 510 uint32_t xcp_id; 511 }; 512 513 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 514 515 /* 516 * Writeback 517 */ 518 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 519 520 /** 521 * amdgpu_wb - This struct is used for small GPU memory allocation. 522 * 523 * This struct is used to allocate a small amount of GPU memory that can be 524 * used to shadow certain states into the memory. This is especially useful for 525 * providing easy CPU access to some states without requiring register access 526 * (e.g., if some block is power gated, reading register may be problematic). 527 * 528 * Note: the term writeback was initially used because many of the amdgpu 529 * components had some level of writeback memory, and this struct initially 530 * described those components. 531 */ 532 struct amdgpu_wb { 533 534 /** 535 * @wb_obj: 536 * 537 * Buffer Object used for the writeback memory. 538 */ 539 struct amdgpu_bo *wb_obj; 540 541 /** 542 * @wb: 543 * 544 * Pointer to the first writeback slot. In terms of CPU address 545 * this value can be accessed directly by using the offset as an index. 546 * For the GPU address, it is necessary to use gpu_addr and the offset. 547 */ 548 volatile uint32_t *wb; 549 550 /** 551 * @gpu_addr: 552 * 553 * Writeback base address in the GPU. 554 */ 555 uint64_t gpu_addr; 556 557 /** 558 * @num_wb: 559 * 560 * Number of writeback slots reserved for amdgpu. 561 */ 562 u32 num_wb; 563 564 /** 565 * @used: 566 * 567 * Track the writeback slot already used. 568 */ 569 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 570 571 /** 572 * @lock: 573 * 574 * Protects read and write of the used field array. 575 */ 576 spinlock_t lock; 577 }; 578 579 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 580 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 581 582 /* 583 * Benchmarking 584 */ 585 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 586 587 /* 588 * ASIC specific register table accessible by UMD 589 */ 590 struct amdgpu_allowed_register_entry { 591 uint32_t reg_offset; 592 bool grbm_indexed; 593 }; 594 595 /** 596 * enum amd_reset_method - Methods for resetting AMD GPU devices 597 * 598 * @AMD_RESET_METHOD_NONE: The device will not be reset. 599 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 600 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 601 * any device. 602 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 603 * individually. Suitable only for some discrete GPU, not 604 * available for all ASICs. 605 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 606 * are reset depends on the ASIC. Notably doesn't reset IPs 607 * shared with the CPU on APUs or the memory controllers (so 608 * VRAM is not lost). Not available on all ASICs. 609 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 610 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 611 * but without powering off the PCI bus. Suitable only for 612 * discrete GPUs. 613 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 614 * and does a secondary bus reset or FLR, depending on what the 615 * underlying hardware supports. 616 * 617 * Methods available for AMD GPU driver for resetting the device. Not all 618 * methods are suitable for every device. User can override the method using 619 * module parameter `reset_method`. 620 */ 621 enum amd_reset_method { 622 AMD_RESET_METHOD_NONE = -1, 623 AMD_RESET_METHOD_LEGACY = 0, 624 AMD_RESET_METHOD_MODE0, 625 AMD_RESET_METHOD_MODE1, 626 AMD_RESET_METHOD_MODE2, 627 AMD_RESET_METHOD_LINK, 628 AMD_RESET_METHOD_BACO, 629 AMD_RESET_METHOD_PCI, 630 AMD_RESET_METHOD_ON_INIT, 631 }; 632 633 struct amdgpu_video_codec_info { 634 u32 codec_type; 635 u32 max_width; 636 u32 max_height; 637 u32 max_pixels_per_frame; 638 u32 max_level; 639 }; 640 641 #define codec_info_build(type, width, height, level) \ 642 .codec_type = type,\ 643 .max_width = width,\ 644 .max_height = height,\ 645 .max_pixels_per_frame = height * width,\ 646 .max_level = level, 647 648 struct amdgpu_video_codecs { 649 const u32 codec_count; 650 const struct amdgpu_video_codec_info *codec_array; 651 }; 652 653 /* 654 * ASIC specific functions. 655 */ 656 struct amdgpu_asic_funcs { 657 bool (*read_disabled_bios)(struct amdgpu_device *adev); 658 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 659 u8 *bios, u32 length_bytes); 660 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 661 u32 sh_num, u32 reg_offset, u32 *value); 662 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 663 int (*reset)(struct amdgpu_device *adev); 664 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 665 /* get the reference clock */ 666 u32 (*get_xclk)(struct amdgpu_device *adev); 667 /* MM block clocks */ 668 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 669 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 670 /* static power management */ 671 int (*get_pcie_lanes)(struct amdgpu_device *adev); 672 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 673 /* get config memsize register */ 674 u32 (*get_config_memsize)(struct amdgpu_device *adev); 675 /* flush hdp write queue */ 676 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 677 /* invalidate hdp read cache */ 678 void (*invalidate_hdp)(struct amdgpu_device *adev, 679 struct amdgpu_ring *ring); 680 /* check if the asic needs a full reset of if soft reset will work */ 681 bool (*need_full_reset)(struct amdgpu_device *adev); 682 /* initialize doorbell layout for specific asic*/ 683 void (*init_doorbell_index)(struct amdgpu_device *adev); 684 /* PCIe bandwidth usage */ 685 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 686 uint64_t *count1); 687 /* do we need to reset the asic at init time (e.g., kexec) */ 688 bool (*need_reset_on_init)(struct amdgpu_device *adev); 689 /* PCIe replay counter */ 690 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 691 /* device supports BACO */ 692 int (*supports_baco)(struct amdgpu_device *adev); 693 /* pre asic_init quirks */ 694 void (*pre_asic_init)(struct amdgpu_device *adev); 695 /* enter/exit umd stable pstate */ 696 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 697 /* query video codecs */ 698 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 699 const struct amdgpu_video_codecs **codecs); 700 /* encode "> 32bits" smn addressing */ 701 u64 (*encode_ext_smn_addressing)(int ext_id); 702 703 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 704 enum amdgpu_reg_state reg_state, void *buf, 705 size_t max_size); 706 }; 707 708 /* 709 * IOCTL. 710 */ 711 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 712 struct drm_file *filp); 713 714 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 715 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 716 struct drm_file *filp); 717 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 718 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 719 struct drm_file *filp); 720 721 /* VRAM scratch page for HDP bug, default vram page */ 722 struct amdgpu_mem_scratch { 723 struct amdgpu_bo *robj; 724 volatile uint32_t *ptr; 725 u64 gpu_addr; 726 }; 727 728 /* 729 * CGS 730 */ 731 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 732 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 733 734 /* 735 * Core structure, functions and helpers. 736 */ 737 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 738 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 739 740 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 741 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 742 743 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 744 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 745 746 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 747 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 748 749 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 750 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 751 752 struct amdgpu_mmio_remap { 753 u32 reg_offset; 754 resource_size_t bus_addr; 755 }; 756 757 /* Define the HW IP blocks will be used in driver , add more if necessary */ 758 enum amd_hw_ip_block_type { 759 GC_HWIP = 1, 760 HDP_HWIP, 761 SDMA0_HWIP, 762 SDMA1_HWIP, 763 SDMA2_HWIP, 764 SDMA3_HWIP, 765 SDMA4_HWIP, 766 SDMA5_HWIP, 767 SDMA6_HWIP, 768 SDMA7_HWIP, 769 LSDMA_HWIP, 770 MMHUB_HWIP, 771 ATHUB_HWIP, 772 NBIO_HWIP, 773 MP0_HWIP, 774 MP1_HWIP, 775 UVD_HWIP, 776 VCN_HWIP = UVD_HWIP, 777 JPEG_HWIP = VCN_HWIP, 778 VCN1_HWIP, 779 VCE_HWIP, 780 VPE_HWIP, 781 DF_HWIP, 782 DCE_HWIP, 783 OSSSYS_HWIP, 784 SMUIO_HWIP, 785 PWR_HWIP, 786 NBIF_HWIP, 787 THM_HWIP, 788 CLK_HWIP, 789 UMC_HWIP, 790 RSMU_HWIP, 791 XGMI_HWIP, 792 DCI_HWIP, 793 PCIE_HWIP, 794 ISP_HWIP, 795 MAX_HWIP 796 }; 797 798 #define HWIP_MAX_INSTANCE 44 799 800 #define HW_ID_MAX 300 801 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 802 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 803 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 804 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 805 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 806 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 807 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 808 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 809 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 810 811 struct amdgpu_ip_map_info { 812 /* Map of logical to actual dev instances/mask */ 813 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 814 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 815 enum amd_hw_ip_block_type block, 816 int8_t inst); 817 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 818 enum amd_hw_ip_block_type block, 819 uint32_t mask); 820 }; 821 822 enum amdgpu_uid_type { 823 AMDGPU_UID_TYPE_XCD, 824 AMDGPU_UID_TYPE_AID, 825 AMDGPU_UID_TYPE_SOC, 826 AMDGPU_UID_TYPE_MAX 827 }; 828 829 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 830 831 struct amdgpu_uid { 832 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 833 struct amdgpu_device *adev; 834 }; 835 836 struct amd_powerplay { 837 void *pp_handle; 838 const struct amd_pm_funcs *pp_funcs; 839 }; 840 841 struct ip_discovery_top; 842 843 /* polaris10 kickers */ 844 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 845 ((rid == 0xE3) || \ 846 (rid == 0xE4) || \ 847 (rid == 0xE5) || \ 848 (rid == 0xE7) || \ 849 (rid == 0xEF))) || \ 850 ((did == 0x6FDF) && \ 851 ((rid == 0xE7) || \ 852 (rid == 0xEF) || \ 853 (rid == 0xFF)))) 854 855 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 856 ((rid == 0xE1) || \ 857 (rid == 0xF7))) 858 859 /* polaris11 kickers */ 860 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 861 ((rid == 0xE0) || \ 862 (rid == 0xE5))) || \ 863 ((did == 0x67FF) && \ 864 ((rid == 0xCF) || \ 865 (rid == 0xEF) || \ 866 (rid == 0xFF)))) 867 868 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 869 ((rid == 0xE2))) 870 871 /* polaris12 kickers */ 872 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 873 ((rid == 0xC0) || \ 874 (rid == 0xC1) || \ 875 (rid == 0xC3) || \ 876 (rid == 0xC7))) || \ 877 ((did == 0x6981) && \ 878 ((rid == 0x00) || \ 879 (rid == 0x01) || \ 880 (rid == 0x10)))) 881 882 struct amdgpu_mqd_prop { 883 uint64_t mqd_gpu_addr; 884 uint64_t hqd_base_gpu_addr; 885 uint64_t rptr_gpu_addr; 886 uint64_t wptr_gpu_addr; 887 uint32_t queue_size; 888 bool use_doorbell; 889 uint32_t doorbell_index; 890 uint64_t eop_gpu_addr; 891 uint32_t hqd_pipe_priority; 892 uint32_t hqd_queue_priority; 893 bool allow_tunneling; 894 bool hqd_active; 895 uint64_t shadow_addr; 896 uint64_t gds_bkup_addr; 897 uint64_t csa_addr; 898 uint64_t fence_address; 899 bool tmz_queue; 900 bool kernel_queue; 901 }; 902 903 struct amdgpu_mqd { 904 unsigned mqd_size; 905 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 906 struct amdgpu_mqd_prop *p); 907 }; 908 909 struct amdgpu_pcie_reset_ctx { 910 bool in_link_reset; 911 bool occurs_dpc; 912 bool audio_suspended; 913 struct pci_dev *swus; 914 struct pci_saved_state *swus_pcistate; 915 struct pci_saved_state *swds_pcistate; 916 }; 917 918 /* 919 * Custom Init levels could be defined for different situations where a full 920 * initialization of all hardware blocks are not expected. Sample cases are 921 * custom init sequences after resume after S0i3/S3, reset on initialization, 922 * partial reset of blocks etc. Presently, this defines only two levels. Levels 923 * are described in corresponding struct definitions - amdgpu_init_default, 924 * amdgpu_init_minimal_xgmi. 925 */ 926 enum amdgpu_init_lvl_id { 927 AMDGPU_INIT_LEVEL_DEFAULT, 928 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 929 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 930 }; 931 932 struct amdgpu_init_level { 933 enum amdgpu_init_lvl_id level; 934 uint32_t hwini_ip_block_mask; 935 }; 936 937 #define AMDGPU_RESET_MAGIC_NUM 64 938 #define AMDGPU_MAX_DF_PERFMONS 4 939 struct amdgpu_reset_domain; 940 struct amdgpu_fru_info; 941 942 enum amdgpu_enforce_isolation_mode { 943 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 944 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 945 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 946 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 947 }; 948 949 950 /* 951 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 952 */ 953 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 954 955 struct amdgpu_device { 956 struct device *dev; 957 struct pci_dev *pdev; 958 struct drm_device ddev; 959 960 #ifdef CONFIG_DRM_AMD_ACP 961 struct amdgpu_acp acp; 962 #endif 963 struct amdgpu_hive_info *hive; 964 struct amdgpu_xcp_mgr *xcp_mgr; 965 /* ASIC */ 966 enum amd_asic_type asic_type; 967 uint32_t family; 968 uint32_t rev_id; 969 uint32_t external_rev_id; 970 unsigned long flags; 971 unsigned long apu_flags; 972 int usec_timeout; 973 const struct amdgpu_asic_funcs *asic_funcs; 974 bool shutdown; 975 bool need_swiotlb; 976 bool accel_working; 977 struct notifier_block acpi_nb; 978 struct notifier_block pm_nb; 979 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 980 struct debugfs_blob_wrapper debugfs_vbios_blob; 981 struct debugfs_blob_wrapper debugfs_discovery_blob; 982 struct mutex srbm_mutex; 983 /* GRBM index mutex. Protects concurrent access to GRBM index */ 984 struct mutex grbm_idx_mutex; 985 struct dev_pm_domain vga_pm_domain; 986 bool have_disp_power_ref; 987 bool have_atomics_support; 988 989 /* BIOS */ 990 bool is_atom_fw; 991 uint8_t *bios; 992 uint32_t bios_size; 993 uint32_t bios_scratch_reg_offset; 994 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 995 996 /* Register/doorbell mmio */ 997 resource_size_t rmmio_base; 998 resource_size_t rmmio_size; 999 void __iomem *rmmio; 1000 /* protects concurrent MM_INDEX/DATA based register access */ 1001 spinlock_t mmio_idx_lock; 1002 struct amdgpu_mmio_remap rmmio_remap; 1003 /* protects concurrent SMC based register access */ 1004 spinlock_t smc_idx_lock; 1005 amdgpu_rreg_t smc_rreg; 1006 amdgpu_wreg_t smc_wreg; 1007 /* protects concurrent PCIE register access */ 1008 spinlock_t pcie_idx_lock; 1009 amdgpu_rreg_t pcie_rreg; 1010 amdgpu_wreg_t pcie_wreg; 1011 amdgpu_rreg_t pciep_rreg; 1012 amdgpu_wreg_t pciep_wreg; 1013 amdgpu_rreg_ext_t pcie_rreg_ext; 1014 amdgpu_wreg_ext_t pcie_wreg_ext; 1015 amdgpu_rreg64_t pcie_rreg64; 1016 amdgpu_wreg64_t pcie_wreg64; 1017 amdgpu_rreg64_ext_t pcie_rreg64_ext; 1018 amdgpu_wreg64_ext_t pcie_wreg64_ext; 1019 /* protects concurrent UVD register access */ 1020 spinlock_t uvd_ctx_idx_lock; 1021 amdgpu_rreg_t uvd_ctx_rreg; 1022 amdgpu_wreg_t uvd_ctx_wreg; 1023 /* protects concurrent DIDT register access */ 1024 spinlock_t didt_idx_lock; 1025 amdgpu_rreg_t didt_rreg; 1026 amdgpu_wreg_t didt_wreg; 1027 /* protects concurrent gc_cac register access */ 1028 spinlock_t gc_cac_idx_lock; 1029 amdgpu_rreg_t gc_cac_rreg; 1030 amdgpu_wreg_t gc_cac_wreg; 1031 /* protects concurrent se_cac register access */ 1032 spinlock_t se_cac_idx_lock; 1033 amdgpu_rreg_t se_cac_rreg; 1034 amdgpu_wreg_t se_cac_wreg; 1035 /* protects concurrent ENDPOINT (audio) register access */ 1036 spinlock_t audio_endpt_idx_lock; 1037 amdgpu_block_rreg_t audio_endpt_rreg; 1038 amdgpu_block_wreg_t audio_endpt_wreg; 1039 struct amdgpu_doorbell doorbell; 1040 1041 /* clock/pll info */ 1042 struct amdgpu_clock clock; 1043 1044 /* MC */ 1045 struct amdgpu_gmc gmc; 1046 struct amdgpu_gart gart; 1047 dma_addr_t dummy_page_addr; 1048 struct amdgpu_vm_manager vm_manager; 1049 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1050 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 1051 1052 /* memory management */ 1053 struct amdgpu_mman mman; 1054 struct amdgpu_mem_scratch mem_scratch; 1055 struct amdgpu_wb wb; 1056 atomic64_t num_bytes_moved; 1057 atomic64_t num_evictions; 1058 atomic64_t num_vram_cpu_page_faults; 1059 atomic_t gpu_reset_counter; 1060 atomic_t vram_lost_counter; 1061 1062 /* data for buffer migration throttling */ 1063 struct { 1064 spinlock_t lock; 1065 s64 last_update_us; 1066 s64 accum_us; /* accumulated microseconds */ 1067 s64 accum_us_vis; /* for visible VRAM */ 1068 u32 log2_max_MBps; 1069 } mm_stats; 1070 1071 /* display */ 1072 bool enable_virtual_display; 1073 struct amdgpu_vkms_output *amdgpu_vkms_output; 1074 struct amdgpu_mode_info mode_info; 1075 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1076 struct delayed_work hotplug_work; 1077 struct amdgpu_irq_src crtc_irq; 1078 struct amdgpu_irq_src vline0_irq; 1079 struct amdgpu_irq_src vupdate_irq; 1080 struct amdgpu_irq_src pageflip_irq; 1081 struct amdgpu_irq_src hpd_irq; 1082 struct amdgpu_irq_src dmub_trace_irq; 1083 struct amdgpu_irq_src dmub_outbox_irq; 1084 1085 /* rings */ 1086 u64 fence_context; 1087 unsigned num_rings; 1088 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1089 struct dma_fence __rcu *gang_submit; 1090 bool ib_pool_ready; 1091 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1092 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1093 1094 /* interrupts */ 1095 struct amdgpu_irq irq; 1096 1097 /* powerplay */ 1098 struct amd_powerplay powerplay; 1099 struct amdgpu_pm pm; 1100 u64 cg_flags; 1101 u32 pg_flags; 1102 1103 /* nbio */ 1104 struct amdgpu_nbio nbio; 1105 1106 /* hdp */ 1107 struct amdgpu_hdp hdp; 1108 1109 /* smuio */ 1110 struct amdgpu_smuio smuio; 1111 1112 /* mmhub */ 1113 struct amdgpu_mmhub mmhub; 1114 1115 /* gfxhub */ 1116 struct amdgpu_gfxhub gfxhub; 1117 1118 /* gfx */ 1119 struct amdgpu_gfx gfx; 1120 1121 /* sdma */ 1122 struct amdgpu_sdma sdma; 1123 1124 /* lsdma */ 1125 struct amdgpu_lsdma lsdma; 1126 1127 /* uvd */ 1128 struct amdgpu_uvd uvd; 1129 1130 /* vce */ 1131 struct amdgpu_vce vce; 1132 1133 /* vcn */ 1134 struct amdgpu_vcn vcn; 1135 1136 /* jpeg */ 1137 struct amdgpu_jpeg jpeg; 1138 1139 /* vpe */ 1140 struct amdgpu_vpe vpe; 1141 1142 /* umsch */ 1143 struct amdgpu_umsch_mm umsch_mm; 1144 bool enable_umsch_mm; 1145 1146 /* firmwares */ 1147 struct amdgpu_firmware firmware; 1148 1149 /* PSP */ 1150 struct psp_context psp; 1151 1152 /* GDS */ 1153 struct amdgpu_gds gds; 1154 1155 /* for userq and VM fences */ 1156 struct amdgpu_seq64 seq64; 1157 1158 /* KFD */ 1159 struct amdgpu_kfd_dev kfd; 1160 1161 /* UMC */ 1162 struct amdgpu_umc umc; 1163 1164 /* display related functionality */ 1165 struct amdgpu_display_manager dm; 1166 1167 #if defined(CONFIG_DRM_AMD_ISP) 1168 /* isp */ 1169 struct amdgpu_isp isp; 1170 #endif 1171 1172 /* mes */ 1173 bool enable_mes; 1174 bool enable_mes_kiq; 1175 bool enable_uni_mes; 1176 struct amdgpu_mes mes; 1177 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1178 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1179 1180 /* xarray used to retrieve the user queue fence driver reference 1181 * in the EOP interrupt handler to signal the particular user 1182 * queue fence. 1183 */ 1184 struct xarray userq_xa; 1185 1186 /* df */ 1187 struct amdgpu_df df; 1188 1189 /* MCA */ 1190 struct amdgpu_mca mca; 1191 1192 /* ACA */ 1193 struct amdgpu_aca aca; 1194 1195 /* CPER */ 1196 struct amdgpu_cper cper; 1197 1198 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1199 uint32_t harvest_ip_mask; 1200 int num_ip_blocks; 1201 struct mutex mn_lock; 1202 DECLARE_HASHTABLE(mn_hash, 7); 1203 1204 /* tracking pinned memory */ 1205 atomic64_t vram_pin_size; 1206 atomic64_t visible_pin_size; 1207 atomic64_t gart_pin_size; 1208 1209 /* soc15 register offset based on ip, instance and segment */ 1210 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1211 struct amdgpu_ip_map_info ip_map; 1212 1213 /* delayed work_func for deferring clockgating during resume */ 1214 struct delayed_work delayed_init_work; 1215 1216 struct amdgpu_virt virt; 1217 1218 /* record hw reset is performed */ 1219 bool has_hw_reset; 1220 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1221 1222 /* s3/s4 mask */ 1223 bool in_suspend; 1224 bool in_s3; 1225 bool in_s4; 1226 bool in_s0ix; 1227 suspend_state_t last_suspend_state; 1228 1229 enum pp_mp1_state mp1_state; 1230 struct amdgpu_doorbell_index doorbell_index; 1231 1232 struct mutex notifier_lock; 1233 1234 int asic_reset_res; 1235 struct work_struct xgmi_reset_work; 1236 struct list_head reset_list; 1237 1238 long gfx_timeout; 1239 long sdma_timeout; 1240 long video_timeout; 1241 long compute_timeout; 1242 long psp_timeout; 1243 1244 uint64_t unique_id; 1245 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1246 1247 /* enable runtime pm on the device */ 1248 bool in_runpm; 1249 bool has_pr3; 1250 1251 bool ucode_sysfs_en; 1252 1253 struct amdgpu_fru_info *fru_info; 1254 atomic_t throttling_logging_enabled; 1255 struct ratelimit_state throttling_logging_rs; 1256 uint32_t ras_hw_enabled; 1257 uint32_t ras_enabled; 1258 bool ras_default_ecc_enabled; 1259 1260 bool no_hw_access; 1261 struct pci_saved_state *pci_state; 1262 pci_channel_state_t pci_channel_state; 1263 1264 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1265 1266 /* Track auto wait count on s_barrier settings */ 1267 bool barrier_has_auto_waitcnt; 1268 1269 struct amdgpu_reset_control *reset_cntl; 1270 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1271 1272 bool ram_is_direct_mapped; 1273 1274 struct list_head ras_list; 1275 1276 struct ip_discovery_top *ip_top; 1277 1278 struct amdgpu_reset_domain *reset_domain; 1279 1280 struct mutex benchmark_mutex; 1281 1282 bool scpm_enabled; 1283 uint32_t scpm_status; 1284 1285 struct work_struct reset_work; 1286 1287 bool dc_enabled; 1288 /* Mask of active clusters */ 1289 uint32_t aid_mask; 1290 1291 /* Debug */ 1292 bool debug_vm; 1293 bool debug_largebar; 1294 bool debug_disable_soft_recovery; 1295 bool debug_use_vram_fw_buf; 1296 bool debug_enable_ras_aca; 1297 bool debug_exp_resets; 1298 bool debug_disable_gpu_ring_reset; 1299 bool debug_vm_userptr; 1300 bool debug_disable_ce_logs; 1301 1302 /* Protection for the following isolation structure */ 1303 struct mutex enforce_isolation_mutex; 1304 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1305 struct amdgpu_isolation { 1306 void *owner; 1307 struct dma_fence *spearhead; 1308 struct amdgpu_sync active; 1309 struct amdgpu_sync prev; 1310 } isolation[MAX_XCP]; 1311 1312 struct amdgpu_init_level *init_lvl; 1313 1314 /* This flag is used to determine how VRAM allocations are handled for APUs 1315 * in KFD: VRAM or GTT. 1316 */ 1317 bool apu_prefer_gtt; 1318 1319 struct list_head userq_mgr_list; 1320 struct mutex userq_mutex; 1321 bool userq_halt_for_enforce_isolation; 1322 struct amdgpu_uid *uid_info; 1323 }; 1324 1325 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1326 uint8_t ip, uint8_t inst) 1327 { 1328 /* This considers only major/minor/rev and ignores 1329 * subrevision/variant fields. 1330 */ 1331 return adev->ip_versions[ip][inst] & ~0xFFU; 1332 } 1333 1334 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1335 uint8_t ip, uint8_t inst) 1336 { 1337 /* This returns full version - major/minor/rev/variant/subrevision */ 1338 return adev->ip_versions[ip][inst]; 1339 } 1340 1341 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1342 { 1343 return container_of(ddev, struct amdgpu_device, ddev); 1344 } 1345 1346 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1347 { 1348 return &adev->ddev; 1349 } 1350 1351 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1352 { 1353 return container_of(bdev, struct amdgpu_device, mman.bdev); 1354 } 1355 1356 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1357 { 1358 return !!adev->aid_mask; 1359 } 1360 1361 int amdgpu_device_init(struct amdgpu_device *adev, 1362 uint32_t flags); 1363 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1364 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1365 1366 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1367 1368 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1369 void *buf, size_t size, bool write); 1370 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1371 void *buf, size_t size, bool write); 1372 1373 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1374 void *buf, size_t size, bool write); 1375 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1376 uint32_t inst, uint32_t reg_addr, char reg_name[], 1377 uint32_t expected_value, uint32_t mask); 1378 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1379 uint32_t reg, uint32_t acc_flags); 1380 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1381 u64 reg_addr); 1382 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1383 uint32_t reg, uint32_t acc_flags, 1384 uint32_t xcc_id); 1385 void amdgpu_device_wreg(struct amdgpu_device *adev, 1386 uint32_t reg, uint32_t v, 1387 uint32_t acc_flags); 1388 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1389 u64 reg_addr, u32 reg_data); 1390 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1391 uint32_t reg, uint32_t v, 1392 uint32_t acc_flags, 1393 uint32_t xcc_id); 1394 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1395 uint32_t reg, uint32_t v, uint32_t xcc_id); 1396 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1397 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1398 1399 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1400 u32 reg_addr); 1401 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1402 u32 reg_addr); 1403 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1404 u64 reg_addr); 1405 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1406 u32 reg_addr, u32 reg_data); 1407 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1408 u32 reg_addr, u64 reg_data); 1409 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1410 u64 reg_addr, u64 reg_data); 1411 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1412 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1413 enum amd_asic_type asic_type); 1414 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1415 1416 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1417 1418 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1419 struct amdgpu_reset_context *reset_context); 1420 1421 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1422 struct amdgpu_reset_context *reset_context); 1423 1424 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1425 1426 int emu_soc_asic_init(struct amdgpu_device *adev); 1427 1428 /* 1429 * Registers read & write functions. 1430 */ 1431 #define AMDGPU_REGS_NO_KIQ (1<<1) 1432 #define AMDGPU_REGS_RLC (1<<2) 1433 1434 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1435 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1436 1437 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1438 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1439 1440 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1441 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1442 1443 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1444 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1445 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1446 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1447 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1448 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1449 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1450 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1451 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1452 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1453 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1454 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1455 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1456 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1457 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1458 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1459 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1460 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1461 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1462 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1463 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1464 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1465 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1466 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1467 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1468 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1469 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1470 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1471 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1472 #define WREG32_P(reg, val, mask) \ 1473 do { \ 1474 uint32_t tmp_ = RREG32(reg); \ 1475 tmp_ &= (mask); \ 1476 tmp_ |= ((val) & ~(mask)); \ 1477 WREG32(reg, tmp_); \ 1478 } while (0) 1479 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1480 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1481 #define WREG32_PLL_P(reg, val, mask) \ 1482 do { \ 1483 uint32_t tmp_ = RREG32_PLL(reg); \ 1484 tmp_ &= (mask); \ 1485 tmp_ |= ((val) & ~(mask)); \ 1486 WREG32_PLL(reg, tmp_); \ 1487 } while (0) 1488 1489 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1490 do { \ 1491 u32 tmp = RREG32_SMC(_Reg); \ 1492 tmp &= (_Mask); \ 1493 tmp |= ((_Val) & ~(_Mask)); \ 1494 WREG32_SMC(_Reg, tmp); \ 1495 } while (0) 1496 1497 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1498 1499 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1500 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1501 1502 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1503 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1504 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1505 1506 #define REG_GET_FIELD(value, reg, field) \ 1507 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1508 1509 #define WREG32_FIELD(reg, field, val) \ 1510 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1511 1512 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1513 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1514 1515 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1516 /* 1517 * BIOS helpers. 1518 */ 1519 #define RBIOS8(i) (adev->bios[i]) 1520 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1521 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1522 1523 /* 1524 * ASICs macro. 1525 */ 1526 #define amdgpu_asic_set_vga_state(adev, state) \ 1527 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1528 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1529 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1530 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1531 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1532 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1533 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1534 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1535 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1536 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1537 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1538 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1539 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1540 #define amdgpu_asic_flush_hdp(adev, r) \ 1541 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1542 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1543 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1544 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1545 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1546 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1547 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1548 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1549 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1550 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1551 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1552 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1553 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1554 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1555 1556 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1557 1558 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1559 #define for_each_inst(i, inst_mask) \ 1560 for (i = ffs(inst_mask); i-- != 0; \ 1561 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1562 1563 /* Common functions */ 1564 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1565 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1566 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1567 struct amdgpu_job *job, 1568 struct amdgpu_reset_context *reset_context); 1569 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1570 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1571 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1572 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1573 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1574 1575 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1576 u64 num_vis_bytes); 1577 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1578 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1579 const u32 *registers, 1580 const u32 array_size); 1581 1582 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1583 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1584 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1585 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1586 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1587 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1588 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1589 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1590 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1591 struct amdgpu_device *peer_adev); 1592 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1593 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1594 1595 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1596 struct amdgpu_ring *ring); 1597 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1598 struct amdgpu_ring *ring); 1599 1600 void amdgpu_device_halt(struct amdgpu_device *adev); 1601 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1602 u32 reg); 1603 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1604 u32 reg, u32 v); 1605 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1606 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1607 struct dma_fence *gang); 1608 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1609 struct amdgpu_ring *ring, 1610 struct amdgpu_job *job); 1611 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1612 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1613 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1614 1615 /* atpx handler */ 1616 #if defined(CONFIG_VGA_SWITCHEROO) 1617 void amdgpu_register_atpx_handler(void); 1618 void amdgpu_unregister_atpx_handler(void); 1619 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1620 bool amdgpu_is_atpx_hybrid(void); 1621 bool amdgpu_has_atpx(void); 1622 #else 1623 static inline void amdgpu_register_atpx_handler(void) {} 1624 static inline void amdgpu_unregister_atpx_handler(void) {} 1625 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1626 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1627 static inline bool amdgpu_has_atpx(void) { return false; } 1628 #endif 1629 1630 /* 1631 * KMS 1632 */ 1633 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1634 extern const int amdgpu_max_kms_ioctl; 1635 1636 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1637 void amdgpu_driver_unload_kms(struct drm_device *dev); 1638 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1639 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1640 struct drm_file *file_priv); 1641 void amdgpu_driver_release_kms(struct drm_device *dev); 1642 1643 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1644 int amdgpu_device_prepare(struct drm_device *dev); 1645 void amdgpu_device_complete(struct drm_device *dev); 1646 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1647 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1648 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1649 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1650 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1651 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1652 struct drm_file *filp); 1653 1654 /* 1655 * functions used by amdgpu_encoder.c 1656 */ 1657 struct amdgpu_afmt_acr { 1658 u32 clock; 1659 1660 int n_32khz; 1661 int cts_32khz; 1662 1663 int n_44_1khz; 1664 int cts_44_1khz; 1665 1666 int n_48khz; 1667 int cts_48khz; 1668 1669 }; 1670 1671 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1672 1673 /* amdgpu_acpi.c */ 1674 1675 struct amdgpu_numa_info { 1676 uint64_t size; 1677 int pxm; 1678 int nid; 1679 }; 1680 1681 /* ATCS Device/Driver State */ 1682 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1683 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1684 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1685 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1686 1687 #if defined(CONFIG_ACPI) 1688 int amdgpu_acpi_init(struct amdgpu_device *adev); 1689 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1690 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1691 bool amdgpu_acpi_is_power_shift_control_supported(void); 1692 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1693 u8 perf_req, bool advertise); 1694 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1695 u8 dev_state, bool drv_state); 1696 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1697 enum amdgpu_ss ss_state); 1698 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1699 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1700 u64 *tmr_size); 1701 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1702 struct amdgpu_numa_info *numa_info); 1703 1704 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1705 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1706 void amdgpu_acpi_detect(void); 1707 void amdgpu_acpi_release(void); 1708 #else 1709 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1710 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1711 u64 *tmr_offset, u64 *tmr_size) 1712 { 1713 return -EINVAL; 1714 } 1715 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1716 int xcc_id, 1717 struct amdgpu_numa_info *numa_info) 1718 { 1719 return -EINVAL; 1720 } 1721 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1722 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1723 static inline void amdgpu_acpi_detect(void) { } 1724 static inline void amdgpu_acpi_release(void) { } 1725 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1726 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1727 u8 dev_state, bool drv_state) { return 0; } 1728 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1729 enum amdgpu_ss ss_state) 1730 { 1731 return 0; 1732 } 1733 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1734 #endif 1735 1736 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1737 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1738 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1739 #else 1740 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1741 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1742 #endif 1743 1744 #if defined(CONFIG_DRM_AMD_ISP) 1745 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1746 #endif 1747 1748 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1749 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1750 1751 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1752 pci_channel_state_t state); 1753 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1754 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1755 void amdgpu_pci_resume(struct pci_dev *pdev); 1756 1757 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1758 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1759 1760 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1761 1762 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1763 enum amd_clockgating_state state); 1764 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1765 enum amd_powergating_state state); 1766 1767 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1768 { 1769 return amdgpu_gpu_recovery != 0 && 1770 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1771 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1772 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1773 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1774 } 1775 1776 #include "amdgpu_object.h" 1777 1778 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1779 { 1780 return adev->gmc.tmz_enabled; 1781 } 1782 1783 int amdgpu_in_reset(struct amdgpu_device *adev); 1784 1785 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1786 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1787 extern const struct attribute_group amdgpu_flash_attr_group; 1788 1789 void amdgpu_set_init_level(struct amdgpu_device *adev, 1790 enum amdgpu_init_lvl_id lvl); 1791 1792 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1793 { 1794 u32 status; 1795 int r; 1796 1797 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1798 if (r || PCI_POSSIBLE_ERROR(status)) { 1799 dev_err(adev->dev, "device lost from bus!"); 1800 return -ENODEV; 1801 } 1802 1803 return 0; 1804 } 1805 1806 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1807 enum amdgpu_uid_type type, uint8_t inst, 1808 uint64_t uid); 1809 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1810 enum amdgpu_uid_type type, uint8_t inst); 1811 #endif 1812