1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/rbtree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <drm/ttm/ttm_bo_api.h> 40 #include <drm/ttm/ttm_bo_driver.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <drm/ttm/ttm_module.h> 43 #include <drm/ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include <kgd_kfd_interface.h> 50 51 #include "amd_shared.h" 52 #include "amdgpu_mode.h" 53 #include "amdgpu_ih.h" 54 #include "amdgpu_irq.h" 55 #include "amdgpu_ucode.h" 56 #include "amdgpu_ttm.h" 57 #include "amdgpu_psp.h" 58 #include "amdgpu_gds.h" 59 #include "amdgpu_sync.h" 60 #include "amdgpu_ring.h" 61 #include "amdgpu_vm.h" 62 #include "amd_powerplay.h" 63 #include "amdgpu_dpm.h" 64 #include "amdgpu_acp.h" 65 #include "amdgpu_uvd.h" 66 #include "amdgpu_vce.h" 67 #include "amdgpu_vcn.h" 68 #include "amdgpu_mn.h" 69 70 #include "gpu_scheduler.h" 71 #include "amdgpu_virt.h" 72 #include "amdgpu_gart.h" 73 74 /* 75 * Modules parameters. 76 */ 77 extern int amdgpu_modeset; 78 extern int amdgpu_vram_limit; 79 extern int amdgpu_vis_vram_limit; 80 extern int amdgpu_gart_size; 81 extern int amdgpu_gtt_size; 82 extern int amdgpu_moverate; 83 extern int amdgpu_benchmarking; 84 extern int amdgpu_testing; 85 extern int amdgpu_audio; 86 extern int amdgpu_disp_priority; 87 extern int amdgpu_hw_i2c; 88 extern int amdgpu_pcie_gen2; 89 extern int amdgpu_msi; 90 extern int amdgpu_lockup_timeout; 91 extern int amdgpu_dpm; 92 extern int amdgpu_fw_load_type; 93 extern int amdgpu_aspm; 94 extern int amdgpu_runtime_pm; 95 extern uint amdgpu_ip_block_mask; 96 extern int amdgpu_bapm; 97 extern int amdgpu_deep_color; 98 extern int amdgpu_vm_size; 99 extern int amdgpu_vm_block_size; 100 extern int amdgpu_vm_fragment_size; 101 extern int amdgpu_vm_fault_stop; 102 extern int amdgpu_vm_debug; 103 extern int amdgpu_vm_update_mode; 104 extern int amdgpu_sched_jobs; 105 extern int amdgpu_sched_hw_submission; 106 extern int amdgpu_no_evict; 107 extern int amdgpu_direct_gma_size; 108 extern uint amdgpu_pcie_gen_cap; 109 extern uint amdgpu_pcie_lane_cap; 110 extern uint amdgpu_cg_mask; 111 extern uint amdgpu_pg_mask; 112 extern uint amdgpu_sdma_phase_quantum; 113 extern char *amdgpu_disable_cu; 114 extern char *amdgpu_virtual_display; 115 extern uint amdgpu_pp_feature_mask; 116 extern int amdgpu_vram_page_split; 117 extern int amdgpu_ngg; 118 extern int amdgpu_prim_buf_per_se; 119 extern int amdgpu_pos_buf_per_se; 120 extern int amdgpu_cntl_sb_buf_per_se; 121 extern int amdgpu_param_buf_per_se; 122 extern int amdgpu_job_hang_limit; 123 extern int amdgpu_lbpw; 124 extern int amdgpu_compute_multipipe; 125 126 #ifdef CONFIG_DRM_AMDGPU_SI 127 extern int amdgpu_si_support; 128 #endif 129 #ifdef CONFIG_DRM_AMDGPU_CIK 130 extern int amdgpu_cik_support; 131 #endif 132 133 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 134 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 135 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 136 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 137 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 138 #define AMDGPU_IB_POOL_SIZE 16 139 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 140 #define AMDGPUFB_CONN_LIMIT 4 141 #define AMDGPU_BIOS_NUM_SCRATCH 16 142 143 /* max number of IP instances */ 144 #define AMDGPU_MAX_SDMA_INSTANCES 2 145 146 /* hard reset data */ 147 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 148 149 /* reset flags */ 150 #define AMDGPU_RESET_GFX (1 << 0) 151 #define AMDGPU_RESET_COMPUTE (1 << 1) 152 #define AMDGPU_RESET_DMA (1 << 2) 153 #define AMDGPU_RESET_CP (1 << 3) 154 #define AMDGPU_RESET_GRBM (1 << 4) 155 #define AMDGPU_RESET_DMA1 (1 << 5) 156 #define AMDGPU_RESET_RLC (1 << 6) 157 #define AMDGPU_RESET_SEM (1 << 7) 158 #define AMDGPU_RESET_IH (1 << 8) 159 #define AMDGPU_RESET_VMC (1 << 9) 160 #define AMDGPU_RESET_MC (1 << 10) 161 #define AMDGPU_RESET_DISPLAY (1 << 11) 162 #define AMDGPU_RESET_UVD (1 << 12) 163 #define AMDGPU_RESET_VCE (1 << 13) 164 #define AMDGPU_RESET_VCE1 (1 << 14) 165 166 /* GFX current status */ 167 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 168 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 169 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 170 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 171 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 172 173 /* max cursor sizes (in pixels) */ 174 #define CIK_CURSOR_WIDTH 128 175 #define CIK_CURSOR_HEIGHT 128 176 177 struct amdgpu_device; 178 struct amdgpu_ib; 179 struct amdgpu_cs_parser; 180 struct amdgpu_job; 181 struct amdgpu_irq_src; 182 struct amdgpu_fpriv; 183 struct amdgpu_bo_va_mapping; 184 185 enum amdgpu_cp_irq { 186 AMDGPU_CP_IRQ_GFX_EOP = 0, 187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 188 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 189 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 192 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 193 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 195 196 AMDGPU_CP_IRQ_LAST 197 }; 198 199 enum amdgpu_sdma_irq { 200 AMDGPU_SDMA_IRQ_TRAP0 = 0, 201 AMDGPU_SDMA_IRQ_TRAP1, 202 203 AMDGPU_SDMA_IRQ_LAST 204 }; 205 206 enum amdgpu_thermal_irq { 207 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 208 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 209 210 AMDGPU_THERMAL_IRQ_LAST 211 }; 212 213 enum amdgpu_kiq_irq { 214 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 215 AMDGPU_CP_KIQ_IRQ_LAST 216 }; 217 218 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 219 enum amd_ip_block_type block_type, 220 enum amd_clockgating_state state); 221 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 222 enum amd_ip_block_type block_type, 223 enum amd_powergating_state state); 224 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 225 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 226 enum amd_ip_block_type block_type); 227 bool amdgpu_is_idle(struct amdgpu_device *adev, 228 enum amd_ip_block_type block_type); 229 230 #define AMDGPU_MAX_IP_NUM 16 231 232 struct amdgpu_ip_block_status { 233 bool valid; 234 bool sw; 235 bool hw; 236 bool late_initialized; 237 bool hang; 238 }; 239 240 struct amdgpu_ip_block_version { 241 const enum amd_ip_block_type type; 242 const u32 major; 243 const u32 minor; 244 const u32 rev; 245 const struct amd_ip_funcs *funcs; 246 }; 247 248 struct amdgpu_ip_block { 249 struct amdgpu_ip_block_status status; 250 const struct amdgpu_ip_block_version *version; 251 }; 252 253 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 254 enum amd_ip_block_type type, 255 u32 major, u32 minor); 256 257 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 258 enum amd_ip_block_type type); 259 260 int amdgpu_ip_block_add(struct amdgpu_device *adev, 261 const struct amdgpu_ip_block_version *ip_block_version); 262 263 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 264 struct amdgpu_buffer_funcs { 265 /* maximum bytes in a single operation */ 266 uint32_t copy_max_bytes; 267 268 /* number of dw to reserve per operation */ 269 unsigned copy_num_dw; 270 271 /* used for buffer migration */ 272 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 273 /* src addr in bytes */ 274 uint64_t src_offset, 275 /* dst addr in bytes */ 276 uint64_t dst_offset, 277 /* number of byte to transfer */ 278 uint32_t byte_count); 279 280 /* maximum bytes in a single operation */ 281 uint32_t fill_max_bytes; 282 283 /* number of dw to reserve per operation */ 284 unsigned fill_num_dw; 285 286 /* used for buffer clearing */ 287 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 288 /* value to write to memory */ 289 uint32_t src_data, 290 /* dst addr in bytes */ 291 uint64_t dst_offset, 292 /* number of byte to fill */ 293 uint32_t byte_count); 294 }; 295 296 /* provided by hw blocks that can write ptes, e.g., sdma */ 297 struct amdgpu_vm_pte_funcs { 298 /* number of dw to reserve per operation */ 299 unsigned copy_pte_num_dw; 300 301 /* copy pte entries from GART */ 302 void (*copy_pte)(struct amdgpu_ib *ib, 303 uint64_t pe, uint64_t src, 304 unsigned count); 305 306 /* write pte one entry at a time with addr mapping */ 307 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 308 uint64_t value, unsigned count, 309 uint32_t incr); 310 311 /* maximum nums of PTEs/PDEs in a single operation */ 312 uint32_t set_max_nums_pte_pde; 313 314 /* number of dw to reserve per operation */ 315 unsigned set_pte_pde_num_dw; 316 317 /* for linear pte/pde updates without addr mapping */ 318 void (*set_pte_pde)(struct amdgpu_ib *ib, 319 uint64_t pe, 320 uint64_t addr, unsigned count, 321 uint32_t incr, uint64_t flags); 322 }; 323 324 /* provided by the gmc block */ 325 struct amdgpu_gart_funcs { 326 /* flush the vm tlb via mmio */ 327 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 328 uint32_t vmid); 329 /* write pte/pde updates using the cpu */ 330 int (*set_pte_pde)(struct amdgpu_device *adev, 331 void *cpu_pt_addr, /* cpu addr of page table */ 332 uint32_t gpu_page_idx, /* pte/pde to update */ 333 uint64_t addr, /* addr to write into pte/pde */ 334 uint64_t flags); /* access flags */ 335 /* enable/disable PRT support */ 336 void (*set_prt)(struct amdgpu_device *adev, bool enable); 337 /* set pte flags based per asic */ 338 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 339 uint32_t flags); 340 /* get the pde for a given mc addr */ 341 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr); 342 uint32_t (*get_invalidate_req)(unsigned int vm_id); 343 }; 344 345 /* provided by the ih block */ 346 struct amdgpu_ih_funcs { 347 /* ring read/write ptr handling, called from interrupt context */ 348 u32 (*get_wptr)(struct amdgpu_device *adev); 349 bool (*prescreen_iv)(struct amdgpu_device *adev); 350 void (*decode_iv)(struct amdgpu_device *adev, 351 struct amdgpu_iv_entry *entry); 352 void (*set_rptr)(struct amdgpu_device *adev); 353 }; 354 355 /* 356 * BIOS. 357 */ 358 bool amdgpu_get_bios(struct amdgpu_device *adev); 359 bool amdgpu_read_bios(struct amdgpu_device *adev); 360 361 /* 362 * Dummy page 363 */ 364 struct amdgpu_dummy_page { 365 struct page *page; 366 dma_addr_t addr; 367 }; 368 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 369 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 370 371 372 /* 373 * Clocks 374 */ 375 376 #define AMDGPU_MAX_PPLL 3 377 378 struct amdgpu_clock { 379 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 380 struct amdgpu_pll spll; 381 struct amdgpu_pll mpll; 382 /* 10 Khz units */ 383 uint32_t default_mclk; 384 uint32_t default_sclk; 385 uint32_t default_dispclk; 386 uint32_t current_dispclk; 387 uint32_t dp_extclk; 388 uint32_t max_pixel_clock; 389 }; 390 391 /* 392 * GEM. 393 */ 394 395 #define AMDGPU_GEM_DOMAIN_MAX 0x3 396 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 397 398 void amdgpu_gem_object_free(struct drm_gem_object *obj); 399 int amdgpu_gem_object_open(struct drm_gem_object *obj, 400 struct drm_file *file_priv); 401 void amdgpu_gem_object_close(struct drm_gem_object *obj, 402 struct drm_file *file_priv); 403 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 404 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 405 struct drm_gem_object * 406 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 407 struct dma_buf_attachment *attach, 408 struct sg_table *sg); 409 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 410 struct drm_gem_object *gobj, 411 int flags); 412 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 413 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 414 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 415 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 416 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 417 int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 418 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 419 420 /* sub-allocation manager, it has to be protected by another lock. 421 * By conception this is an helper for other part of the driver 422 * like the indirect buffer or semaphore, which both have their 423 * locking. 424 * 425 * Principe is simple, we keep a list of sub allocation in offset 426 * order (first entry has offset == 0, last entry has the highest 427 * offset). 428 * 429 * When allocating new object we first check if there is room at 430 * the end total_size - (last_object_offset + last_object_size) >= 431 * alloc_size. If so we allocate new object there. 432 * 433 * When there is not enough room at the end, we start waiting for 434 * each sub object until we reach object_offset+object_size >= 435 * alloc_size, this object then become the sub object we return. 436 * 437 * Alignment can't be bigger than page size. 438 * 439 * Hole are not considered for allocation to keep things simple. 440 * Assumption is that there won't be hole (all object on same 441 * alignment). 442 */ 443 444 #define AMDGPU_SA_NUM_FENCE_LISTS 32 445 446 struct amdgpu_sa_manager { 447 wait_queue_head_t wq; 448 struct amdgpu_bo *bo; 449 struct list_head *hole; 450 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 451 struct list_head olist; 452 unsigned size; 453 uint64_t gpu_addr; 454 void *cpu_ptr; 455 uint32_t domain; 456 uint32_t align; 457 }; 458 459 /* sub-allocation buffer */ 460 struct amdgpu_sa_bo { 461 struct list_head olist; 462 struct list_head flist; 463 struct amdgpu_sa_manager *manager; 464 unsigned soffset; 465 unsigned eoffset; 466 struct dma_fence *fence; 467 }; 468 469 /* 470 * GEM objects. 471 */ 472 void amdgpu_gem_force_release(struct amdgpu_device *adev); 473 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 474 int alignment, u32 initial_domain, 475 u64 flags, bool kernel, 476 struct reservation_object *resv, 477 struct drm_gem_object **obj); 478 479 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 480 struct drm_device *dev, 481 struct drm_mode_create_dumb *args); 482 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 483 struct drm_device *dev, 484 uint32_t handle, uint64_t *offset_p); 485 int amdgpu_fence_slab_init(void); 486 void amdgpu_fence_slab_fini(void); 487 488 /* 489 * VMHUB structures, functions & helpers 490 */ 491 struct amdgpu_vmhub { 492 uint32_t ctx0_ptb_addr_lo32; 493 uint32_t ctx0_ptb_addr_hi32; 494 uint32_t vm_inv_eng0_req; 495 uint32_t vm_inv_eng0_ack; 496 uint32_t vm_context0_cntl; 497 uint32_t vm_l2_pro_fault_status; 498 uint32_t vm_l2_pro_fault_cntl; 499 }; 500 501 /* 502 * GPU MC structures, functions & helpers 503 */ 504 struct amdgpu_mc { 505 resource_size_t aper_size; 506 resource_size_t aper_base; 507 resource_size_t agp_base; 508 /* for some chips with <= 32MB we need to lie 509 * about vram size near mc fb location */ 510 u64 mc_vram_size; 511 u64 visible_vram_size; 512 u64 gart_size; 513 u64 gart_start; 514 u64 gart_end; 515 u64 vram_start; 516 u64 vram_end; 517 unsigned vram_width; 518 u64 real_vram_size; 519 int vram_mtrr; 520 u64 mc_mask; 521 const struct firmware *fw; /* MC firmware */ 522 uint32_t fw_version; 523 struct amdgpu_irq_src vm_fault; 524 uint32_t vram_type; 525 uint32_t srbm_soft_reset; 526 bool prt_warning; 527 uint64_t stolen_size; 528 /* apertures */ 529 u64 shared_aperture_start; 530 u64 shared_aperture_end; 531 u64 private_aperture_start; 532 u64 private_aperture_end; 533 /* protects concurrent invalidation */ 534 spinlock_t invalidate_lock; 535 }; 536 537 /* 538 * GPU doorbell structures, functions & helpers 539 */ 540 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 541 { 542 AMDGPU_DOORBELL_KIQ = 0x000, 543 AMDGPU_DOORBELL_HIQ = 0x001, 544 AMDGPU_DOORBELL_DIQ = 0x002, 545 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 546 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 547 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 548 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 549 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 550 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 551 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 552 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 553 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 554 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 555 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 556 AMDGPU_DOORBELL_IH = 0x1E8, 557 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 558 AMDGPU_DOORBELL_INVALID = 0xFFFF 559 } AMDGPU_DOORBELL_ASSIGNMENT; 560 561 struct amdgpu_doorbell { 562 /* doorbell mmio */ 563 resource_size_t base; 564 resource_size_t size; 565 u32 __iomem *ptr; 566 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 567 }; 568 569 /* 570 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 571 */ 572 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 573 { 574 /* 575 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 576 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 577 * Compute related doorbells are allocated from 0x00 to 0x8a 578 */ 579 580 581 /* kernel scheduling */ 582 AMDGPU_DOORBELL64_KIQ = 0x00, 583 584 /* HSA interface queue and debug queue */ 585 AMDGPU_DOORBELL64_HIQ = 0x01, 586 AMDGPU_DOORBELL64_DIQ = 0x02, 587 588 /* Compute engines */ 589 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 590 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 591 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 592 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 593 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 594 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 595 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 596 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 597 598 /* User queue doorbell range (128 doorbells) */ 599 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 600 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 601 602 /* Graphics engine */ 603 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 604 605 /* 606 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 607 * Graphics voltage island aperture 1 608 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 609 */ 610 611 /* sDMA engines */ 612 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 613 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 614 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 615 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 616 617 /* Interrupt handler */ 618 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 619 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 620 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 621 622 /* VCN engine use 32 bits doorbell */ 623 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 624 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 625 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 626 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 627 628 /* overlap the doorbell assignment with VCN as they are mutually exclusive 629 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 630 */ 631 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 632 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 633 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 634 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 635 636 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 637 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 638 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 639 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 640 641 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 642 AMDGPU_DOORBELL64_INVALID = 0xFFFF 643 } AMDGPU_DOORBELL64_ASSIGNMENT; 644 645 646 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 647 phys_addr_t *aperture_base, 648 size_t *aperture_size, 649 size_t *start_offset); 650 651 /* 652 * IRQS. 653 */ 654 655 struct amdgpu_flip_work { 656 struct delayed_work flip_work; 657 struct work_struct unpin_work; 658 struct amdgpu_device *adev; 659 int crtc_id; 660 u32 target_vblank; 661 uint64_t base; 662 struct drm_pending_vblank_event *event; 663 struct amdgpu_bo *old_abo; 664 struct dma_fence *excl; 665 unsigned shared_count; 666 struct dma_fence **shared; 667 struct dma_fence_cb cb; 668 bool async; 669 }; 670 671 672 /* 673 * CP & rings. 674 */ 675 676 struct amdgpu_ib { 677 struct amdgpu_sa_bo *sa_bo; 678 uint32_t length_dw; 679 uint64_t gpu_addr; 680 uint32_t *ptr; 681 uint32_t flags; 682 }; 683 684 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 685 686 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 687 struct amdgpu_job **job, struct amdgpu_vm *vm); 688 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 689 struct amdgpu_job **job); 690 691 void amdgpu_job_free_resources(struct amdgpu_job *job); 692 void amdgpu_job_free(struct amdgpu_job *job); 693 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 694 struct amd_sched_entity *entity, void *owner, 695 struct dma_fence **f); 696 697 /* 698 * Queue manager 699 */ 700 struct amdgpu_queue_mapper { 701 int hw_ip; 702 struct mutex lock; 703 /* protected by lock */ 704 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS]; 705 }; 706 707 struct amdgpu_queue_mgr { 708 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM]; 709 }; 710 711 int amdgpu_queue_mgr_init(struct amdgpu_device *adev, 712 struct amdgpu_queue_mgr *mgr); 713 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev, 714 struct amdgpu_queue_mgr *mgr); 715 int amdgpu_queue_mgr_map(struct amdgpu_device *adev, 716 struct amdgpu_queue_mgr *mgr, 717 int hw_ip, int instance, int ring, 718 struct amdgpu_ring **out_ring); 719 720 /* 721 * context related structures 722 */ 723 724 struct amdgpu_ctx_ring { 725 uint64_t sequence; 726 struct dma_fence **fences; 727 struct amd_sched_entity entity; 728 }; 729 730 struct amdgpu_ctx { 731 struct kref refcount; 732 struct amdgpu_device *adev; 733 struct amdgpu_queue_mgr queue_mgr; 734 unsigned reset_counter; 735 uint32_t vram_lost_counter; 736 spinlock_t ring_lock; 737 struct dma_fence **fences; 738 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 739 bool preamble_presented; 740 enum amd_sched_priority init_priority; 741 enum amd_sched_priority override_priority; 742 struct mutex lock; 743 }; 744 745 struct amdgpu_ctx_mgr { 746 struct amdgpu_device *adev; 747 struct mutex lock; 748 /* protected by lock */ 749 struct idr ctx_handles; 750 }; 751 752 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 753 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 754 755 int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 756 struct dma_fence *fence, uint64_t *seq); 757 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 758 struct amdgpu_ring *ring, uint64_t seq); 759 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 760 enum amd_sched_priority priority); 761 762 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 763 struct drm_file *filp); 764 765 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id); 766 767 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 768 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 769 770 771 /* 772 * file private structure 773 */ 774 775 struct amdgpu_fpriv { 776 struct amdgpu_vm vm; 777 struct amdgpu_bo_va *prt_va; 778 struct amdgpu_bo_va *csa_va; 779 struct mutex bo_list_lock; 780 struct idr bo_list_handles; 781 struct amdgpu_ctx_mgr ctx_mgr; 782 }; 783 784 /* 785 * residency list 786 */ 787 struct amdgpu_bo_list_entry { 788 struct amdgpu_bo *robj; 789 struct ttm_validate_buffer tv; 790 struct amdgpu_bo_va *bo_va; 791 uint32_t priority; 792 struct page **user_pages; 793 int user_invalidated; 794 }; 795 796 struct amdgpu_bo_list { 797 struct mutex lock; 798 struct rcu_head rhead; 799 struct kref refcount; 800 struct amdgpu_bo *gds_obj; 801 struct amdgpu_bo *gws_obj; 802 struct amdgpu_bo *oa_obj; 803 unsigned first_userptr; 804 unsigned num_entries; 805 struct amdgpu_bo_list_entry *array; 806 }; 807 808 struct amdgpu_bo_list * 809 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 810 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 811 struct list_head *validated); 812 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 813 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 814 815 /* 816 * GFX stuff 817 */ 818 #include "clearstate_defs.h" 819 820 struct amdgpu_rlc_funcs { 821 void (*enter_safe_mode)(struct amdgpu_device *adev); 822 void (*exit_safe_mode)(struct amdgpu_device *adev); 823 }; 824 825 struct amdgpu_rlc { 826 /* for power gating */ 827 struct amdgpu_bo *save_restore_obj; 828 uint64_t save_restore_gpu_addr; 829 volatile uint32_t *sr_ptr; 830 const u32 *reg_list; 831 u32 reg_list_size; 832 /* for clear state */ 833 struct amdgpu_bo *clear_state_obj; 834 uint64_t clear_state_gpu_addr; 835 volatile uint32_t *cs_ptr; 836 const struct cs_section_def *cs_data; 837 u32 clear_state_size; 838 /* for cp tables */ 839 struct amdgpu_bo *cp_table_obj; 840 uint64_t cp_table_gpu_addr; 841 volatile uint32_t *cp_table_ptr; 842 u32 cp_table_size; 843 844 /* safe mode for updating CG/PG state */ 845 bool in_safe_mode; 846 const struct amdgpu_rlc_funcs *funcs; 847 848 /* for firmware data */ 849 u32 save_and_restore_offset; 850 u32 clear_state_descriptor_offset; 851 u32 avail_scratch_ram_locations; 852 u32 reg_restore_list_size; 853 u32 reg_list_format_start; 854 u32 reg_list_format_separate_start; 855 u32 starting_offsets_start; 856 u32 reg_list_format_size_bytes; 857 u32 reg_list_size_bytes; 858 859 u32 *register_list_format; 860 u32 *register_restore; 861 }; 862 863 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES 864 865 struct amdgpu_mec { 866 struct amdgpu_bo *hpd_eop_obj; 867 u64 hpd_eop_gpu_addr; 868 struct amdgpu_bo *mec_fw_obj; 869 u64 mec_fw_gpu_addr; 870 u32 num_mec; 871 u32 num_pipe_per_mec; 872 u32 num_queue_per_pipe; 873 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 874 875 /* These are the resources for which amdgpu takes ownership */ 876 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 877 }; 878 879 struct amdgpu_kiq { 880 u64 eop_gpu_addr; 881 struct amdgpu_bo *eop_obj; 882 spinlock_t ring_lock; 883 struct amdgpu_ring ring; 884 struct amdgpu_irq_src irq; 885 }; 886 887 /* 888 * GPU scratch registers structures, functions & helpers 889 */ 890 struct amdgpu_scratch { 891 unsigned num_reg; 892 uint32_t reg_base; 893 uint32_t free_mask; 894 }; 895 896 /* 897 * GFX configurations 898 */ 899 #define AMDGPU_GFX_MAX_SE 4 900 #define AMDGPU_GFX_MAX_SH_PER_SE 2 901 902 struct amdgpu_rb_config { 903 uint32_t rb_backend_disable; 904 uint32_t user_rb_backend_disable; 905 uint32_t raster_config; 906 uint32_t raster_config_1; 907 }; 908 909 struct gb_addr_config { 910 uint16_t pipe_interleave_size; 911 uint8_t num_pipes; 912 uint8_t max_compress_frags; 913 uint8_t num_banks; 914 uint8_t num_se; 915 uint8_t num_rb_per_se; 916 }; 917 918 struct amdgpu_gfx_config { 919 unsigned max_shader_engines; 920 unsigned max_tile_pipes; 921 unsigned max_cu_per_sh; 922 unsigned max_sh_per_se; 923 unsigned max_backends_per_se; 924 unsigned max_texture_channel_caches; 925 unsigned max_gprs; 926 unsigned max_gs_threads; 927 unsigned max_hw_contexts; 928 unsigned sc_prim_fifo_size_frontend; 929 unsigned sc_prim_fifo_size_backend; 930 unsigned sc_hiz_tile_fifo_size; 931 unsigned sc_earlyz_tile_fifo_size; 932 933 unsigned num_tile_pipes; 934 unsigned backend_enable_mask; 935 unsigned mem_max_burst_length_bytes; 936 unsigned mem_row_size_in_kb; 937 unsigned shader_engine_tile_size; 938 unsigned num_gpus; 939 unsigned multi_gpu_tile_size; 940 unsigned mc_arb_ramcfg; 941 unsigned gb_addr_config; 942 unsigned num_rbs; 943 unsigned gs_vgt_table_depth; 944 unsigned gs_prim_buffer_depth; 945 946 uint32_t tile_mode_array[32]; 947 uint32_t macrotile_mode_array[16]; 948 949 struct gb_addr_config gb_addr_config_fields; 950 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 951 952 /* gfx configure feature */ 953 uint32_t double_offchip_lds_buf; 954 }; 955 956 struct amdgpu_cu_info { 957 uint32_t max_waves_per_simd; 958 uint32_t wave_front_size; 959 uint32_t max_scratch_slots_per_cu; 960 uint32_t lds_size; 961 962 /* total active CU number */ 963 uint32_t number; 964 uint32_t ao_cu_mask; 965 uint32_t ao_cu_bitmap[4][4]; 966 uint32_t bitmap[4][4]; 967 }; 968 969 struct amdgpu_gfx_funcs { 970 /* get the gpu clock counter */ 971 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 972 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 973 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 974 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 975 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 976 }; 977 978 struct amdgpu_ngg_buf { 979 struct amdgpu_bo *bo; 980 uint64_t gpu_addr; 981 uint32_t size; 982 uint32_t bo_size; 983 }; 984 985 enum { 986 NGG_PRIM = 0, 987 NGG_POS, 988 NGG_CNTL, 989 NGG_PARAM, 990 NGG_BUF_MAX 991 }; 992 993 struct amdgpu_ngg { 994 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 995 uint32_t gds_reserve_addr; 996 uint32_t gds_reserve_size; 997 bool init; 998 }; 999 1000 struct amdgpu_gfx { 1001 struct mutex gpu_clock_mutex; 1002 struct amdgpu_gfx_config config; 1003 struct amdgpu_rlc rlc; 1004 struct amdgpu_mec mec; 1005 struct amdgpu_kiq kiq; 1006 struct amdgpu_scratch scratch; 1007 const struct firmware *me_fw; /* ME firmware */ 1008 uint32_t me_fw_version; 1009 const struct firmware *pfp_fw; /* PFP firmware */ 1010 uint32_t pfp_fw_version; 1011 const struct firmware *ce_fw; /* CE firmware */ 1012 uint32_t ce_fw_version; 1013 const struct firmware *rlc_fw; /* RLC firmware */ 1014 uint32_t rlc_fw_version; 1015 const struct firmware *mec_fw; /* MEC firmware */ 1016 uint32_t mec_fw_version; 1017 const struct firmware *mec2_fw; /* MEC2 firmware */ 1018 uint32_t mec2_fw_version; 1019 uint32_t me_feature_version; 1020 uint32_t ce_feature_version; 1021 uint32_t pfp_feature_version; 1022 uint32_t rlc_feature_version; 1023 uint32_t mec_feature_version; 1024 uint32_t mec2_feature_version; 1025 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1026 unsigned num_gfx_rings; 1027 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1028 unsigned num_compute_rings; 1029 struct amdgpu_irq_src eop_irq; 1030 struct amdgpu_irq_src priv_reg_irq; 1031 struct amdgpu_irq_src priv_inst_irq; 1032 /* gfx status */ 1033 uint32_t gfx_current_status; 1034 /* ce ram size*/ 1035 unsigned ce_ram_size; 1036 struct amdgpu_cu_info cu_info; 1037 const struct amdgpu_gfx_funcs *funcs; 1038 1039 /* reset mask */ 1040 uint32_t grbm_soft_reset; 1041 uint32_t srbm_soft_reset; 1042 /* s3/s4 mask */ 1043 bool in_suspend; 1044 /* NGG */ 1045 struct amdgpu_ngg ngg; 1046 1047 /* pipe reservation */ 1048 struct mutex pipe_reserve_mutex; 1049 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1050 }; 1051 1052 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1053 unsigned size, struct amdgpu_ib *ib); 1054 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1055 struct dma_fence *f); 1056 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1057 struct amdgpu_ib *ibs, struct amdgpu_job *job, 1058 struct dma_fence **f); 1059 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1060 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1061 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1062 1063 /* 1064 * CS. 1065 */ 1066 struct amdgpu_cs_chunk { 1067 uint32_t chunk_id; 1068 uint32_t length_dw; 1069 void *kdata; 1070 }; 1071 1072 struct amdgpu_cs_parser { 1073 struct amdgpu_device *adev; 1074 struct drm_file *filp; 1075 struct amdgpu_ctx *ctx; 1076 1077 /* chunks */ 1078 unsigned nchunks; 1079 struct amdgpu_cs_chunk *chunks; 1080 1081 /* scheduler job object */ 1082 struct amdgpu_job *job; 1083 1084 /* buffer objects */ 1085 struct ww_acquire_ctx ticket; 1086 struct amdgpu_bo_list *bo_list; 1087 struct amdgpu_mn *mn; 1088 struct amdgpu_bo_list_entry vm_pd; 1089 struct list_head validated; 1090 struct dma_fence *fence; 1091 uint64_t bytes_moved_threshold; 1092 uint64_t bytes_moved_vis_threshold; 1093 uint64_t bytes_moved; 1094 uint64_t bytes_moved_vis; 1095 struct amdgpu_bo_list_entry *evictable; 1096 1097 /* user fence */ 1098 struct amdgpu_bo_list_entry uf_entry; 1099 1100 unsigned num_post_dep_syncobjs; 1101 struct drm_syncobj **post_dep_syncobjs; 1102 }; 1103 1104 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1105 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1106 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1107 1108 struct amdgpu_job { 1109 struct amd_sched_job base; 1110 struct amdgpu_device *adev; 1111 struct amdgpu_vm *vm; 1112 struct amdgpu_ring *ring; 1113 struct amdgpu_sync sync; 1114 struct amdgpu_sync dep_sync; 1115 struct amdgpu_sync sched_sync; 1116 struct amdgpu_ib *ibs; 1117 struct dma_fence *fence; /* the hw fence */ 1118 uint32_t preamble_status; 1119 uint32_t num_ibs; 1120 void *owner; 1121 uint64_t fence_ctx; /* the fence_context this job uses */ 1122 bool vm_needs_flush; 1123 unsigned vm_id; 1124 uint64_t vm_pd_addr; 1125 uint32_t gds_base, gds_size; 1126 uint32_t gws_base, gws_size; 1127 uint32_t oa_base, oa_size; 1128 uint32_t vram_lost_counter; 1129 1130 /* user fence handling */ 1131 uint64_t uf_addr; 1132 uint64_t uf_sequence; 1133 1134 }; 1135 #define to_amdgpu_job(sched_job) \ 1136 container_of((sched_job), struct amdgpu_job, base) 1137 1138 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1139 uint32_t ib_idx, int idx) 1140 { 1141 return p->job->ibs[ib_idx].ptr[idx]; 1142 } 1143 1144 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1145 uint32_t ib_idx, int idx, 1146 uint32_t value) 1147 { 1148 p->job->ibs[ib_idx].ptr[idx] = value; 1149 } 1150 1151 /* 1152 * Writeback 1153 */ 1154 #define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */ 1155 1156 struct amdgpu_wb { 1157 struct amdgpu_bo *wb_obj; 1158 volatile uint32_t *wb; 1159 uint64_t gpu_addr; 1160 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1161 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1162 }; 1163 1164 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1165 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1166 1167 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1168 1169 /* 1170 * SDMA 1171 */ 1172 struct amdgpu_sdma_instance { 1173 /* SDMA firmware */ 1174 const struct firmware *fw; 1175 uint32_t fw_version; 1176 uint32_t feature_version; 1177 1178 struct amdgpu_ring ring; 1179 bool burst_nop; 1180 }; 1181 1182 struct amdgpu_sdma { 1183 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1184 #ifdef CONFIG_DRM_AMDGPU_SI 1185 //SI DMA has a difference trap irq number for the second engine 1186 struct amdgpu_irq_src trap_irq_1; 1187 #endif 1188 struct amdgpu_irq_src trap_irq; 1189 struct amdgpu_irq_src illegal_inst_irq; 1190 int num_instances; 1191 uint32_t srbm_soft_reset; 1192 }; 1193 1194 /* 1195 * Firmware 1196 */ 1197 enum amdgpu_firmware_load_type { 1198 AMDGPU_FW_LOAD_DIRECT = 0, 1199 AMDGPU_FW_LOAD_SMU, 1200 AMDGPU_FW_LOAD_PSP, 1201 }; 1202 1203 struct amdgpu_firmware { 1204 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1205 enum amdgpu_firmware_load_type load_type; 1206 struct amdgpu_bo *fw_buf; 1207 unsigned int fw_size; 1208 unsigned int max_ucodes; 1209 /* firmwares are loaded by psp instead of smu from vega10 */ 1210 const struct amdgpu_psp_funcs *funcs; 1211 struct amdgpu_bo *rbuf; 1212 struct mutex mutex; 1213 1214 /* gpu info firmware data pointer */ 1215 const struct firmware *gpu_info_fw; 1216 1217 void *fw_buf_ptr; 1218 uint64_t fw_buf_mc; 1219 }; 1220 1221 /* 1222 * Benchmarking 1223 */ 1224 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1225 1226 1227 /* 1228 * Testing 1229 */ 1230 void amdgpu_test_moves(struct amdgpu_device *adev); 1231 1232 /* 1233 * Debugfs 1234 */ 1235 struct amdgpu_debugfs { 1236 const struct drm_info_list *files; 1237 unsigned num_files; 1238 }; 1239 1240 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1241 const struct drm_info_list *files, 1242 unsigned nfiles); 1243 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1244 1245 #if defined(CONFIG_DEBUG_FS) 1246 int amdgpu_debugfs_init(struct drm_minor *minor); 1247 #endif 1248 1249 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1250 1251 /* 1252 * amdgpu smumgr functions 1253 */ 1254 struct amdgpu_smumgr_funcs { 1255 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1256 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1257 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1258 }; 1259 1260 /* 1261 * amdgpu smumgr 1262 */ 1263 struct amdgpu_smumgr { 1264 struct amdgpu_bo *toc_buf; 1265 struct amdgpu_bo *smu_buf; 1266 /* asic priv smu data */ 1267 void *priv; 1268 spinlock_t smu_lock; 1269 /* smumgr functions */ 1270 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1271 /* ucode loading complete flag */ 1272 uint32_t fw_flags; 1273 }; 1274 1275 /* 1276 * ASIC specific register table accessible by UMD 1277 */ 1278 struct amdgpu_allowed_register_entry { 1279 uint32_t reg_offset; 1280 bool grbm_indexed; 1281 }; 1282 1283 /* 1284 * ASIC specific functions. 1285 */ 1286 struct amdgpu_asic_funcs { 1287 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1288 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1289 u8 *bios, u32 length_bytes); 1290 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1291 u32 sh_num, u32 reg_offset, u32 *value); 1292 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1293 int (*reset)(struct amdgpu_device *adev); 1294 /* get the reference clock */ 1295 u32 (*get_xclk)(struct amdgpu_device *adev); 1296 /* MM block clocks */ 1297 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1298 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1299 /* static power management */ 1300 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1301 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1302 /* get config memsize register */ 1303 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1304 }; 1305 1306 /* 1307 * IOCTL. 1308 */ 1309 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1310 struct drm_file *filp); 1311 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1312 struct drm_file *filp); 1313 1314 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1315 struct drm_file *filp); 1316 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1317 struct drm_file *filp); 1318 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1319 struct drm_file *filp); 1320 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1321 struct drm_file *filp); 1322 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1323 struct drm_file *filp); 1324 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1325 struct drm_file *filp); 1326 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1327 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 1328 struct drm_file *filp); 1329 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1330 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1331 struct drm_file *filp); 1332 1333 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1334 struct drm_file *filp); 1335 1336 /* VRAM scratch page for HDP bug, default vram page */ 1337 struct amdgpu_vram_scratch { 1338 struct amdgpu_bo *robj; 1339 volatile uint32_t *ptr; 1340 u64 gpu_addr; 1341 }; 1342 1343 /* 1344 * ACPI 1345 */ 1346 struct amdgpu_atif_notification_cfg { 1347 bool enabled; 1348 int command_code; 1349 }; 1350 1351 struct amdgpu_atif_notifications { 1352 bool display_switch; 1353 bool expansion_mode_change; 1354 bool thermal_state; 1355 bool forced_power_state; 1356 bool system_power_state; 1357 bool display_conf_change; 1358 bool px_gfx_switch; 1359 bool brightness_change; 1360 bool dgpu_display_event; 1361 }; 1362 1363 struct amdgpu_atif_functions { 1364 bool system_params; 1365 bool sbios_requests; 1366 bool select_active_disp; 1367 bool lid_state; 1368 bool get_tv_standard; 1369 bool set_tv_standard; 1370 bool get_panel_expansion_mode; 1371 bool set_panel_expansion_mode; 1372 bool temperature_change; 1373 bool graphics_device_types; 1374 }; 1375 1376 struct amdgpu_atif { 1377 struct amdgpu_atif_notifications notifications; 1378 struct amdgpu_atif_functions functions; 1379 struct amdgpu_atif_notification_cfg notification_cfg; 1380 struct amdgpu_encoder *encoder_for_bl; 1381 }; 1382 1383 struct amdgpu_atcs_functions { 1384 bool get_ext_state; 1385 bool pcie_perf_req; 1386 bool pcie_dev_rdy; 1387 bool pcie_bus_width; 1388 }; 1389 1390 struct amdgpu_atcs { 1391 struct amdgpu_atcs_functions functions; 1392 }; 1393 1394 /* 1395 * Firmware VRAM reservation 1396 */ 1397 struct amdgpu_fw_vram_usage { 1398 u64 start_offset; 1399 u64 size; 1400 struct amdgpu_bo *reserved_bo; 1401 void *va; 1402 }; 1403 1404 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev); 1405 1406 /* 1407 * CGS 1408 */ 1409 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1410 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1411 1412 /* 1413 * Core structure, functions and helpers. 1414 */ 1415 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1416 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1417 1418 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1419 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1420 1421 #define AMDGPU_RESET_MAGIC_NUM 64 1422 struct amdgpu_device { 1423 struct device *dev; 1424 struct drm_device *ddev; 1425 struct pci_dev *pdev; 1426 1427 #ifdef CONFIG_DRM_AMD_ACP 1428 struct amdgpu_acp acp; 1429 #endif 1430 1431 /* ASIC */ 1432 enum amd_asic_type asic_type; 1433 uint32_t family; 1434 uint32_t rev_id; 1435 uint32_t external_rev_id; 1436 unsigned long flags; 1437 int usec_timeout; 1438 const struct amdgpu_asic_funcs *asic_funcs; 1439 bool shutdown; 1440 bool need_dma32; 1441 bool accel_working; 1442 struct work_struct reset_work; 1443 struct notifier_block acpi_nb; 1444 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1445 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1446 unsigned debugfs_count; 1447 #if defined(CONFIG_DEBUG_FS) 1448 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1449 #endif 1450 struct amdgpu_atif atif; 1451 struct amdgpu_atcs atcs; 1452 struct mutex srbm_mutex; 1453 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1454 struct mutex grbm_idx_mutex; 1455 struct dev_pm_domain vga_pm_domain; 1456 bool have_disp_power_ref; 1457 1458 /* BIOS */ 1459 bool is_atom_fw; 1460 uint8_t *bios; 1461 uint32_t bios_size; 1462 struct amdgpu_bo *stolen_vga_memory; 1463 uint32_t bios_scratch_reg_offset; 1464 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1465 1466 /* Register/doorbell mmio */ 1467 resource_size_t rmmio_base; 1468 resource_size_t rmmio_size; 1469 void __iomem *rmmio; 1470 /* protects concurrent MM_INDEX/DATA based register access */ 1471 spinlock_t mmio_idx_lock; 1472 /* protects concurrent SMC based register access */ 1473 spinlock_t smc_idx_lock; 1474 amdgpu_rreg_t smc_rreg; 1475 amdgpu_wreg_t smc_wreg; 1476 /* protects concurrent PCIE register access */ 1477 spinlock_t pcie_idx_lock; 1478 amdgpu_rreg_t pcie_rreg; 1479 amdgpu_wreg_t pcie_wreg; 1480 amdgpu_rreg_t pciep_rreg; 1481 amdgpu_wreg_t pciep_wreg; 1482 /* protects concurrent UVD register access */ 1483 spinlock_t uvd_ctx_idx_lock; 1484 amdgpu_rreg_t uvd_ctx_rreg; 1485 amdgpu_wreg_t uvd_ctx_wreg; 1486 /* protects concurrent DIDT register access */ 1487 spinlock_t didt_idx_lock; 1488 amdgpu_rreg_t didt_rreg; 1489 amdgpu_wreg_t didt_wreg; 1490 /* protects concurrent gc_cac register access */ 1491 spinlock_t gc_cac_idx_lock; 1492 amdgpu_rreg_t gc_cac_rreg; 1493 amdgpu_wreg_t gc_cac_wreg; 1494 /* protects concurrent se_cac register access */ 1495 spinlock_t se_cac_idx_lock; 1496 amdgpu_rreg_t se_cac_rreg; 1497 amdgpu_wreg_t se_cac_wreg; 1498 /* protects concurrent ENDPOINT (audio) register access */ 1499 spinlock_t audio_endpt_idx_lock; 1500 amdgpu_block_rreg_t audio_endpt_rreg; 1501 amdgpu_block_wreg_t audio_endpt_wreg; 1502 void __iomem *rio_mem; 1503 resource_size_t rio_mem_size; 1504 struct amdgpu_doorbell doorbell; 1505 1506 /* clock/pll info */ 1507 struct amdgpu_clock clock; 1508 1509 /* MC */ 1510 struct amdgpu_mc mc; 1511 struct amdgpu_gart gart; 1512 struct amdgpu_dummy_page dummy_page; 1513 struct amdgpu_vm_manager vm_manager; 1514 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1515 1516 /* memory management */ 1517 struct amdgpu_mman mman; 1518 struct amdgpu_vram_scratch vram_scratch; 1519 struct amdgpu_wb wb; 1520 atomic64_t num_bytes_moved; 1521 atomic64_t num_evictions; 1522 atomic64_t num_vram_cpu_page_faults; 1523 atomic_t gpu_reset_counter; 1524 atomic_t vram_lost_counter; 1525 1526 /* data for buffer migration throttling */ 1527 struct { 1528 spinlock_t lock; 1529 s64 last_update_us; 1530 s64 accum_us; /* accumulated microseconds */ 1531 s64 accum_us_vis; /* for visible VRAM */ 1532 u32 log2_max_MBps; 1533 } mm_stats; 1534 1535 /* display */ 1536 bool enable_virtual_display; 1537 struct amdgpu_mode_info mode_info; 1538 struct work_struct hotplug_work; 1539 struct amdgpu_irq_src crtc_irq; 1540 struct amdgpu_irq_src pageflip_irq; 1541 struct amdgpu_irq_src hpd_irq; 1542 1543 /* rings */ 1544 u64 fence_context; 1545 unsigned num_rings; 1546 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1547 bool ib_pool_ready; 1548 struct amdgpu_sa_manager ring_tmp_bo; 1549 1550 /* interrupts */ 1551 struct amdgpu_irq irq; 1552 1553 /* powerplay */ 1554 struct amd_powerplay powerplay; 1555 bool pp_force_state_enabled; 1556 1557 /* dpm */ 1558 struct amdgpu_pm pm; 1559 u32 cg_flags; 1560 u32 pg_flags; 1561 1562 /* amdgpu smumgr */ 1563 struct amdgpu_smumgr smu; 1564 1565 /* gfx */ 1566 struct amdgpu_gfx gfx; 1567 1568 /* sdma */ 1569 struct amdgpu_sdma sdma; 1570 1571 union { 1572 struct { 1573 /* uvd */ 1574 struct amdgpu_uvd uvd; 1575 1576 /* vce */ 1577 struct amdgpu_vce vce; 1578 }; 1579 1580 /* vcn */ 1581 struct amdgpu_vcn vcn; 1582 }; 1583 1584 /* firmwares */ 1585 struct amdgpu_firmware firmware; 1586 1587 /* PSP */ 1588 struct psp_context psp; 1589 1590 /* GDS */ 1591 struct amdgpu_gds gds; 1592 1593 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1594 int num_ip_blocks; 1595 struct mutex mn_lock; 1596 DECLARE_HASHTABLE(mn_hash, 7); 1597 1598 /* tracking pinned memory */ 1599 u64 vram_pin_size; 1600 u64 invisible_pin_size; 1601 u64 gart_pin_size; 1602 1603 /* amdkfd interface */ 1604 struct kfd_dev *kfd; 1605 1606 /* delayed work_func for deferring clockgating during resume */ 1607 struct delayed_work late_init_work; 1608 1609 struct amdgpu_virt virt; 1610 /* firmware VRAM reservation */ 1611 struct amdgpu_fw_vram_usage fw_vram_usage; 1612 1613 /* link all shadow bo */ 1614 struct list_head shadow_list; 1615 struct mutex shadow_list_lock; 1616 /* link all gtt */ 1617 spinlock_t gtt_list_lock; 1618 struct list_head gtt_list; 1619 /* keep an lru list of rings by HW IP */ 1620 struct list_head ring_lru_list; 1621 spinlock_t ring_lru_list_lock; 1622 1623 /* record hw reset is performed */ 1624 bool has_hw_reset; 1625 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1626 1627 /* record last mm index being written through WREG32*/ 1628 unsigned long last_mm_index; 1629 bool in_sriov_reset; 1630 }; 1631 1632 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1633 { 1634 return container_of(bdev, struct amdgpu_device, mman.bdev); 1635 } 1636 1637 int amdgpu_device_init(struct amdgpu_device *adev, 1638 struct drm_device *ddev, 1639 struct pci_dev *pdev, 1640 uint32_t flags); 1641 void amdgpu_device_fini(struct amdgpu_device *adev); 1642 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1643 1644 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1645 uint32_t acc_flags); 1646 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1647 uint32_t acc_flags); 1648 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1649 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1650 1651 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1652 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1653 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1654 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1655 1656 /* 1657 * Registers read & write functions. 1658 */ 1659 1660 #define AMDGPU_REGS_IDX (1<<0) 1661 #define AMDGPU_REGS_NO_KIQ (1<<1) 1662 1663 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1664 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1665 1666 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1667 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1668 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1669 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1670 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1671 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1672 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1673 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1674 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1675 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1676 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1677 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1678 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1679 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1680 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1681 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1682 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1683 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1684 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1685 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1686 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1687 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1688 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1689 #define WREG32_P(reg, val, mask) \ 1690 do { \ 1691 uint32_t tmp_ = RREG32(reg); \ 1692 tmp_ &= (mask); \ 1693 tmp_ |= ((val) & ~(mask)); \ 1694 WREG32(reg, tmp_); \ 1695 } while (0) 1696 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1697 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1698 #define WREG32_PLL_P(reg, val, mask) \ 1699 do { \ 1700 uint32_t tmp_ = RREG32_PLL(reg); \ 1701 tmp_ &= (mask); \ 1702 tmp_ |= ((val) & ~(mask)); \ 1703 WREG32_PLL(reg, tmp_); \ 1704 } while (0) 1705 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1706 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1707 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1708 1709 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1710 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1711 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1712 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1713 1714 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1715 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1716 1717 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1718 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1719 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1720 1721 #define REG_GET_FIELD(value, reg, field) \ 1722 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1723 1724 #define WREG32_FIELD(reg, field, val) \ 1725 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1726 1727 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1728 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1729 1730 /* 1731 * BIOS helpers. 1732 */ 1733 #define RBIOS8(i) (adev->bios[i]) 1734 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1735 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1736 1737 static inline struct amdgpu_sdma_instance * 1738 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1739 { 1740 struct amdgpu_device *adev = ring->adev; 1741 int i; 1742 1743 for (i = 0; i < adev->sdma.num_instances; i++) 1744 if (&adev->sdma.instance[i].ring == ring) 1745 break; 1746 1747 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1748 return &adev->sdma.instance[i]; 1749 else 1750 return NULL; 1751 } 1752 1753 /* 1754 * ASICs macro. 1755 */ 1756 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1757 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1758 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1759 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1760 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1761 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1762 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1763 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1764 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1765 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1766 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1767 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1768 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1769 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1770 #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr)) 1771 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1772 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1773 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1774 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 1775 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1776 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1777 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1778 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1779 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1780 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1781 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1782 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1783 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1784 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1785 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1786 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1787 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1788 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1789 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1790 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1791 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1792 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 1793 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1794 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1795 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1796 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1797 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) 1798 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1799 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1800 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1801 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1802 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1803 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1804 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1805 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1806 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1807 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1808 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1809 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1810 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1811 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1812 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1813 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1814 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1815 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1816 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1817 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1818 1819 /* Common functions */ 1820 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1821 bool amdgpu_need_backup(struct amdgpu_device *adev); 1822 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1823 bool amdgpu_need_post(struct amdgpu_device *adev); 1824 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1825 1826 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1827 u64 num_vis_bytes); 1828 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1829 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1830 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1831 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1832 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1833 int amdgpu_ttm_init(struct amdgpu_device *adev); 1834 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1835 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1836 const u32 *registers, 1837 const u32 array_size); 1838 1839 bool amdgpu_device_is_px(struct drm_device *dev); 1840 /* atpx handler */ 1841 #if defined(CONFIG_VGA_SWITCHEROO) 1842 void amdgpu_register_atpx_handler(void); 1843 void amdgpu_unregister_atpx_handler(void); 1844 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1845 bool amdgpu_is_atpx_hybrid(void); 1846 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1847 bool amdgpu_has_atpx(void); 1848 #else 1849 static inline void amdgpu_register_atpx_handler(void) {} 1850 static inline void amdgpu_unregister_atpx_handler(void) {} 1851 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1852 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1853 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1854 static inline bool amdgpu_has_atpx(void) { return false; } 1855 #endif 1856 1857 /* 1858 * KMS 1859 */ 1860 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1861 extern const int amdgpu_max_kms_ioctl; 1862 1863 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1864 void amdgpu_driver_unload_kms(struct drm_device *dev); 1865 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1866 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1867 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1868 struct drm_file *file_priv); 1869 int amdgpu_suspend(struct amdgpu_device *adev); 1870 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1871 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1872 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1873 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1874 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1875 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1876 unsigned long arg); 1877 1878 /* 1879 * functions used by amdgpu_encoder.c 1880 */ 1881 struct amdgpu_afmt_acr { 1882 u32 clock; 1883 1884 int n_32khz; 1885 int cts_32khz; 1886 1887 int n_44_1khz; 1888 int cts_44_1khz; 1889 1890 int n_48khz; 1891 int cts_48khz; 1892 1893 }; 1894 1895 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1896 1897 /* amdgpu_acpi.c */ 1898 #if defined(CONFIG_ACPI) 1899 int amdgpu_acpi_init(struct amdgpu_device *adev); 1900 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1901 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1902 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1903 u8 perf_req, bool advertise); 1904 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1905 #else 1906 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1907 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1908 #endif 1909 1910 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1911 uint64_t addr, struct amdgpu_bo **bo, 1912 struct amdgpu_bo_va_mapping **mapping); 1913 1914 #include "amdgpu_object.h" 1915 #endif 1916