1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_ras.h" 111 #include "amdgpu_xcp.h" 112 113 #define MAX_GPU_INSTANCE 64 114 115 struct amdgpu_gpu_instance 116 { 117 struct amdgpu_device *adev; 118 int mgpu_fan_enabled; 119 }; 120 121 struct amdgpu_mgpu_info 122 { 123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 124 struct mutex mutex; 125 uint32_t num_gpu; 126 uint32_t num_dgpu; 127 uint32_t num_apu; 128 129 /* delayed reset_func for XGMI configuration if necessary */ 130 struct delayed_work delayed_reset_work; 131 bool pending_reset; 132 }; 133 134 enum amdgpu_ss { 135 AMDGPU_SS_DRV_LOAD, 136 AMDGPU_SS_DEV_D0, 137 AMDGPU_SS_DEV_D3, 138 AMDGPU_SS_DRV_UNLOAD 139 }; 140 141 struct amdgpu_watchdog_timer 142 { 143 bool timeout_fatal_disable; 144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145 }; 146 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 148 149 /* 150 * Modules parameters. 151 */ 152 extern int amdgpu_modeset; 153 extern unsigned int amdgpu_vram_limit; 154 extern int amdgpu_vis_vram_limit; 155 extern int amdgpu_gart_size; 156 extern int amdgpu_gtt_size; 157 extern int amdgpu_moverate; 158 extern int amdgpu_audio; 159 extern int amdgpu_disp_priority; 160 extern int amdgpu_hw_i2c; 161 extern int amdgpu_pcie_gen2; 162 extern int amdgpu_msi; 163 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 164 extern int amdgpu_dpm; 165 extern int amdgpu_fw_load_type; 166 extern int amdgpu_aspm; 167 extern int amdgpu_runtime_pm; 168 extern uint amdgpu_ip_block_mask; 169 extern int amdgpu_bapm; 170 extern int amdgpu_deep_color; 171 extern int amdgpu_vm_size; 172 extern int amdgpu_vm_block_size; 173 extern int amdgpu_vm_fragment_size; 174 extern int amdgpu_vm_fault_stop; 175 extern int amdgpu_vm_debug; 176 extern int amdgpu_vm_update_mode; 177 extern int amdgpu_exp_hw_support; 178 extern int amdgpu_dc; 179 extern int amdgpu_sched_jobs; 180 extern int amdgpu_sched_hw_submission; 181 extern uint amdgpu_pcie_gen_cap; 182 extern uint amdgpu_pcie_lane_cap; 183 extern u64 amdgpu_cg_mask; 184 extern uint amdgpu_pg_mask; 185 extern uint amdgpu_sdma_phase_quantum; 186 extern char *amdgpu_disable_cu; 187 extern char *amdgpu_virtual_display; 188 extern uint amdgpu_pp_feature_mask; 189 extern uint amdgpu_force_long_training; 190 extern int amdgpu_lbpw; 191 extern int amdgpu_compute_multipipe; 192 extern int amdgpu_gpu_recovery; 193 extern int amdgpu_emu_mode; 194 extern uint amdgpu_smu_memory_pool_size; 195 extern int amdgpu_smu_pptable_id; 196 extern uint amdgpu_dc_feature_mask; 197 extern uint amdgpu_dc_debug_mask; 198 extern uint amdgpu_dc_visual_confirm; 199 extern uint amdgpu_dm_abm_level; 200 extern int amdgpu_backlight; 201 extern struct amdgpu_mgpu_info mgpu_info; 202 extern int amdgpu_ras_enable; 203 extern uint amdgpu_ras_mask; 204 extern int amdgpu_bad_page_threshold; 205 extern bool amdgpu_ignore_bad_page_threshold; 206 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 207 extern int amdgpu_async_gfx_ring; 208 extern int amdgpu_mcbp; 209 extern int amdgpu_discovery; 210 extern int amdgpu_mes; 211 extern int amdgpu_mes_kiq; 212 extern int amdgpu_noretry; 213 extern int amdgpu_force_asic_type; 214 extern int amdgpu_smartshift_bias; 215 extern int amdgpu_use_xgmi_p2p; 216 extern int amdgpu_mtype_local; 217 extern bool enforce_isolation; 218 #ifdef CONFIG_HSA_AMD 219 extern int sched_policy; 220 extern bool debug_evictions; 221 extern bool no_system_mem_limit; 222 extern int halt_if_hws_hang; 223 #else 224 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 225 static const bool __maybe_unused debug_evictions; /* = false */ 226 static const bool __maybe_unused no_system_mem_limit; 227 static const int __maybe_unused halt_if_hws_hang; 228 #endif 229 #ifdef CONFIG_HSA_AMD_P2P 230 extern bool pcie_p2p; 231 #endif 232 233 extern int amdgpu_tmz; 234 extern int amdgpu_reset_method; 235 236 #ifdef CONFIG_DRM_AMDGPU_SI 237 extern int amdgpu_si_support; 238 #endif 239 #ifdef CONFIG_DRM_AMDGPU_CIK 240 extern int amdgpu_cik_support; 241 #endif 242 extern int amdgpu_num_kcq; 243 244 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 245 extern int amdgpu_vcnfw_log; 246 extern int amdgpu_sg_display; 247 extern int amdgpu_umsch_mm; 248 extern int amdgpu_seamless; 249 250 extern int amdgpu_user_partt_mode; 251 252 #define AMDGPU_VM_MAX_NUM_CTX 4096 253 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 254 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 255 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 256 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 257 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 258 #define AMDGPUFB_CONN_LIMIT 4 259 #define AMDGPU_BIOS_NUM_SCRATCH 16 260 261 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 262 263 /* hard reset data */ 264 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 265 266 /* reset flags */ 267 #define AMDGPU_RESET_GFX (1 << 0) 268 #define AMDGPU_RESET_COMPUTE (1 << 1) 269 #define AMDGPU_RESET_DMA (1 << 2) 270 #define AMDGPU_RESET_CP (1 << 3) 271 #define AMDGPU_RESET_GRBM (1 << 4) 272 #define AMDGPU_RESET_DMA1 (1 << 5) 273 #define AMDGPU_RESET_RLC (1 << 6) 274 #define AMDGPU_RESET_SEM (1 << 7) 275 #define AMDGPU_RESET_IH (1 << 8) 276 #define AMDGPU_RESET_VMC (1 << 9) 277 #define AMDGPU_RESET_MC (1 << 10) 278 #define AMDGPU_RESET_DISPLAY (1 << 11) 279 #define AMDGPU_RESET_UVD (1 << 12) 280 #define AMDGPU_RESET_VCE (1 << 13) 281 #define AMDGPU_RESET_VCE1 (1 << 14) 282 283 /* max cursor sizes (in pixels) */ 284 #define CIK_CURSOR_WIDTH 128 285 #define CIK_CURSOR_HEIGHT 128 286 287 /* smart shift bias level limits */ 288 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 289 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 290 291 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 292 #define AMDGPU_SWCTF_EXTRA_DELAY 50 293 294 struct amdgpu_xcp_mgr; 295 struct amdgpu_device; 296 struct amdgpu_irq_src; 297 struct amdgpu_fpriv; 298 struct amdgpu_bo_va_mapping; 299 struct kfd_vm_fault_info; 300 struct amdgpu_hive_info; 301 struct amdgpu_reset_context; 302 struct amdgpu_reset_control; 303 304 enum amdgpu_cp_irq { 305 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 306 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 307 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 308 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 310 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 311 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 312 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 313 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 314 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 315 316 AMDGPU_CP_IRQ_LAST 317 }; 318 319 enum amdgpu_thermal_irq { 320 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 321 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 322 323 AMDGPU_THERMAL_IRQ_LAST 324 }; 325 326 enum amdgpu_kiq_irq { 327 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 328 AMDGPU_CP_KIQ_IRQ_LAST 329 }; 330 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 331 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 332 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 333 #define MAX_KIQ_REG_TRY 1000 334 335 int amdgpu_device_ip_set_clockgating_state(void *dev, 336 enum amd_ip_block_type block_type, 337 enum amd_clockgating_state state); 338 int amdgpu_device_ip_set_powergating_state(void *dev, 339 enum amd_ip_block_type block_type, 340 enum amd_powergating_state state); 341 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 342 u64 *flags); 343 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 344 enum amd_ip_block_type block_type); 345 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 346 enum amd_ip_block_type block_type); 347 348 #define AMDGPU_MAX_IP_NUM 16 349 350 struct amdgpu_ip_block_status { 351 bool valid; 352 bool sw; 353 bool hw; 354 bool late_initialized; 355 bool hang; 356 }; 357 358 struct amdgpu_ip_block_version { 359 const enum amd_ip_block_type type; 360 const u32 major; 361 const u32 minor; 362 const u32 rev; 363 const struct amd_ip_funcs *funcs; 364 }; 365 366 #define HW_REV(_Major, _Minor, _Rev) \ 367 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 368 369 struct amdgpu_ip_block { 370 struct amdgpu_ip_block_status status; 371 const struct amdgpu_ip_block_version *version; 372 }; 373 374 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 375 enum amd_ip_block_type type, 376 u32 major, u32 minor); 377 378 struct amdgpu_ip_block * 379 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 380 enum amd_ip_block_type type); 381 382 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 383 const struct amdgpu_ip_block_version *ip_block_version); 384 385 /* 386 * BIOS. 387 */ 388 bool amdgpu_get_bios(struct amdgpu_device *adev); 389 bool amdgpu_read_bios(struct amdgpu_device *adev); 390 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 391 u8 *bios, u32 length_bytes); 392 /* 393 * Clocks 394 */ 395 396 #define AMDGPU_MAX_PPLL 3 397 398 struct amdgpu_clock { 399 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 400 struct amdgpu_pll spll; 401 struct amdgpu_pll mpll; 402 /* 10 Khz units */ 403 uint32_t default_mclk; 404 uint32_t default_sclk; 405 uint32_t default_dispclk; 406 uint32_t current_dispclk; 407 uint32_t dp_extclk; 408 uint32_t max_pixel_clock; 409 }; 410 411 /* sub-allocation manager, it has to be protected by another lock. 412 * By conception this is an helper for other part of the driver 413 * like the indirect buffer or semaphore, which both have their 414 * locking. 415 * 416 * Principe is simple, we keep a list of sub allocation in offset 417 * order (first entry has offset == 0, last entry has the highest 418 * offset). 419 * 420 * When allocating new object we first check if there is room at 421 * the end total_size - (last_object_offset + last_object_size) >= 422 * alloc_size. If so we allocate new object there. 423 * 424 * When there is not enough room at the end, we start waiting for 425 * each sub object until we reach object_offset+object_size >= 426 * alloc_size, this object then become the sub object we return. 427 * 428 * Alignment can't be bigger than page size. 429 * 430 * Hole are not considered for allocation to keep things simple. 431 * Assumption is that there won't be hole (all object on same 432 * alignment). 433 */ 434 435 struct amdgpu_sa_manager { 436 struct drm_suballoc_manager base; 437 struct amdgpu_bo *bo; 438 uint64_t gpu_addr; 439 void *cpu_ptr; 440 }; 441 442 int amdgpu_fence_slab_init(void); 443 void amdgpu_fence_slab_fini(void); 444 445 /* 446 * IRQS. 447 */ 448 449 struct amdgpu_flip_work { 450 struct delayed_work flip_work; 451 struct work_struct unpin_work; 452 struct amdgpu_device *adev; 453 int crtc_id; 454 u32 target_vblank; 455 uint64_t base; 456 struct drm_pending_vblank_event *event; 457 struct amdgpu_bo *old_abo; 458 unsigned shared_count; 459 struct dma_fence **shared; 460 struct dma_fence_cb cb; 461 bool async; 462 }; 463 464 465 /* 466 * file private structure 467 */ 468 469 struct amdgpu_fpriv { 470 struct amdgpu_vm vm; 471 struct amdgpu_bo_va *prt_va; 472 struct amdgpu_bo_va *csa_va; 473 struct mutex bo_list_lock; 474 struct idr bo_list_handles; 475 struct amdgpu_ctx_mgr ctx_mgr; 476 /** GPU partition selection */ 477 uint32_t xcp_id; 478 }; 479 480 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 481 482 /* 483 * Writeback 484 */ 485 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 486 487 struct amdgpu_wb { 488 struct amdgpu_bo *wb_obj; 489 volatile uint32_t *wb; 490 uint64_t gpu_addr; 491 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 492 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 493 }; 494 495 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 496 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 497 498 /* 499 * Benchmarking 500 */ 501 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 502 503 /* 504 * ASIC specific register table accessible by UMD 505 */ 506 struct amdgpu_allowed_register_entry { 507 uint32_t reg_offset; 508 bool grbm_indexed; 509 }; 510 511 enum amd_reset_method { 512 AMD_RESET_METHOD_NONE = -1, 513 AMD_RESET_METHOD_LEGACY = 0, 514 AMD_RESET_METHOD_MODE0, 515 AMD_RESET_METHOD_MODE1, 516 AMD_RESET_METHOD_MODE2, 517 AMD_RESET_METHOD_BACO, 518 AMD_RESET_METHOD_PCI, 519 }; 520 521 struct amdgpu_video_codec_info { 522 u32 codec_type; 523 u32 max_width; 524 u32 max_height; 525 u32 max_pixels_per_frame; 526 u32 max_level; 527 }; 528 529 #define codec_info_build(type, width, height, level) \ 530 .codec_type = type,\ 531 .max_width = width,\ 532 .max_height = height,\ 533 .max_pixels_per_frame = height * width,\ 534 .max_level = level, 535 536 struct amdgpu_video_codecs { 537 const u32 codec_count; 538 const struct amdgpu_video_codec_info *codec_array; 539 }; 540 541 /* 542 * ASIC specific functions. 543 */ 544 struct amdgpu_asic_funcs { 545 bool (*read_disabled_bios)(struct amdgpu_device *adev); 546 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 547 u8 *bios, u32 length_bytes); 548 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 549 u32 sh_num, u32 reg_offset, u32 *value); 550 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 551 int (*reset)(struct amdgpu_device *adev); 552 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 553 /* get the reference clock */ 554 u32 (*get_xclk)(struct amdgpu_device *adev); 555 /* MM block clocks */ 556 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 557 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 558 /* static power management */ 559 int (*get_pcie_lanes)(struct amdgpu_device *adev); 560 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 561 /* get config memsize register */ 562 u32 (*get_config_memsize)(struct amdgpu_device *adev); 563 /* flush hdp write queue */ 564 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 565 /* invalidate hdp read cache */ 566 void (*invalidate_hdp)(struct amdgpu_device *adev, 567 struct amdgpu_ring *ring); 568 /* check if the asic needs a full reset of if soft reset will work */ 569 bool (*need_full_reset)(struct amdgpu_device *adev); 570 /* initialize doorbell layout for specific asic*/ 571 void (*init_doorbell_index)(struct amdgpu_device *adev); 572 /* PCIe bandwidth usage */ 573 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 574 uint64_t *count1); 575 /* do we need to reset the asic at init time (e.g., kexec) */ 576 bool (*need_reset_on_init)(struct amdgpu_device *adev); 577 /* PCIe replay counter */ 578 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 579 /* device supports BACO */ 580 bool (*supports_baco)(struct amdgpu_device *adev); 581 /* pre asic_init quirks */ 582 void (*pre_asic_init)(struct amdgpu_device *adev); 583 /* enter/exit umd stable pstate */ 584 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 585 /* query video codecs */ 586 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 587 const struct amdgpu_video_codecs **codecs); 588 /* encode "> 32bits" smn addressing */ 589 u64 (*encode_ext_smn_addressing)(int ext_id); 590 }; 591 592 /* 593 * IOCTL. 594 */ 595 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 596 struct drm_file *filp); 597 598 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 599 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 600 struct drm_file *filp); 601 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 602 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 603 struct drm_file *filp); 604 605 /* VRAM scratch page for HDP bug, default vram page */ 606 struct amdgpu_mem_scratch { 607 struct amdgpu_bo *robj; 608 volatile uint32_t *ptr; 609 u64 gpu_addr; 610 }; 611 612 /* 613 * CGS 614 */ 615 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 616 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 617 618 /* 619 * Core structure, functions and helpers. 620 */ 621 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 622 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 623 624 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 625 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 626 627 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 628 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 629 630 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 631 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 632 633 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 634 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 635 636 struct amdgpu_mmio_remap { 637 u32 reg_offset; 638 resource_size_t bus_addr; 639 }; 640 641 /* Define the HW IP blocks will be used in driver , add more if necessary */ 642 enum amd_hw_ip_block_type { 643 GC_HWIP = 1, 644 HDP_HWIP, 645 SDMA0_HWIP, 646 SDMA1_HWIP, 647 SDMA2_HWIP, 648 SDMA3_HWIP, 649 SDMA4_HWIP, 650 SDMA5_HWIP, 651 SDMA6_HWIP, 652 SDMA7_HWIP, 653 LSDMA_HWIP, 654 MMHUB_HWIP, 655 ATHUB_HWIP, 656 NBIO_HWIP, 657 MP0_HWIP, 658 MP1_HWIP, 659 UVD_HWIP, 660 VCN_HWIP = UVD_HWIP, 661 JPEG_HWIP = VCN_HWIP, 662 VCN1_HWIP, 663 VCE_HWIP, 664 VPE_HWIP, 665 DF_HWIP, 666 DCE_HWIP, 667 OSSSYS_HWIP, 668 SMUIO_HWIP, 669 PWR_HWIP, 670 NBIF_HWIP, 671 THM_HWIP, 672 CLK_HWIP, 673 UMC_HWIP, 674 RSMU_HWIP, 675 XGMI_HWIP, 676 DCI_HWIP, 677 PCIE_HWIP, 678 MAX_HWIP 679 }; 680 681 #define HWIP_MAX_INSTANCE 44 682 683 #define HW_ID_MAX 300 684 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv)) 685 #define IP_VERSION_MAJ(ver) ((ver) >> 16) 686 #define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF) 687 #define IP_VERSION_REV(ver) ((ver) & 0xFF) 688 689 struct amdgpu_ip_map_info { 690 /* Map of logical to actual dev instances/mask */ 691 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 692 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 693 enum amd_hw_ip_block_type block, 694 int8_t inst); 695 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 696 enum amd_hw_ip_block_type block, 697 uint32_t mask); 698 }; 699 700 struct amd_powerplay { 701 void *pp_handle; 702 const struct amd_pm_funcs *pp_funcs; 703 }; 704 705 struct ip_discovery_top; 706 707 /* polaris10 kickers */ 708 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 709 ((rid == 0xE3) || \ 710 (rid == 0xE4) || \ 711 (rid == 0xE5) || \ 712 (rid == 0xE7) || \ 713 (rid == 0xEF))) || \ 714 ((did == 0x6FDF) && \ 715 ((rid == 0xE7) || \ 716 (rid == 0xEF) || \ 717 (rid == 0xFF)))) 718 719 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 720 ((rid == 0xE1) || \ 721 (rid == 0xF7))) 722 723 /* polaris11 kickers */ 724 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 725 ((rid == 0xE0) || \ 726 (rid == 0xE5))) || \ 727 ((did == 0x67FF) && \ 728 ((rid == 0xCF) || \ 729 (rid == 0xEF) || \ 730 (rid == 0xFF)))) 731 732 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 733 ((rid == 0xE2))) 734 735 /* polaris12 kickers */ 736 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 737 ((rid == 0xC0) || \ 738 (rid == 0xC1) || \ 739 (rid == 0xC3) || \ 740 (rid == 0xC7))) || \ 741 ((did == 0x6981) && \ 742 ((rid == 0x00) || \ 743 (rid == 0x01) || \ 744 (rid == 0x10)))) 745 746 struct amdgpu_mqd_prop { 747 uint64_t mqd_gpu_addr; 748 uint64_t hqd_base_gpu_addr; 749 uint64_t rptr_gpu_addr; 750 uint64_t wptr_gpu_addr; 751 uint32_t queue_size; 752 bool use_doorbell; 753 uint32_t doorbell_index; 754 uint64_t eop_gpu_addr; 755 uint32_t hqd_pipe_priority; 756 uint32_t hqd_queue_priority; 757 bool hqd_active; 758 }; 759 760 struct amdgpu_mqd { 761 unsigned mqd_size; 762 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 763 struct amdgpu_mqd_prop *p); 764 }; 765 766 #define AMDGPU_RESET_MAGIC_NUM 64 767 #define AMDGPU_MAX_DF_PERFMONS 4 768 #define AMDGPU_PRODUCT_NAME_LEN 64 769 struct amdgpu_reset_domain; 770 771 /* 772 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 773 */ 774 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 775 776 struct amdgpu_device { 777 struct device *dev; 778 struct pci_dev *pdev; 779 struct drm_device ddev; 780 781 #ifdef CONFIG_DRM_AMD_ACP 782 struct amdgpu_acp acp; 783 #endif 784 struct amdgpu_hive_info *hive; 785 struct amdgpu_xcp_mgr *xcp_mgr; 786 /* ASIC */ 787 enum amd_asic_type asic_type; 788 uint32_t family; 789 uint32_t rev_id; 790 uint32_t external_rev_id; 791 unsigned long flags; 792 unsigned long apu_flags; 793 int usec_timeout; 794 const struct amdgpu_asic_funcs *asic_funcs; 795 bool shutdown; 796 bool need_swiotlb; 797 bool accel_working; 798 struct notifier_block acpi_nb; 799 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 800 struct debugfs_blob_wrapper debugfs_vbios_blob; 801 struct debugfs_blob_wrapper debugfs_discovery_blob; 802 struct mutex srbm_mutex; 803 /* GRBM index mutex. Protects concurrent access to GRBM index */ 804 struct mutex grbm_idx_mutex; 805 struct dev_pm_domain vga_pm_domain; 806 bool have_disp_power_ref; 807 bool have_atomics_support; 808 809 /* BIOS */ 810 bool is_atom_fw; 811 uint8_t *bios; 812 uint32_t bios_size; 813 uint32_t bios_scratch_reg_offset; 814 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 815 816 /* Register/doorbell mmio */ 817 resource_size_t rmmio_base; 818 resource_size_t rmmio_size; 819 void __iomem *rmmio; 820 /* protects concurrent MM_INDEX/DATA based register access */ 821 spinlock_t mmio_idx_lock; 822 struct amdgpu_mmio_remap rmmio_remap; 823 /* protects concurrent SMC based register access */ 824 spinlock_t smc_idx_lock; 825 amdgpu_rreg_t smc_rreg; 826 amdgpu_wreg_t smc_wreg; 827 /* protects concurrent PCIE register access */ 828 spinlock_t pcie_idx_lock; 829 amdgpu_rreg_t pcie_rreg; 830 amdgpu_wreg_t pcie_wreg; 831 amdgpu_rreg_t pciep_rreg; 832 amdgpu_wreg_t pciep_wreg; 833 amdgpu_rreg_ext_t pcie_rreg_ext; 834 amdgpu_wreg_ext_t pcie_wreg_ext; 835 amdgpu_rreg64_t pcie_rreg64; 836 amdgpu_wreg64_t pcie_wreg64; 837 amdgpu_rreg64_ext_t pcie_rreg64_ext; 838 amdgpu_wreg64_ext_t pcie_wreg64_ext; 839 /* protects concurrent UVD register access */ 840 spinlock_t uvd_ctx_idx_lock; 841 amdgpu_rreg_t uvd_ctx_rreg; 842 amdgpu_wreg_t uvd_ctx_wreg; 843 /* protects concurrent DIDT register access */ 844 spinlock_t didt_idx_lock; 845 amdgpu_rreg_t didt_rreg; 846 amdgpu_wreg_t didt_wreg; 847 /* protects concurrent gc_cac register access */ 848 spinlock_t gc_cac_idx_lock; 849 amdgpu_rreg_t gc_cac_rreg; 850 amdgpu_wreg_t gc_cac_wreg; 851 /* protects concurrent se_cac register access */ 852 spinlock_t se_cac_idx_lock; 853 amdgpu_rreg_t se_cac_rreg; 854 amdgpu_wreg_t se_cac_wreg; 855 /* protects concurrent ENDPOINT (audio) register access */ 856 spinlock_t audio_endpt_idx_lock; 857 amdgpu_block_rreg_t audio_endpt_rreg; 858 amdgpu_block_wreg_t audio_endpt_wreg; 859 struct amdgpu_doorbell doorbell; 860 861 /* clock/pll info */ 862 struct amdgpu_clock clock; 863 864 /* MC */ 865 struct amdgpu_gmc gmc; 866 struct amdgpu_gart gart; 867 dma_addr_t dummy_page_addr; 868 struct amdgpu_vm_manager vm_manager; 869 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 870 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 871 872 /* memory management */ 873 struct amdgpu_mman mman; 874 struct amdgpu_mem_scratch mem_scratch; 875 struct amdgpu_wb wb; 876 atomic64_t num_bytes_moved; 877 atomic64_t num_evictions; 878 atomic64_t num_vram_cpu_page_faults; 879 atomic_t gpu_reset_counter; 880 atomic_t vram_lost_counter; 881 882 /* data for buffer migration throttling */ 883 struct { 884 spinlock_t lock; 885 s64 last_update_us; 886 s64 accum_us; /* accumulated microseconds */ 887 s64 accum_us_vis; /* for visible VRAM */ 888 u32 log2_max_MBps; 889 } mm_stats; 890 891 /* display */ 892 bool enable_virtual_display; 893 struct amdgpu_vkms_output *amdgpu_vkms_output; 894 struct amdgpu_mode_info mode_info; 895 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 896 struct delayed_work hotplug_work; 897 struct amdgpu_irq_src crtc_irq; 898 struct amdgpu_irq_src vline0_irq; 899 struct amdgpu_irq_src vupdate_irq; 900 struct amdgpu_irq_src pageflip_irq; 901 struct amdgpu_irq_src hpd_irq; 902 struct amdgpu_irq_src dmub_trace_irq; 903 struct amdgpu_irq_src dmub_outbox_irq; 904 905 /* rings */ 906 u64 fence_context; 907 unsigned num_rings; 908 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 909 struct dma_fence __rcu *gang_submit; 910 bool ib_pool_ready; 911 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 912 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 913 914 /* interrupts */ 915 struct amdgpu_irq irq; 916 917 /* powerplay */ 918 struct amd_powerplay powerplay; 919 struct amdgpu_pm pm; 920 u64 cg_flags; 921 u32 pg_flags; 922 923 /* nbio */ 924 struct amdgpu_nbio nbio; 925 926 /* hdp */ 927 struct amdgpu_hdp hdp; 928 929 /* smuio */ 930 struct amdgpu_smuio smuio; 931 932 /* mmhub */ 933 struct amdgpu_mmhub mmhub; 934 935 /* gfxhub */ 936 struct amdgpu_gfxhub gfxhub; 937 938 /* gfx */ 939 struct amdgpu_gfx gfx; 940 941 /* sdma */ 942 struct amdgpu_sdma sdma; 943 944 /* lsdma */ 945 struct amdgpu_lsdma lsdma; 946 947 /* uvd */ 948 struct amdgpu_uvd uvd; 949 950 /* vce */ 951 struct amdgpu_vce vce; 952 953 /* vcn */ 954 struct amdgpu_vcn vcn; 955 956 /* jpeg */ 957 struct amdgpu_jpeg jpeg; 958 959 /* vpe */ 960 struct amdgpu_vpe vpe; 961 962 /* umsch */ 963 struct amdgpu_umsch_mm umsch_mm; 964 bool enable_umsch_mm; 965 966 /* firmwares */ 967 struct amdgpu_firmware firmware; 968 969 /* PSP */ 970 struct psp_context psp; 971 972 /* GDS */ 973 struct amdgpu_gds gds; 974 975 /* KFD */ 976 struct amdgpu_kfd_dev kfd; 977 978 /* UMC */ 979 struct amdgpu_umc umc; 980 981 /* display related functionality */ 982 struct amdgpu_display_manager dm; 983 984 /* mes */ 985 bool enable_mes; 986 bool enable_mes_kiq; 987 struct amdgpu_mes mes; 988 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 989 990 /* df */ 991 struct amdgpu_df df; 992 993 /* MCA */ 994 struct amdgpu_mca mca; 995 996 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 997 uint32_t harvest_ip_mask; 998 int num_ip_blocks; 999 struct mutex mn_lock; 1000 DECLARE_HASHTABLE(mn_hash, 7); 1001 1002 /* tracking pinned memory */ 1003 atomic64_t vram_pin_size; 1004 atomic64_t visible_pin_size; 1005 atomic64_t gart_pin_size; 1006 1007 /* soc15 register offset based on ip, instance and segment */ 1008 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1009 struct amdgpu_ip_map_info ip_map; 1010 1011 /* delayed work_func for deferring clockgating during resume */ 1012 struct delayed_work delayed_init_work; 1013 1014 struct amdgpu_virt virt; 1015 1016 /* link all shadow bo */ 1017 struct list_head shadow_list; 1018 struct mutex shadow_list_lock; 1019 1020 /* record hw reset is performed */ 1021 bool has_hw_reset; 1022 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1023 1024 /* s3/s4 mask */ 1025 bool in_suspend; 1026 bool in_s3; 1027 bool in_s4; 1028 bool in_s0ix; 1029 1030 enum pp_mp1_state mp1_state; 1031 struct amdgpu_doorbell_index doorbell_index; 1032 1033 struct mutex notifier_lock; 1034 1035 int asic_reset_res; 1036 struct work_struct xgmi_reset_work; 1037 struct list_head reset_list; 1038 1039 long gfx_timeout; 1040 long sdma_timeout; 1041 long video_timeout; 1042 long compute_timeout; 1043 1044 uint64_t unique_id; 1045 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1046 1047 /* enable runtime pm on the device */ 1048 bool in_runpm; 1049 bool has_pr3; 1050 1051 bool ucode_sysfs_en; 1052 1053 /* Chip product information */ 1054 char product_number[20]; 1055 char product_name[AMDGPU_PRODUCT_NAME_LEN]; 1056 char serial[20]; 1057 1058 atomic_t throttling_logging_enabled; 1059 struct ratelimit_state throttling_logging_rs; 1060 uint32_t ras_hw_enabled; 1061 uint32_t ras_enabled; 1062 1063 bool no_hw_access; 1064 struct pci_saved_state *pci_state; 1065 pci_channel_state_t pci_channel_state; 1066 1067 /* Track auto wait count on s_barrier settings */ 1068 bool barrier_has_auto_waitcnt; 1069 1070 struct amdgpu_reset_control *reset_cntl; 1071 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1072 1073 bool ram_is_direct_mapped; 1074 1075 struct list_head ras_list; 1076 1077 struct ip_discovery_top *ip_top; 1078 1079 struct amdgpu_reset_domain *reset_domain; 1080 1081 struct mutex benchmark_mutex; 1082 1083 /* reset dump register */ 1084 uint32_t *reset_dump_reg_list; 1085 uint32_t *reset_dump_reg_value; 1086 int num_regs; 1087 #ifdef CONFIG_DEV_COREDUMP 1088 struct amdgpu_task_info reset_task_info; 1089 bool reset_vram_lost; 1090 struct timespec64 reset_time; 1091 #endif 1092 1093 bool scpm_enabled; 1094 uint32_t scpm_status; 1095 1096 struct work_struct reset_work; 1097 1098 bool job_hang; 1099 bool dc_enabled; 1100 /* Mask of active clusters */ 1101 uint32_t aid_mask; 1102 1103 /* Debug */ 1104 bool debug_vm; 1105 bool debug_largebar; 1106 bool debug_disable_soft_recovery; 1107 }; 1108 1109 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1110 uint8_t ip, uint8_t inst) 1111 { 1112 return adev->ip_versions[ip][inst]; 1113 } 1114 1115 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1116 { 1117 return container_of(ddev, struct amdgpu_device, ddev); 1118 } 1119 1120 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1121 { 1122 return &adev->ddev; 1123 } 1124 1125 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1126 { 1127 return container_of(bdev, struct amdgpu_device, mman.bdev); 1128 } 1129 1130 int amdgpu_device_init(struct amdgpu_device *adev, 1131 uint32_t flags); 1132 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1133 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1134 1135 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1136 1137 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1138 void *buf, size_t size, bool write); 1139 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1140 void *buf, size_t size, bool write); 1141 1142 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1143 void *buf, size_t size, bool write); 1144 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1145 uint32_t inst, uint32_t reg_addr, char reg_name[], 1146 uint32_t expected_value, uint32_t mask); 1147 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1148 uint32_t reg, uint32_t acc_flags); 1149 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1150 u64 reg_addr); 1151 void amdgpu_device_wreg(struct amdgpu_device *adev, 1152 uint32_t reg, uint32_t v, 1153 uint32_t acc_flags); 1154 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1155 u64 reg_addr, u32 reg_data); 1156 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1157 uint32_t reg, uint32_t v, uint32_t xcc_id); 1158 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1159 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1160 1161 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1162 u32 reg_addr); 1163 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1164 u32 reg_addr); 1165 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1166 u64 reg_addr); 1167 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1168 u32 reg_addr, u32 reg_data); 1169 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1170 u32 reg_addr, u64 reg_data); 1171 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1172 u64 reg_addr, u64 reg_data); 1173 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1174 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1175 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1176 1177 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1178 1179 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1180 struct amdgpu_reset_context *reset_context); 1181 1182 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1183 struct amdgpu_reset_context *reset_context); 1184 1185 int emu_soc_asic_init(struct amdgpu_device *adev); 1186 1187 /* 1188 * Registers read & write functions. 1189 */ 1190 #define AMDGPU_REGS_NO_KIQ (1<<1) 1191 #define AMDGPU_REGS_RLC (1<<2) 1192 1193 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1194 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1195 1196 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1197 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1198 1199 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1200 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1201 1202 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1203 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1204 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1205 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1206 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1207 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1208 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1209 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1210 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1211 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1212 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1213 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1214 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1215 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1216 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1217 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1218 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1219 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1220 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1221 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1222 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1223 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1224 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1225 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1226 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1227 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1228 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1229 #define WREG32_P(reg, val, mask) \ 1230 do { \ 1231 uint32_t tmp_ = RREG32(reg); \ 1232 tmp_ &= (mask); \ 1233 tmp_ |= ((val) & ~(mask)); \ 1234 WREG32(reg, tmp_); \ 1235 } while (0) 1236 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1237 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1238 #define WREG32_PLL_P(reg, val, mask) \ 1239 do { \ 1240 uint32_t tmp_ = RREG32_PLL(reg); \ 1241 tmp_ &= (mask); \ 1242 tmp_ |= ((val) & ~(mask)); \ 1243 WREG32_PLL(reg, tmp_); \ 1244 } while (0) 1245 1246 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1247 do { \ 1248 u32 tmp = RREG32_SMC(_Reg); \ 1249 tmp &= (_Mask); \ 1250 tmp |= ((_Val) & ~(_Mask)); \ 1251 WREG32_SMC(_Reg, tmp); \ 1252 } while (0) 1253 1254 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1255 1256 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1257 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1258 1259 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1260 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1261 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1262 1263 #define REG_GET_FIELD(value, reg, field) \ 1264 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1265 1266 #define WREG32_FIELD(reg, field, val) \ 1267 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1268 1269 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1270 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1271 1272 /* 1273 * BIOS helpers. 1274 */ 1275 #define RBIOS8(i) (adev->bios[i]) 1276 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1277 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1278 1279 /* 1280 * ASICs macro. 1281 */ 1282 #define amdgpu_asic_set_vga_state(adev, state) \ 1283 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1284 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1285 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1286 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1287 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1288 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1289 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1290 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1291 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1292 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1293 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1294 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1295 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1296 #define amdgpu_asic_flush_hdp(adev, r) \ 1297 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1298 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1299 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1300 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1301 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1302 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1303 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1304 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1305 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1306 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1307 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1308 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1309 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1310 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1311 1312 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1313 1314 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1315 #define for_each_inst(i, inst_mask) \ 1316 for (i = ffs(inst_mask); i-- != 0; \ 1317 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1318 1319 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1320 1321 /* Common functions */ 1322 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1323 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1324 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1325 struct amdgpu_job *job, 1326 struct amdgpu_reset_context *reset_context); 1327 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1328 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1329 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1330 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1331 bool amdgpu_device_pcie_dynamic_switching_supported(void); 1332 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1333 bool amdgpu_device_aspm_support_quirk(void); 1334 1335 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1336 u64 num_vis_bytes); 1337 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1338 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1339 const u32 *registers, 1340 const u32 array_size); 1341 1342 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1343 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1344 bool amdgpu_device_supports_px(struct drm_device *dev); 1345 bool amdgpu_device_supports_boco(struct drm_device *dev); 1346 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1347 bool amdgpu_device_supports_baco(struct drm_device *dev); 1348 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1349 struct amdgpu_device *peer_adev); 1350 int amdgpu_device_baco_enter(struct drm_device *dev); 1351 int amdgpu_device_baco_exit(struct drm_device *dev); 1352 1353 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1354 struct amdgpu_ring *ring); 1355 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1356 struct amdgpu_ring *ring); 1357 1358 void amdgpu_device_halt(struct amdgpu_device *adev); 1359 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1360 u32 reg); 1361 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1362 u32 reg, u32 v); 1363 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1364 struct dma_fence *gang); 1365 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1366 1367 /* atpx handler */ 1368 #if defined(CONFIG_VGA_SWITCHEROO) 1369 void amdgpu_register_atpx_handler(void); 1370 void amdgpu_unregister_atpx_handler(void); 1371 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1372 bool amdgpu_is_atpx_hybrid(void); 1373 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1374 bool amdgpu_has_atpx(void); 1375 #else 1376 static inline void amdgpu_register_atpx_handler(void) {} 1377 static inline void amdgpu_unregister_atpx_handler(void) {} 1378 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1379 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1380 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1381 static inline bool amdgpu_has_atpx(void) { return false; } 1382 #endif 1383 1384 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1385 void *amdgpu_atpx_get_dhandle(void); 1386 #else 1387 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1388 #endif 1389 1390 /* 1391 * KMS 1392 */ 1393 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1394 extern const int amdgpu_max_kms_ioctl; 1395 1396 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1397 void amdgpu_driver_unload_kms(struct drm_device *dev); 1398 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1399 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1400 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1401 struct drm_file *file_priv); 1402 void amdgpu_driver_release_kms(struct drm_device *dev); 1403 1404 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1405 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1406 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1407 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1408 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1409 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1410 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1411 struct drm_file *filp); 1412 1413 /* 1414 * functions used by amdgpu_encoder.c 1415 */ 1416 struct amdgpu_afmt_acr { 1417 u32 clock; 1418 1419 int n_32khz; 1420 int cts_32khz; 1421 1422 int n_44_1khz; 1423 int cts_44_1khz; 1424 1425 int n_48khz; 1426 int cts_48khz; 1427 1428 }; 1429 1430 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1431 1432 /* amdgpu_acpi.c */ 1433 1434 struct amdgpu_numa_info { 1435 uint64_t size; 1436 int pxm; 1437 int nid; 1438 }; 1439 1440 /* ATCS Device/Driver State */ 1441 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1442 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1443 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1444 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1445 1446 #if defined(CONFIG_ACPI) 1447 int amdgpu_acpi_init(struct amdgpu_device *adev); 1448 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1449 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1450 bool amdgpu_acpi_is_power_shift_control_supported(void); 1451 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1452 u8 perf_req, bool advertise); 1453 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1454 u8 dev_state, bool drv_state); 1455 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1456 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1457 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1458 u64 *tmr_size); 1459 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1460 struct amdgpu_numa_info *numa_info); 1461 1462 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1463 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1464 void amdgpu_acpi_detect(void); 1465 void amdgpu_acpi_release(void); 1466 #else 1467 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1468 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1469 u64 *tmr_offset, u64 *tmr_size) 1470 { 1471 return -EINVAL; 1472 } 1473 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1474 int xcc_id, 1475 struct amdgpu_numa_info *numa_info) 1476 { 1477 return -EINVAL; 1478 } 1479 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1480 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1481 static inline void amdgpu_acpi_detect(void) { } 1482 static inline void amdgpu_acpi_release(void) { } 1483 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1484 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1485 u8 dev_state, bool drv_state) { return 0; } 1486 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1487 enum amdgpu_ss ss_state) { return 0; } 1488 #endif 1489 1490 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1491 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1492 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1493 #else 1494 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1495 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1496 #endif 1497 1498 #if defined(CONFIG_DRM_AMD_DC) 1499 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1500 #else 1501 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1502 #endif 1503 1504 1505 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1506 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1507 1508 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1509 pci_channel_state_t state); 1510 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1511 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1512 void amdgpu_pci_resume(struct pci_dev *pdev); 1513 1514 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1515 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1516 1517 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1518 1519 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1520 enum amd_clockgating_state state); 1521 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1522 enum amd_powergating_state state); 1523 1524 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1525 { 1526 return amdgpu_gpu_recovery != 0 && 1527 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1528 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1529 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1530 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1531 } 1532 1533 #include "amdgpu_object.h" 1534 1535 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1536 { 1537 return adev->gmc.tmz_enabled; 1538 } 1539 1540 int amdgpu_in_reset(struct amdgpu_device *adev); 1541 1542 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1543 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1544 extern const struct attribute_group amdgpu_flash_attr_group; 1545 1546 #endif 1547