1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_ras.h" 111 #include "amdgpu_xcp.h" 112 #include "amdgpu_seq64.h" 113 114 #define MAX_GPU_INSTANCE 64 115 116 struct amdgpu_gpu_instance 117 { 118 struct amdgpu_device *adev; 119 int mgpu_fan_enabled; 120 }; 121 122 struct amdgpu_mgpu_info 123 { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct mutex mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 130 /* delayed reset_func for XGMI configuration if necessary */ 131 struct delayed_work delayed_reset_work; 132 bool pending_reset; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_watchdog_timer 143 { 144 bool timeout_fatal_disable; 145 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 146 }; 147 148 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 149 150 /* 151 * Modules parameters. 152 */ 153 extern int amdgpu_modeset; 154 extern unsigned int amdgpu_vram_limit; 155 extern int amdgpu_vis_vram_limit; 156 extern int amdgpu_gart_size; 157 extern int amdgpu_gtt_size; 158 extern int amdgpu_moverate; 159 extern int amdgpu_audio; 160 extern int amdgpu_disp_priority; 161 extern int amdgpu_hw_i2c; 162 extern int amdgpu_pcie_gen2; 163 extern int amdgpu_msi; 164 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 165 extern int amdgpu_dpm; 166 extern int amdgpu_fw_load_type; 167 extern int amdgpu_aspm; 168 extern int amdgpu_runtime_pm; 169 extern uint amdgpu_ip_block_mask; 170 extern int amdgpu_bapm; 171 extern int amdgpu_deep_color; 172 extern int amdgpu_vm_size; 173 extern int amdgpu_vm_block_size; 174 extern int amdgpu_vm_fragment_size; 175 extern int amdgpu_vm_fault_stop; 176 extern int amdgpu_vm_debug; 177 extern int amdgpu_vm_update_mode; 178 extern int amdgpu_exp_hw_support; 179 extern int amdgpu_dc; 180 extern int amdgpu_sched_jobs; 181 extern int amdgpu_sched_hw_submission; 182 extern uint amdgpu_pcie_gen_cap; 183 extern uint amdgpu_pcie_lane_cap; 184 extern u64 amdgpu_cg_mask; 185 extern uint amdgpu_pg_mask; 186 extern uint amdgpu_sdma_phase_quantum; 187 extern char *amdgpu_disable_cu; 188 extern char *amdgpu_virtual_display; 189 extern uint amdgpu_pp_feature_mask; 190 extern uint amdgpu_force_long_training; 191 extern int amdgpu_lbpw; 192 extern int amdgpu_compute_multipipe; 193 extern int amdgpu_gpu_recovery; 194 extern int amdgpu_emu_mode; 195 extern uint amdgpu_smu_memory_pool_size; 196 extern int amdgpu_smu_pptable_id; 197 extern uint amdgpu_dc_feature_mask; 198 extern uint amdgpu_dc_debug_mask; 199 extern uint amdgpu_dc_visual_confirm; 200 extern uint amdgpu_dm_abm_level; 201 extern int amdgpu_backlight; 202 extern struct amdgpu_mgpu_info mgpu_info; 203 extern int amdgpu_ras_enable; 204 extern uint amdgpu_ras_mask; 205 extern int amdgpu_bad_page_threshold; 206 extern bool amdgpu_ignore_bad_page_threshold; 207 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 208 extern int amdgpu_async_gfx_ring; 209 extern int amdgpu_mcbp; 210 extern int amdgpu_discovery; 211 extern int amdgpu_mes; 212 extern int amdgpu_mes_kiq; 213 extern int amdgpu_noretry; 214 extern int amdgpu_force_asic_type; 215 extern int amdgpu_smartshift_bias; 216 extern int amdgpu_use_xgmi_p2p; 217 extern int amdgpu_mtype_local; 218 extern bool enforce_isolation; 219 #ifdef CONFIG_HSA_AMD 220 extern int sched_policy; 221 extern bool debug_evictions; 222 extern bool no_system_mem_limit; 223 extern int halt_if_hws_hang; 224 #else 225 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 226 static const bool __maybe_unused debug_evictions; /* = false */ 227 static const bool __maybe_unused no_system_mem_limit; 228 static const int __maybe_unused halt_if_hws_hang; 229 #endif 230 #ifdef CONFIG_HSA_AMD_P2P 231 extern bool pcie_p2p; 232 #endif 233 234 extern int amdgpu_tmz; 235 extern int amdgpu_reset_method; 236 237 #ifdef CONFIG_DRM_AMDGPU_SI 238 extern int amdgpu_si_support; 239 #endif 240 #ifdef CONFIG_DRM_AMDGPU_CIK 241 extern int amdgpu_cik_support; 242 #endif 243 extern int amdgpu_num_kcq; 244 245 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 246 extern int amdgpu_vcnfw_log; 247 extern int amdgpu_sg_display; 248 extern int amdgpu_umsch_mm; 249 extern int amdgpu_seamless; 250 251 extern int amdgpu_user_partt_mode; 252 extern int amdgpu_agp; 253 254 #define AMDGPU_VM_MAX_NUM_CTX 4096 255 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 256 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 257 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 258 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 259 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 260 #define AMDGPUFB_CONN_LIMIT 4 261 #define AMDGPU_BIOS_NUM_SCRATCH 16 262 263 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 264 265 /* hard reset data */ 266 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 267 268 /* reset flags */ 269 #define AMDGPU_RESET_GFX (1 << 0) 270 #define AMDGPU_RESET_COMPUTE (1 << 1) 271 #define AMDGPU_RESET_DMA (1 << 2) 272 #define AMDGPU_RESET_CP (1 << 3) 273 #define AMDGPU_RESET_GRBM (1 << 4) 274 #define AMDGPU_RESET_DMA1 (1 << 5) 275 #define AMDGPU_RESET_RLC (1 << 6) 276 #define AMDGPU_RESET_SEM (1 << 7) 277 #define AMDGPU_RESET_IH (1 << 8) 278 #define AMDGPU_RESET_VMC (1 << 9) 279 #define AMDGPU_RESET_MC (1 << 10) 280 #define AMDGPU_RESET_DISPLAY (1 << 11) 281 #define AMDGPU_RESET_UVD (1 << 12) 282 #define AMDGPU_RESET_VCE (1 << 13) 283 #define AMDGPU_RESET_VCE1 (1 << 14) 284 285 /* max cursor sizes (in pixels) */ 286 #define CIK_CURSOR_WIDTH 128 287 #define CIK_CURSOR_HEIGHT 128 288 289 /* smart shift bias level limits */ 290 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 291 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 292 293 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 294 #define AMDGPU_SWCTF_EXTRA_DELAY 50 295 296 struct amdgpu_xcp_mgr; 297 struct amdgpu_device; 298 struct amdgpu_irq_src; 299 struct amdgpu_fpriv; 300 struct amdgpu_bo_va_mapping; 301 struct kfd_vm_fault_info; 302 struct amdgpu_hive_info; 303 struct amdgpu_reset_context; 304 struct amdgpu_reset_control; 305 306 enum amdgpu_cp_irq { 307 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 308 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 309 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 310 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 311 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 312 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 313 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 314 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 315 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 316 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 317 318 AMDGPU_CP_IRQ_LAST 319 }; 320 321 enum amdgpu_thermal_irq { 322 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 323 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 324 325 AMDGPU_THERMAL_IRQ_LAST 326 }; 327 328 enum amdgpu_kiq_irq { 329 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 330 AMDGPU_CP_KIQ_IRQ_LAST 331 }; 332 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 333 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 334 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 335 #define MAX_KIQ_REG_TRY 1000 336 337 int amdgpu_device_ip_set_clockgating_state(void *dev, 338 enum amd_ip_block_type block_type, 339 enum amd_clockgating_state state); 340 int amdgpu_device_ip_set_powergating_state(void *dev, 341 enum amd_ip_block_type block_type, 342 enum amd_powergating_state state); 343 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 344 u64 *flags); 345 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 346 enum amd_ip_block_type block_type); 347 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 348 enum amd_ip_block_type block_type); 349 350 #define AMDGPU_MAX_IP_NUM 16 351 352 struct amdgpu_ip_block_status { 353 bool valid; 354 bool sw; 355 bool hw; 356 bool late_initialized; 357 bool hang; 358 }; 359 360 struct amdgpu_ip_block_version { 361 const enum amd_ip_block_type type; 362 const u32 major; 363 const u32 minor; 364 const u32 rev; 365 const struct amd_ip_funcs *funcs; 366 }; 367 368 struct amdgpu_ip_block { 369 struct amdgpu_ip_block_status status; 370 const struct amdgpu_ip_block_version *version; 371 }; 372 373 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 374 enum amd_ip_block_type type, 375 u32 major, u32 minor); 376 377 struct amdgpu_ip_block * 378 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 379 enum amd_ip_block_type type); 380 381 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 382 const struct amdgpu_ip_block_version *ip_block_version); 383 384 /* 385 * BIOS. 386 */ 387 bool amdgpu_get_bios(struct amdgpu_device *adev); 388 bool amdgpu_read_bios(struct amdgpu_device *adev); 389 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 390 u8 *bios, u32 length_bytes); 391 /* 392 * Clocks 393 */ 394 395 #define AMDGPU_MAX_PPLL 3 396 397 struct amdgpu_clock { 398 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 399 struct amdgpu_pll spll; 400 struct amdgpu_pll mpll; 401 /* 10 Khz units */ 402 uint32_t default_mclk; 403 uint32_t default_sclk; 404 uint32_t default_dispclk; 405 uint32_t current_dispclk; 406 uint32_t dp_extclk; 407 uint32_t max_pixel_clock; 408 }; 409 410 /* sub-allocation manager, it has to be protected by another lock. 411 * By conception this is an helper for other part of the driver 412 * like the indirect buffer or semaphore, which both have their 413 * locking. 414 * 415 * Principe is simple, we keep a list of sub allocation in offset 416 * order (first entry has offset == 0, last entry has the highest 417 * offset). 418 * 419 * When allocating new object we first check if there is room at 420 * the end total_size - (last_object_offset + last_object_size) >= 421 * alloc_size. If so we allocate new object there. 422 * 423 * When there is not enough room at the end, we start waiting for 424 * each sub object until we reach object_offset+object_size >= 425 * alloc_size, this object then become the sub object we return. 426 * 427 * Alignment can't be bigger than page size. 428 * 429 * Hole are not considered for allocation to keep things simple. 430 * Assumption is that there won't be hole (all object on same 431 * alignment). 432 */ 433 434 struct amdgpu_sa_manager { 435 struct drm_suballoc_manager base; 436 struct amdgpu_bo *bo; 437 uint64_t gpu_addr; 438 void *cpu_ptr; 439 }; 440 441 int amdgpu_fence_slab_init(void); 442 void amdgpu_fence_slab_fini(void); 443 444 /* 445 * IRQS. 446 */ 447 448 struct amdgpu_flip_work { 449 struct delayed_work flip_work; 450 struct work_struct unpin_work; 451 struct amdgpu_device *adev; 452 int crtc_id; 453 u32 target_vblank; 454 uint64_t base; 455 struct drm_pending_vblank_event *event; 456 struct amdgpu_bo *old_abo; 457 unsigned shared_count; 458 struct dma_fence **shared; 459 struct dma_fence_cb cb; 460 bool async; 461 }; 462 463 464 /* 465 * file private structure 466 */ 467 468 struct amdgpu_fpriv { 469 struct amdgpu_vm vm; 470 struct amdgpu_bo_va *prt_va; 471 struct amdgpu_bo_va *csa_va; 472 struct amdgpu_bo_va *seq64_va; 473 struct mutex bo_list_lock; 474 struct idr bo_list_handles; 475 struct amdgpu_ctx_mgr ctx_mgr; 476 /** GPU partition selection */ 477 uint32_t xcp_id; 478 }; 479 480 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 481 482 /* 483 * Writeback 484 */ 485 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 486 487 struct amdgpu_wb { 488 struct amdgpu_bo *wb_obj; 489 volatile uint32_t *wb; 490 uint64_t gpu_addr; 491 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 492 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 493 }; 494 495 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 496 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 497 498 /* 499 * Benchmarking 500 */ 501 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 502 503 /* 504 * ASIC specific register table accessible by UMD 505 */ 506 struct amdgpu_allowed_register_entry { 507 uint32_t reg_offset; 508 bool grbm_indexed; 509 }; 510 511 /** 512 * enum amd_reset_method - Methods for resetting AMD GPU devices 513 * 514 * @AMD_RESET_METHOD_NONE: The device will not be reset. 515 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 516 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 517 * any device. 518 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 519 * individually. Suitable only for some discrete GPU, not 520 * available for all ASICs. 521 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 522 * are reset depends on the ASIC. Notably doesn't reset IPs 523 * shared with the CPU on APUs or the memory controllers (so 524 * VRAM is not lost). Not available on all ASICs. 525 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 526 * but without powering off the PCI bus. Suitable only for 527 * discrete GPUs. 528 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 529 * and does a secondary bus reset or FLR, depending on what the 530 * underlying hardware supports. 531 * 532 * Methods available for AMD GPU driver for resetting the device. Not all 533 * methods are suitable for every device. User can override the method using 534 * module parameter `reset_method`. 535 */ 536 enum amd_reset_method { 537 AMD_RESET_METHOD_NONE = -1, 538 AMD_RESET_METHOD_LEGACY = 0, 539 AMD_RESET_METHOD_MODE0, 540 AMD_RESET_METHOD_MODE1, 541 AMD_RESET_METHOD_MODE2, 542 AMD_RESET_METHOD_BACO, 543 AMD_RESET_METHOD_PCI, 544 }; 545 546 struct amdgpu_video_codec_info { 547 u32 codec_type; 548 u32 max_width; 549 u32 max_height; 550 u32 max_pixels_per_frame; 551 u32 max_level; 552 }; 553 554 #define codec_info_build(type, width, height, level) \ 555 .codec_type = type,\ 556 .max_width = width,\ 557 .max_height = height,\ 558 .max_pixels_per_frame = height * width,\ 559 .max_level = level, 560 561 struct amdgpu_video_codecs { 562 const u32 codec_count; 563 const struct amdgpu_video_codec_info *codec_array; 564 }; 565 566 /* 567 * ASIC specific functions. 568 */ 569 struct amdgpu_asic_funcs { 570 bool (*read_disabled_bios)(struct amdgpu_device *adev); 571 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 572 u8 *bios, u32 length_bytes); 573 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 574 u32 sh_num, u32 reg_offset, u32 *value); 575 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 576 int (*reset)(struct amdgpu_device *adev); 577 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 578 /* get the reference clock */ 579 u32 (*get_xclk)(struct amdgpu_device *adev); 580 /* MM block clocks */ 581 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 582 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 583 /* static power management */ 584 int (*get_pcie_lanes)(struct amdgpu_device *adev); 585 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 586 /* get config memsize register */ 587 u32 (*get_config_memsize)(struct amdgpu_device *adev); 588 /* flush hdp write queue */ 589 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 590 /* invalidate hdp read cache */ 591 void (*invalidate_hdp)(struct amdgpu_device *adev, 592 struct amdgpu_ring *ring); 593 /* check if the asic needs a full reset of if soft reset will work */ 594 bool (*need_full_reset)(struct amdgpu_device *adev); 595 /* initialize doorbell layout for specific asic*/ 596 void (*init_doorbell_index)(struct amdgpu_device *adev); 597 /* PCIe bandwidth usage */ 598 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 599 uint64_t *count1); 600 /* do we need to reset the asic at init time (e.g., kexec) */ 601 bool (*need_reset_on_init)(struct amdgpu_device *adev); 602 /* PCIe replay counter */ 603 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 604 /* device supports BACO */ 605 bool (*supports_baco)(struct amdgpu_device *adev); 606 /* pre asic_init quirks */ 607 void (*pre_asic_init)(struct amdgpu_device *adev); 608 /* enter/exit umd stable pstate */ 609 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 610 /* query video codecs */ 611 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 612 const struct amdgpu_video_codecs **codecs); 613 /* encode "> 32bits" smn addressing */ 614 u64 (*encode_ext_smn_addressing)(int ext_id); 615 }; 616 617 /* 618 * IOCTL. 619 */ 620 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 621 struct drm_file *filp); 622 623 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 624 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 625 struct drm_file *filp); 626 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 627 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 628 struct drm_file *filp); 629 630 /* VRAM scratch page for HDP bug, default vram page */ 631 struct amdgpu_mem_scratch { 632 struct amdgpu_bo *robj; 633 volatile uint32_t *ptr; 634 u64 gpu_addr; 635 }; 636 637 /* 638 * CGS 639 */ 640 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 641 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 642 643 /* 644 * Core structure, functions and helpers. 645 */ 646 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 647 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 648 649 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 650 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 651 652 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 653 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 654 655 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 656 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 657 658 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 659 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 660 661 struct amdgpu_mmio_remap { 662 u32 reg_offset; 663 resource_size_t bus_addr; 664 }; 665 666 /* Define the HW IP blocks will be used in driver , add more if necessary */ 667 enum amd_hw_ip_block_type { 668 GC_HWIP = 1, 669 HDP_HWIP, 670 SDMA0_HWIP, 671 SDMA1_HWIP, 672 SDMA2_HWIP, 673 SDMA3_HWIP, 674 SDMA4_HWIP, 675 SDMA5_HWIP, 676 SDMA6_HWIP, 677 SDMA7_HWIP, 678 LSDMA_HWIP, 679 MMHUB_HWIP, 680 ATHUB_HWIP, 681 NBIO_HWIP, 682 MP0_HWIP, 683 MP1_HWIP, 684 UVD_HWIP, 685 VCN_HWIP = UVD_HWIP, 686 JPEG_HWIP = VCN_HWIP, 687 VCN1_HWIP, 688 VCE_HWIP, 689 VPE_HWIP, 690 DF_HWIP, 691 DCE_HWIP, 692 OSSSYS_HWIP, 693 SMUIO_HWIP, 694 PWR_HWIP, 695 NBIF_HWIP, 696 THM_HWIP, 697 CLK_HWIP, 698 UMC_HWIP, 699 RSMU_HWIP, 700 XGMI_HWIP, 701 DCI_HWIP, 702 PCIE_HWIP, 703 MAX_HWIP 704 }; 705 706 #define HWIP_MAX_INSTANCE 44 707 708 #define HW_ID_MAX 300 709 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 710 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 711 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 712 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 713 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 714 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 715 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 716 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 717 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 718 719 struct amdgpu_ip_map_info { 720 /* Map of logical to actual dev instances/mask */ 721 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 722 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 723 enum amd_hw_ip_block_type block, 724 int8_t inst); 725 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 726 enum amd_hw_ip_block_type block, 727 uint32_t mask); 728 }; 729 730 struct amd_powerplay { 731 void *pp_handle; 732 const struct amd_pm_funcs *pp_funcs; 733 }; 734 735 struct ip_discovery_top; 736 737 /* polaris10 kickers */ 738 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 739 ((rid == 0xE3) || \ 740 (rid == 0xE4) || \ 741 (rid == 0xE5) || \ 742 (rid == 0xE7) || \ 743 (rid == 0xEF))) || \ 744 ((did == 0x6FDF) && \ 745 ((rid == 0xE7) || \ 746 (rid == 0xEF) || \ 747 (rid == 0xFF)))) 748 749 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 750 ((rid == 0xE1) || \ 751 (rid == 0xF7))) 752 753 /* polaris11 kickers */ 754 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 755 ((rid == 0xE0) || \ 756 (rid == 0xE5))) || \ 757 ((did == 0x67FF) && \ 758 ((rid == 0xCF) || \ 759 (rid == 0xEF) || \ 760 (rid == 0xFF)))) 761 762 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 763 ((rid == 0xE2))) 764 765 /* polaris12 kickers */ 766 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 767 ((rid == 0xC0) || \ 768 (rid == 0xC1) || \ 769 (rid == 0xC3) || \ 770 (rid == 0xC7))) || \ 771 ((did == 0x6981) && \ 772 ((rid == 0x00) || \ 773 (rid == 0x01) || \ 774 (rid == 0x10)))) 775 776 struct amdgpu_mqd_prop { 777 uint64_t mqd_gpu_addr; 778 uint64_t hqd_base_gpu_addr; 779 uint64_t rptr_gpu_addr; 780 uint64_t wptr_gpu_addr; 781 uint32_t queue_size; 782 bool use_doorbell; 783 uint32_t doorbell_index; 784 uint64_t eop_gpu_addr; 785 uint32_t hqd_pipe_priority; 786 uint32_t hqd_queue_priority; 787 bool hqd_active; 788 }; 789 790 struct amdgpu_mqd { 791 unsigned mqd_size; 792 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 793 struct amdgpu_mqd_prop *p); 794 }; 795 796 #define AMDGPU_RESET_MAGIC_NUM 64 797 #define AMDGPU_MAX_DF_PERFMONS 4 798 struct amdgpu_reset_domain; 799 struct amdgpu_fru_info; 800 801 struct amdgpu_reset_info { 802 /* reset dump register */ 803 u32 *reset_dump_reg_list; 804 u32 *reset_dump_reg_value; 805 int num_regs; 806 807 #ifdef CONFIG_DEV_COREDUMP 808 struct amdgpu_coredump_info *coredump_info; 809 #endif 810 }; 811 812 /* 813 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 814 */ 815 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 816 817 struct amdgpu_device { 818 struct device *dev; 819 struct pci_dev *pdev; 820 struct drm_device ddev; 821 822 #ifdef CONFIG_DRM_AMD_ACP 823 struct amdgpu_acp acp; 824 #endif 825 struct amdgpu_hive_info *hive; 826 struct amdgpu_xcp_mgr *xcp_mgr; 827 /* ASIC */ 828 enum amd_asic_type asic_type; 829 uint32_t family; 830 uint32_t rev_id; 831 uint32_t external_rev_id; 832 unsigned long flags; 833 unsigned long apu_flags; 834 int usec_timeout; 835 const struct amdgpu_asic_funcs *asic_funcs; 836 bool shutdown; 837 bool need_swiotlb; 838 bool accel_working; 839 struct notifier_block acpi_nb; 840 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 841 struct debugfs_blob_wrapper debugfs_vbios_blob; 842 struct debugfs_blob_wrapper debugfs_discovery_blob; 843 struct mutex srbm_mutex; 844 /* GRBM index mutex. Protects concurrent access to GRBM index */ 845 struct mutex grbm_idx_mutex; 846 struct dev_pm_domain vga_pm_domain; 847 bool have_disp_power_ref; 848 bool have_atomics_support; 849 850 /* BIOS */ 851 bool is_atom_fw; 852 uint8_t *bios; 853 uint32_t bios_size; 854 uint32_t bios_scratch_reg_offset; 855 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 856 857 /* Register/doorbell mmio */ 858 resource_size_t rmmio_base; 859 resource_size_t rmmio_size; 860 void __iomem *rmmio; 861 /* protects concurrent MM_INDEX/DATA based register access */ 862 spinlock_t mmio_idx_lock; 863 struct amdgpu_mmio_remap rmmio_remap; 864 /* protects concurrent SMC based register access */ 865 spinlock_t smc_idx_lock; 866 amdgpu_rreg_t smc_rreg; 867 amdgpu_wreg_t smc_wreg; 868 /* protects concurrent PCIE register access */ 869 spinlock_t pcie_idx_lock; 870 amdgpu_rreg_t pcie_rreg; 871 amdgpu_wreg_t pcie_wreg; 872 amdgpu_rreg_t pciep_rreg; 873 amdgpu_wreg_t pciep_wreg; 874 amdgpu_rreg_ext_t pcie_rreg_ext; 875 amdgpu_wreg_ext_t pcie_wreg_ext; 876 amdgpu_rreg64_t pcie_rreg64; 877 amdgpu_wreg64_t pcie_wreg64; 878 amdgpu_rreg64_ext_t pcie_rreg64_ext; 879 amdgpu_wreg64_ext_t pcie_wreg64_ext; 880 /* protects concurrent UVD register access */ 881 spinlock_t uvd_ctx_idx_lock; 882 amdgpu_rreg_t uvd_ctx_rreg; 883 amdgpu_wreg_t uvd_ctx_wreg; 884 /* protects concurrent DIDT register access */ 885 spinlock_t didt_idx_lock; 886 amdgpu_rreg_t didt_rreg; 887 amdgpu_wreg_t didt_wreg; 888 /* protects concurrent gc_cac register access */ 889 spinlock_t gc_cac_idx_lock; 890 amdgpu_rreg_t gc_cac_rreg; 891 amdgpu_wreg_t gc_cac_wreg; 892 /* protects concurrent se_cac register access */ 893 spinlock_t se_cac_idx_lock; 894 amdgpu_rreg_t se_cac_rreg; 895 amdgpu_wreg_t se_cac_wreg; 896 /* protects concurrent ENDPOINT (audio) register access */ 897 spinlock_t audio_endpt_idx_lock; 898 amdgpu_block_rreg_t audio_endpt_rreg; 899 amdgpu_block_wreg_t audio_endpt_wreg; 900 struct amdgpu_doorbell doorbell; 901 902 /* clock/pll info */ 903 struct amdgpu_clock clock; 904 905 /* MC */ 906 struct amdgpu_gmc gmc; 907 struct amdgpu_gart gart; 908 dma_addr_t dummy_page_addr; 909 struct amdgpu_vm_manager vm_manager; 910 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 911 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 912 913 /* memory management */ 914 struct amdgpu_mman mman; 915 struct amdgpu_mem_scratch mem_scratch; 916 struct amdgpu_wb wb; 917 atomic64_t num_bytes_moved; 918 atomic64_t num_evictions; 919 atomic64_t num_vram_cpu_page_faults; 920 atomic_t gpu_reset_counter; 921 atomic_t vram_lost_counter; 922 923 /* data for buffer migration throttling */ 924 struct { 925 spinlock_t lock; 926 s64 last_update_us; 927 s64 accum_us; /* accumulated microseconds */ 928 s64 accum_us_vis; /* for visible VRAM */ 929 u32 log2_max_MBps; 930 } mm_stats; 931 932 /* display */ 933 bool enable_virtual_display; 934 struct amdgpu_vkms_output *amdgpu_vkms_output; 935 struct amdgpu_mode_info mode_info; 936 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 937 struct delayed_work hotplug_work; 938 struct amdgpu_irq_src crtc_irq; 939 struct amdgpu_irq_src vline0_irq; 940 struct amdgpu_irq_src vupdate_irq; 941 struct amdgpu_irq_src pageflip_irq; 942 struct amdgpu_irq_src hpd_irq; 943 struct amdgpu_irq_src dmub_trace_irq; 944 struct amdgpu_irq_src dmub_outbox_irq; 945 946 /* rings */ 947 u64 fence_context; 948 unsigned num_rings; 949 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 950 struct dma_fence __rcu *gang_submit; 951 bool ib_pool_ready; 952 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 953 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 954 955 /* interrupts */ 956 struct amdgpu_irq irq; 957 958 /* powerplay */ 959 struct amd_powerplay powerplay; 960 struct amdgpu_pm pm; 961 u64 cg_flags; 962 u32 pg_flags; 963 964 /* nbio */ 965 struct amdgpu_nbio nbio; 966 967 /* hdp */ 968 struct amdgpu_hdp hdp; 969 970 /* smuio */ 971 struct amdgpu_smuio smuio; 972 973 /* mmhub */ 974 struct amdgpu_mmhub mmhub; 975 976 /* gfxhub */ 977 struct amdgpu_gfxhub gfxhub; 978 979 /* gfx */ 980 struct amdgpu_gfx gfx; 981 982 /* sdma */ 983 struct amdgpu_sdma sdma; 984 985 /* lsdma */ 986 struct amdgpu_lsdma lsdma; 987 988 /* uvd */ 989 struct amdgpu_uvd uvd; 990 991 /* vce */ 992 struct amdgpu_vce vce; 993 994 /* vcn */ 995 struct amdgpu_vcn vcn; 996 997 /* jpeg */ 998 struct amdgpu_jpeg jpeg; 999 1000 /* vpe */ 1001 struct amdgpu_vpe vpe; 1002 1003 /* umsch */ 1004 struct amdgpu_umsch_mm umsch_mm; 1005 bool enable_umsch_mm; 1006 1007 /* firmwares */ 1008 struct amdgpu_firmware firmware; 1009 1010 /* PSP */ 1011 struct psp_context psp; 1012 1013 /* GDS */ 1014 struct amdgpu_gds gds; 1015 1016 /* for userq and VM fences */ 1017 struct amdgpu_seq64 seq64; 1018 1019 /* KFD */ 1020 struct amdgpu_kfd_dev kfd; 1021 1022 /* UMC */ 1023 struct amdgpu_umc umc; 1024 1025 /* display related functionality */ 1026 struct amdgpu_display_manager dm; 1027 1028 /* mes */ 1029 bool enable_mes; 1030 bool enable_mes_kiq; 1031 struct amdgpu_mes mes; 1032 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1033 1034 /* df */ 1035 struct amdgpu_df df; 1036 1037 /* MCA */ 1038 struct amdgpu_mca mca; 1039 1040 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1041 uint32_t harvest_ip_mask; 1042 int num_ip_blocks; 1043 struct mutex mn_lock; 1044 DECLARE_HASHTABLE(mn_hash, 7); 1045 1046 /* tracking pinned memory */ 1047 atomic64_t vram_pin_size; 1048 atomic64_t visible_pin_size; 1049 atomic64_t gart_pin_size; 1050 1051 /* soc15 register offset based on ip, instance and segment */ 1052 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1053 struct amdgpu_ip_map_info ip_map; 1054 1055 /* delayed work_func for deferring clockgating during resume */ 1056 struct delayed_work delayed_init_work; 1057 1058 struct amdgpu_virt virt; 1059 1060 /* link all shadow bo */ 1061 struct list_head shadow_list; 1062 struct mutex shadow_list_lock; 1063 1064 /* record hw reset is performed */ 1065 bool has_hw_reset; 1066 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1067 1068 /* s3/s4 mask */ 1069 bool in_suspend; 1070 bool in_s3; 1071 bool in_s4; 1072 bool in_s0ix; 1073 1074 enum pp_mp1_state mp1_state; 1075 struct amdgpu_doorbell_index doorbell_index; 1076 1077 struct mutex notifier_lock; 1078 1079 int asic_reset_res; 1080 struct work_struct xgmi_reset_work; 1081 struct list_head reset_list; 1082 1083 long gfx_timeout; 1084 long sdma_timeout; 1085 long video_timeout; 1086 long compute_timeout; 1087 1088 uint64_t unique_id; 1089 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1090 1091 /* enable runtime pm on the device */ 1092 bool in_runpm; 1093 bool has_pr3; 1094 1095 bool ucode_sysfs_en; 1096 1097 struct amdgpu_fru_info *fru_info; 1098 atomic_t throttling_logging_enabled; 1099 struct ratelimit_state throttling_logging_rs; 1100 uint32_t ras_hw_enabled; 1101 uint32_t ras_enabled; 1102 1103 bool no_hw_access; 1104 struct pci_saved_state *pci_state; 1105 pci_channel_state_t pci_channel_state; 1106 1107 /* Track auto wait count on s_barrier settings */ 1108 bool barrier_has_auto_waitcnt; 1109 1110 struct amdgpu_reset_control *reset_cntl; 1111 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1112 1113 bool ram_is_direct_mapped; 1114 1115 struct list_head ras_list; 1116 1117 struct ip_discovery_top *ip_top; 1118 1119 struct amdgpu_reset_domain *reset_domain; 1120 1121 struct mutex benchmark_mutex; 1122 1123 struct amdgpu_reset_info reset_info; 1124 1125 bool scpm_enabled; 1126 uint32_t scpm_status; 1127 1128 struct work_struct reset_work; 1129 1130 bool job_hang; 1131 bool dc_enabled; 1132 /* Mask of active clusters */ 1133 uint32_t aid_mask; 1134 1135 /* Debug */ 1136 bool debug_vm; 1137 bool debug_largebar; 1138 bool debug_disable_soft_recovery; 1139 }; 1140 1141 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1142 uint8_t ip, uint8_t inst) 1143 { 1144 /* This considers only major/minor/rev and ignores 1145 * subrevision/variant fields. 1146 */ 1147 return adev->ip_versions[ip][inst] & ~0xFFU; 1148 } 1149 1150 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1151 uint8_t ip, uint8_t inst) 1152 { 1153 /* This returns full version - major/minor/rev/variant/subrevision */ 1154 return adev->ip_versions[ip][inst]; 1155 } 1156 1157 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1158 { 1159 return container_of(ddev, struct amdgpu_device, ddev); 1160 } 1161 1162 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1163 { 1164 return &adev->ddev; 1165 } 1166 1167 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1168 { 1169 return container_of(bdev, struct amdgpu_device, mman.bdev); 1170 } 1171 1172 int amdgpu_device_init(struct amdgpu_device *adev, 1173 uint32_t flags); 1174 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1175 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1176 1177 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1178 1179 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1180 void *buf, size_t size, bool write); 1181 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1182 void *buf, size_t size, bool write); 1183 1184 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1185 void *buf, size_t size, bool write); 1186 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1187 uint32_t inst, uint32_t reg_addr, char reg_name[], 1188 uint32_t expected_value, uint32_t mask); 1189 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1190 uint32_t reg, uint32_t acc_flags); 1191 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1192 u64 reg_addr); 1193 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1194 uint32_t reg, uint32_t acc_flags, 1195 uint32_t xcc_id); 1196 void amdgpu_device_wreg(struct amdgpu_device *adev, 1197 uint32_t reg, uint32_t v, 1198 uint32_t acc_flags); 1199 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1200 u64 reg_addr, u32 reg_data); 1201 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1202 uint32_t reg, uint32_t v, 1203 uint32_t acc_flags, 1204 uint32_t xcc_id); 1205 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1206 uint32_t reg, uint32_t v, uint32_t xcc_id); 1207 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1208 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1209 1210 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1211 u32 reg_addr); 1212 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1213 u32 reg_addr); 1214 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1215 u64 reg_addr); 1216 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1217 u32 reg_addr, u32 reg_data); 1218 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1219 u32 reg_addr, u64 reg_data); 1220 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1221 u64 reg_addr, u64 reg_data); 1222 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1223 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1224 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1225 1226 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1227 1228 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1229 struct amdgpu_reset_context *reset_context); 1230 1231 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1232 struct amdgpu_reset_context *reset_context); 1233 1234 int emu_soc_asic_init(struct amdgpu_device *adev); 1235 1236 /* 1237 * Registers read & write functions. 1238 */ 1239 #define AMDGPU_REGS_NO_KIQ (1<<1) 1240 #define AMDGPU_REGS_RLC (1<<2) 1241 1242 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1243 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1244 1245 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1246 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1247 1248 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1249 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1250 1251 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1252 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1253 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1254 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1255 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1256 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1257 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1258 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1259 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1260 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1261 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1262 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1263 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1264 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1265 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1266 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1267 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1268 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1269 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1270 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1271 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1272 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1273 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1274 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1275 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1276 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1277 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1278 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1279 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1280 #define WREG32_P(reg, val, mask) \ 1281 do { \ 1282 uint32_t tmp_ = RREG32(reg); \ 1283 tmp_ &= (mask); \ 1284 tmp_ |= ((val) & ~(mask)); \ 1285 WREG32(reg, tmp_); \ 1286 } while (0) 1287 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1288 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1289 #define WREG32_PLL_P(reg, val, mask) \ 1290 do { \ 1291 uint32_t tmp_ = RREG32_PLL(reg); \ 1292 tmp_ &= (mask); \ 1293 tmp_ |= ((val) & ~(mask)); \ 1294 WREG32_PLL(reg, tmp_); \ 1295 } while (0) 1296 1297 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1298 do { \ 1299 u32 tmp = RREG32_SMC(_Reg); \ 1300 tmp &= (_Mask); \ 1301 tmp |= ((_Val) & ~(_Mask)); \ 1302 WREG32_SMC(_Reg, tmp); \ 1303 } while (0) 1304 1305 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1306 1307 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1308 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1309 1310 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1311 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1312 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1313 1314 #define REG_GET_FIELD(value, reg, field) \ 1315 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1316 1317 #define WREG32_FIELD(reg, field, val) \ 1318 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1319 1320 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1321 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1322 1323 /* 1324 * BIOS helpers. 1325 */ 1326 #define RBIOS8(i) (adev->bios[i]) 1327 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1328 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1329 1330 /* 1331 * ASICs macro. 1332 */ 1333 #define amdgpu_asic_set_vga_state(adev, state) \ 1334 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1335 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1336 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1337 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1338 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1339 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1340 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1341 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1342 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1343 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1344 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1345 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1346 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1347 #define amdgpu_asic_flush_hdp(adev, r) \ 1348 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1349 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1350 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1351 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1352 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1353 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1354 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1355 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1356 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1357 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1358 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1359 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1360 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1361 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1362 1363 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1364 1365 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1366 #define for_each_inst(i, inst_mask) \ 1367 for (i = ffs(inst_mask); i-- != 0; \ 1368 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1369 1370 /* Common functions */ 1371 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1372 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1373 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1374 struct amdgpu_job *job, 1375 struct amdgpu_reset_context *reset_context); 1376 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1377 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1378 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1379 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1380 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1381 1382 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1383 u64 num_vis_bytes); 1384 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1385 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1386 const u32 *registers, 1387 const u32 array_size); 1388 1389 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1390 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1391 bool amdgpu_device_supports_px(struct drm_device *dev); 1392 bool amdgpu_device_supports_boco(struct drm_device *dev); 1393 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1394 bool amdgpu_device_supports_baco(struct drm_device *dev); 1395 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1396 struct amdgpu_device *peer_adev); 1397 int amdgpu_device_baco_enter(struct drm_device *dev); 1398 int amdgpu_device_baco_exit(struct drm_device *dev); 1399 1400 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1401 struct amdgpu_ring *ring); 1402 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1403 struct amdgpu_ring *ring); 1404 1405 void amdgpu_device_halt(struct amdgpu_device *adev); 1406 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1407 u32 reg); 1408 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1409 u32 reg, u32 v); 1410 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1411 struct dma_fence *gang); 1412 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1413 1414 /* atpx handler */ 1415 #if defined(CONFIG_VGA_SWITCHEROO) 1416 void amdgpu_register_atpx_handler(void); 1417 void amdgpu_unregister_atpx_handler(void); 1418 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1419 bool amdgpu_is_atpx_hybrid(void); 1420 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1421 bool amdgpu_has_atpx(void); 1422 #else 1423 static inline void amdgpu_register_atpx_handler(void) {} 1424 static inline void amdgpu_unregister_atpx_handler(void) {} 1425 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1426 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1427 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1428 static inline bool amdgpu_has_atpx(void) { return false; } 1429 #endif 1430 1431 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1432 void *amdgpu_atpx_get_dhandle(void); 1433 #else 1434 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1435 #endif 1436 1437 /* 1438 * KMS 1439 */ 1440 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1441 extern const int amdgpu_max_kms_ioctl; 1442 1443 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1444 void amdgpu_driver_unload_kms(struct drm_device *dev); 1445 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1446 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1447 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1448 struct drm_file *file_priv); 1449 void amdgpu_driver_release_kms(struct drm_device *dev); 1450 1451 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1452 int amdgpu_device_prepare(struct drm_device *dev); 1453 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1454 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1455 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1456 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1457 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1458 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1459 struct drm_file *filp); 1460 1461 /* 1462 * functions used by amdgpu_encoder.c 1463 */ 1464 struct amdgpu_afmt_acr { 1465 u32 clock; 1466 1467 int n_32khz; 1468 int cts_32khz; 1469 1470 int n_44_1khz; 1471 int cts_44_1khz; 1472 1473 int n_48khz; 1474 int cts_48khz; 1475 1476 }; 1477 1478 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1479 1480 /* amdgpu_acpi.c */ 1481 1482 struct amdgpu_numa_info { 1483 uint64_t size; 1484 int pxm; 1485 int nid; 1486 }; 1487 1488 /* ATCS Device/Driver State */ 1489 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1490 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1491 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1492 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1493 1494 #if defined(CONFIG_ACPI) 1495 int amdgpu_acpi_init(struct amdgpu_device *adev); 1496 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1497 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1498 bool amdgpu_acpi_is_power_shift_control_supported(void); 1499 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1500 u8 perf_req, bool advertise); 1501 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1502 u8 dev_state, bool drv_state); 1503 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1504 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1505 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1506 u64 *tmr_size); 1507 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1508 struct amdgpu_numa_info *numa_info); 1509 1510 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1511 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1512 void amdgpu_acpi_detect(void); 1513 void amdgpu_acpi_release(void); 1514 #else 1515 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1516 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1517 u64 *tmr_offset, u64 *tmr_size) 1518 { 1519 return -EINVAL; 1520 } 1521 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1522 int xcc_id, 1523 struct amdgpu_numa_info *numa_info) 1524 { 1525 return -EINVAL; 1526 } 1527 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1528 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1529 static inline void amdgpu_acpi_detect(void) { } 1530 static inline void amdgpu_acpi_release(void) { } 1531 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1532 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1533 u8 dev_state, bool drv_state) { return 0; } 1534 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1535 enum amdgpu_ss ss_state) { return 0; } 1536 #endif 1537 1538 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1539 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1540 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1541 #else 1542 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1543 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1544 #endif 1545 1546 #if defined(CONFIG_DRM_AMD_DC) 1547 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1548 #else 1549 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1550 #endif 1551 1552 1553 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1554 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1555 1556 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1557 pci_channel_state_t state); 1558 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1559 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1560 void amdgpu_pci_resume(struct pci_dev *pdev); 1561 1562 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1563 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1564 1565 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1566 1567 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1568 enum amd_clockgating_state state); 1569 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1570 enum amd_powergating_state state); 1571 1572 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1573 { 1574 return amdgpu_gpu_recovery != 0 && 1575 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1576 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1577 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1578 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1579 } 1580 1581 #include "amdgpu_object.h" 1582 1583 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1584 { 1585 return adev->gmc.tmz_enabled; 1586 } 1587 1588 int amdgpu_in_reset(struct amdgpu_device *adev); 1589 1590 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1591 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1592 extern const struct attribute_group amdgpu_flash_attr_group; 1593 1594 #endif 1595