1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 #include "amd_powerplay.h" 56 #include "amdgpu_acp.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern unsigned amdgpu_ip_block_mask; 79 extern int amdgpu_bapm; 80 extern int amdgpu_deep_color; 81 extern int amdgpu_vm_size; 82 extern int amdgpu_vm_block_size; 83 extern int amdgpu_vm_fault_stop; 84 extern int amdgpu_vm_debug; 85 extern int amdgpu_sched_jobs; 86 extern int amdgpu_sched_hw_submission; 87 extern int amdgpu_powerplay; 88 extern unsigned amdgpu_pcie_gen_cap; 89 extern unsigned amdgpu_pcie_lane_cap; 90 91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 95 #define AMDGPU_IB_POOL_SIZE 16 96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 97 #define AMDGPUFB_CONN_LIMIT 4 98 #define AMDGPU_BIOS_NUM_SCRATCH 8 99 100 /* max number of rings */ 101 #define AMDGPU_MAX_RINGS 16 102 #define AMDGPU_MAX_GFX_RINGS 1 103 #define AMDGPU_MAX_COMPUTE_RINGS 8 104 #define AMDGPU_MAX_VCE_RINGS 2 105 106 /* max number of IP instances */ 107 #define AMDGPU_MAX_SDMA_INSTANCES 2 108 109 /* hardcode that limit for now */ 110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 111 112 /* hard reset data */ 113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 114 115 /* reset flags */ 116 #define AMDGPU_RESET_GFX (1 << 0) 117 #define AMDGPU_RESET_COMPUTE (1 << 1) 118 #define AMDGPU_RESET_DMA (1 << 2) 119 #define AMDGPU_RESET_CP (1 << 3) 120 #define AMDGPU_RESET_GRBM (1 << 4) 121 #define AMDGPU_RESET_DMA1 (1 << 5) 122 #define AMDGPU_RESET_RLC (1 << 6) 123 #define AMDGPU_RESET_SEM (1 << 7) 124 #define AMDGPU_RESET_IH (1 << 8) 125 #define AMDGPU_RESET_VMC (1 << 9) 126 #define AMDGPU_RESET_MC (1 << 10) 127 #define AMDGPU_RESET_DISPLAY (1 << 11) 128 #define AMDGPU_RESET_UVD (1 << 12) 129 #define AMDGPU_RESET_VCE (1 << 13) 130 #define AMDGPU_RESET_VCE1 (1 << 14) 131 132 /* GFX current status */ 133 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 134 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 135 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 136 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 137 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 138 139 /* max cursor sizes (in pixels) */ 140 #define CIK_CURSOR_WIDTH 128 141 #define CIK_CURSOR_HEIGHT 128 142 143 struct amdgpu_device; 144 struct amdgpu_ib; 145 struct amdgpu_vm; 146 struct amdgpu_ring; 147 struct amdgpu_cs_parser; 148 struct amdgpu_job; 149 struct amdgpu_irq_src; 150 struct amdgpu_fpriv; 151 152 enum amdgpu_cp_irq { 153 AMDGPU_CP_IRQ_GFX_EOP = 0, 154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 162 163 AMDGPU_CP_IRQ_LAST 164 }; 165 166 enum amdgpu_sdma_irq { 167 AMDGPU_SDMA_IRQ_TRAP0 = 0, 168 AMDGPU_SDMA_IRQ_TRAP1, 169 170 AMDGPU_SDMA_IRQ_LAST 171 }; 172 173 enum amdgpu_thermal_irq { 174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 176 177 AMDGPU_THERMAL_IRQ_LAST 178 }; 179 180 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 181 enum amd_ip_block_type block_type, 182 enum amd_clockgating_state state); 183 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 184 enum amd_ip_block_type block_type, 185 enum amd_powergating_state state); 186 187 struct amdgpu_ip_block_version { 188 enum amd_ip_block_type type; 189 u32 major; 190 u32 minor; 191 u32 rev; 192 const struct amd_ip_funcs *funcs; 193 }; 194 195 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 196 enum amd_ip_block_type type, 197 u32 major, u32 minor); 198 199 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 200 struct amdgpu_device *adev, 201 enum amd_ip_block_type type); 202 203 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 204 struct amdgpu_buffer_funcs { 205 /* maximum bytes in a single operation */ 206 uint32_t copy_max_bytes; 207 208 /* number of dw to reserve per operation */ 209 unsigned copy_num_dw; 210 211 /* used for buffer migration */ 212 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 213 /* src addr in bytes */ 214 uint64_t src_offset, 215 /* dst addr in bytes */ 216 uint64_t dst_offset, 217 /* number of byte to transfer */ 218 uint32_t byte_count); 219 220 /* maximum bytes in a single operation */ 221 uint32_t fill_max_bytes; 222 223 /* number of dw to reserve per operation */ 224 unsigned fill_num_dw; 225 226 /* used for buffer clearing */ 227 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 228 /* value to write to memory */ 229 uint32_t src_data, 230 /* dst addr in bytes */ 231 uint64_t dst_offset, 232 /* number of byte to fill */ 233 uint32_t byte_count); 234 }; 235 236 /* provided by hw blocks that can write ptes, e.g., sdma */ 237 struct amdgpu_vm_pte_funcs { 238 /* copy pte entries from GART */ 239 void (*copy_pte)(struct amdgpu_ib *ib, 240 uint64_t pe, uint64_t src, 241 unsigned count); 242 /* write pte one entry at a time with addr mapping */ 243 void (*write_pte)(struct amdgpu_ib *ib, 244 const dma_addr_t *pages_addr, uint64_t pe, 245 uint64_t addr, unsigned count, 246 uint32_t incr, uint32_t flags); 247 /* for linear pte/pde updates without addr mapping */ 248 void (*set_pte_pde)(struct amdgpu_ib *ib, 249 uint64_t pe, 250 uint64_t addr, unsigned count, 251 uint32_t incr, uint32_t flags); 252 }; 253 254 /* provided by the gmc block */ 255 struct amdgpu_gart_funcs { 256 /* flush the vm tlb via mmio */ 257 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 258 uint32_t vmid); 259 /* write pte/pde updates using the cpu */ 260 int (*set_pte_pde)(struct amdgpu_device *adev, 261 void *cpu_pt_addr, /* cpu addr of page table */ 262 uint32_t gpu_page_idx, /* pte/pde to update */ 263 uint64_t addr, /* addr to write into pte/pde */ 264 uint32_t flags); /* access flags */ 265 }; 266 267 /* provided by the ih block */ 268 struct amdgpu_ih_funcs { 269 /* ring read/write ptr handling, called from interrupt context */ 270 u32 (*get_wptr)(struct amdgpu_device *adev); 271 void (*decode_iv)(struct amdgpu_device *adev, 272 struct amdgpu_iv_entry *entry); 273 void (*set_rptr)(struct amdgpu_device *adev); 274 }; 275 276 /* provided by hw blocks that expose a ring buffer for commands */ 277 struct amdgpu_ring_funcs { 278 /* ring read/write ptr handling */ 279 u32 (*get_rptr)(struct amdgpu_ring *ring); 280 u32 (*get_wptr)(struct amdgpu_ring *ring); 281 void (*set_wptr)(struct amdgpu_ring *ring); 282 /* validating and patching of IBs */ 283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 284 /* command emit functions */ 285 void (*emit_ib)(struct amdgpu_ring *ring, 286 struct amdgpu_ib *ib); 287 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 288 uint64_t seq, unsigned flags); 289 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 291 uint64_t pd_addr); 292 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 293 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); 294 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 295 uint32_t gds_base, uint32_t gds_size, 296 uint32_t gws_base, uint32_t gws_size, 297 uint32_t oa_base, uint32_t oa_size); 298 /* testing functions */ 299 int (*test_ring)(struct amdgpu_ring *ring); 300 int (*test_ib)(struct amdgpu_ring *ring); 301 /* insert NOP packets */ 302 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 303 /* pad the indirect buffer to the necessary number of dw */ 304 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 305 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 306 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 307 }; 308 309 /* 310 * BIOS. 311 */ 312 bool amdgpu_get_bios(struct amdgpu_device *adev); 313 bool amdgpu_read_bios(struct amdgpu_device *adev); 314 315 /* 316 * Dummy page 317 */ 318 struct amdgpu_dummy_page { 319 struct page *page; 320 dma_addr_t addr; 321 }; 322 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 323 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 324 325 326 /* 327 * Clocks 328 */ 329 330 #define AMDGPU_MAX_PPLL 3 331 332 struct amdgpu_clock { 333 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 334 struct amdgpu_pll spll; 335 struct amdgpu_pll mpll; 336 /* 10 Khz units */ 337 uint32_t default_mclk; 338 uint32_t default_sclk; 339 uint32_t default_dispclk; 340 uint32_t current_dispclk; 341 uint32_t dp_extclk; 342 uint32_t max_pixel_clock; 343 }; 344 345 /* 346 * Fences. 347 */ 348 struct amdgpu_fence_driver { 349 uint64_t gpu_addr; 350 volatile uint32_t *cpu_addr; 351 /* sync_seq is protected by ring emission lock */ 352 uint32_t sync_seq; 353 atomic_t last_seq; 354 bool initialized; 355 struct amdgpu_irq_src *irq_src; 356 unsigned irq_type; 357 struct timer_list fallback_timer; 358 unsigned num_fences_mask; 359 spinlock_t lock; 360 struct fence **fences; 361 }; 362 363 /* some special values for the owner field */ 364 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 365 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 366 367 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 368 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 369 370 struct amdgpu_user_fence { 371 /* write-back bo */ 372 struct amdgpu_bo *bo; 373 /* write-back address offset to bo start */ 374 uint32_t offset; 375 }; 376 377 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 378 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 379 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 380 381 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 382 unsigned num_hw_submission); 383 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 384 struct amdgpu_irq_src *irq_src, 385 unsigned irq_type); 386 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 387 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 388 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence); 389 void amdgpu_fence_process(struct amdgpu_ring *ring); 390 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 391 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 392 393 /* 394 * TTM. 395 */ 396 struct amdgpu_mman { 397 struct ttm_bo_global_ref bo_global_ref; 398 struct drm_global_reference mem_global_ref; 399 struct ttm_bo_device bdev; 400 bool mem_global_referenced; 401 bool initialized; 402 403 #if defined(CONFIG_DEBUG_FS) 404 struct dentry *vram; 405 struct dentry *gtt; 406 #endif 407 408 /* buffer handling */ 409 const struct amdgpu_buffer_funcs *buffer_funcs; 410 struct amdgpu_ring *buffer_funcs_ring; 411 /* Scheduler entity for buffer moves */ 412 struct amd_sched_entity entity; 413 }; 414 415 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 416 uint64_t src_offset, 417 uint64_t dst_offset, 418 uint32_t byte_count, 419 struct reservation_object *resv, 420 struct fence **fence); 421 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 422 423 struct amdgpu_bo_list_entry { 424 struct amdgpu_bo *robj; 425 struct ttm_validate_buffer tv; 426 struct amdgpu_bo_va *bo_va; 427 uint32_t priority; 428 struct page **user_pages; 429 int user_invalidated; 430 }; 431 432 struct amdgpu_bo_va_mapping { 433 struct list_head list; 434 struct interval_tree_node it; 435 uint64_t offset; 436 uint32_t flags; 437 }; 438 439 /* bo virtual addresses in a specific vm */ 440 struct amdgpu_bo_va { 441 /* protected by bo being reserved */ 442 struct list_head bo_list; 443 struct fence *last_pt_update; 444 unsigned ref_count; 445 446 /* protected by vm mutex and spinlock */ 447 struct list_head vm_status; 448 449 /* mappings for this bo_va */ 450 struct list_head invalids; 451 struct list_head valids; 452 453 /* constant after initialization */ 454 struct amdgpu_vm *vm; 455 struct amdgpu_bo *bo; 456 }; 457 458 #define AMDGPU_GEM_DOMAIN_MAX 0x3 459 460 struct amdgpu_bo { 461 /* Protected by gem.mutex */ 462 struct list_head list; 463 /* Protected by tbo.reserved */ 464 u32 prefered_domains; 465 u32 allowed_domains; 466 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 467 struct ttm_placement placement; 468 struct ttm_buffer_object tbo; 469 struct ttm_bo_kmap_obj kmap; 470 u64 flags; 471 unsigned pin_count; 472 void *kptr; 473 u64 tiling_flags; 474 u64 metadata_flags; 475 void *metadata; 476 u32 metadata_size; 477 /* list of all virtual address to which this bo 478 * is associated to 479 */ 480 struct list_head va; 481 /* Constant after initialization */ 482 struct amdgpu_device *adev; 483 struct drm_gem_object gem_base; 484 struct amdgpu_bo *parent; 485 486 struct ttm_bo_kmap_obj dma_buf_vmap; 487 struct amdgpu_mn *mn; 488 struct list_head mn_list; 489 }; 490 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 491 492 void amdgpu_gem_object_free(struct drm_gem_object *obj); 493 int amdgpu_gem_object_open(struct drm_gem_object *obj, 494 struct drm_file *file_priv); 495 void amdgpu_gem_object_close(struct drm_gem_object *obj, 496 struct drm_file *file_priv); 497 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 498 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 499 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 500 struct dma_buf_attachment *attach, 501 struct sg_table *sg); 502 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 503 struct drm_gem_object *gobj, 504 int flags); 505 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 506 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 507 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 508 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 509 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 510 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 511 512 /* sub-allocation manager, it has to be protected by another lock. 513 * By conception this is an helper for other part of the driver 514 * like the indirect buffer or semaphore, which both have their 515 * locking. 516 * 517 * Principe is simple, we keep a list of sub allocation in offset 518 * order (first entry has offset == 0, last entry has the highest 519 * offset). 520 * 521 * When allocating new object we first check if there is room at 522 * the end total_size - (last_object_offset + last_object_size) >= 523 * alloc_size. If so we allocate new object there. 524 * 525 * When there is not enough room at the end, we start waiting for 526 * each sub object until we reach object_offset+object_size >= 527 * alloc_size, this object then become the sub object we return. 528 * 529 * Alignment can't be bigger than page size. 530 * 531 * Hole are not considered for allocation to keep things simple. 532 * Assumption is that there won't be hole (all object on same 533 * alignment). 534 */ 535 536 #define AMDGPU_SA_NUM_FENCE_LISTS 32 537 538 struct amdgpu_sa_manager { 539 wait_queue_head_t wq; 540 struct amdgpu_bo *bo; 541 struct list_head *hole; 542 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 543 struct list_head olist; 544 unsigned size; 545 uint64_t gpu_addr; 546 void *cpu_ptr; 547 uint32_t domain; 548 uint32_t align; 549 }; 550 551 /* sub-allocation buffer */ 552 struct amdgpu_sa_bo { 553 struct list_head olist; 554 struct list_head flist; 555 struct amdgpu_sa_manager *manager; 556 unsigned soffset; 557 unsigned eoffset; 558 struct fence *fence; 559 }; 560 561 /* 562 * GEM objects. 563 */ 564 void amdgpu_gem_force_release(struct amdgpu_device *adev); 565 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 566 int alignment, u32 initial_domain, 567 u64 flags, bool kernel, 568 struct drm_gem_object **obj); 569 570 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 571 struct drm_device *dev, 572 struct drm_mode_create_dumb *args); 573 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 574 struct drm_device *dev, 575 uint32_t handle, uint64_t *offset_p); 576 /* 577 * Synchronization 578 */ 579 struct amdgpu_sync { 580 DECLARE_HASHTABLE(fences, 4); 581 struct fence *last_vm_update; 582 }; 583 584 void amdgpu_sync_create(struct amdgpu_sync *sync); 585 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 586 struct fence *f); 587 int amdgpu_sync_resv(struct amdgpu_device *adev, 588 struct amdgpu_sync *sync, 589 struct reservation_object *resv, 590 void *owner); 591 bool amdgpu_sync_is_idle(struct amdgpu_sync *sync); 592 int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src, 593 struct fence *fence); 594 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 595 int amdgpu_sync_wait(struct amdgpu_sync *sync); 596 void amdgpu_sync_free(struct amdgpu_sync *sync); 597 int amdgpu_sync_init(void); 598 void amdgpu_sync_fini(void); 599 600 /* 601 * GART structures, functions & helpers 602 */ 603 struct amdgpu_mc; 604 605 #define AMDGPU_GPU_PAGE_SIZE 4096 606 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 607 #define AMDGPU_GPU_PAGE_SHIFT 12 608 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 609 610 struct amdgpu_gart { 611 dma_addr_t table_addr; 612 struct amdgpu_bo *robj; 613 void *ptr; 614 unsigned num_gpu_pages; 615 unsigned num_cpu_pages; 616 unsigned table_size; 617 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 618 struct page **pages; 619 #endif 620 bool ready; 621 const struct amdgpu_gart_funcs *gart_funcs; 622 }; 623 624 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 625 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 626 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 627 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 628 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 629 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 630 int amdgpu_gart_init(struct amdgpu_device *adev); 631 void amdgpu_gart_fini(struct amdgpu_device *adev); 632 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 633 int pages); 634 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 635 int pages, struct page **pagelist, 636 dma_addr_t *dma_addr, uint32_t flags); 637 638 /* 639 * GPU MC structures, functions & helpers 640 */ 641 struct amdgpu_mc { 642 resource_size_t aper_size; 643 resource_size_t aper_base; 644 resource_size_t agp_base; 645 /* for some chips with <= 32MB we need to lie 646 * about vram size near mc fb location */ 647 u64 mc_vram_size; 648 u64 visible_vram_size; 649 u64 gtt_size; 650 u64 gtt_start; 651 u64 gtt_end; 652 u64 vram_start; 653 u64 vram_end; 654 unsigned vram_width; 655 u64 real_vram_size; 656 int vram_mtrr; 657 u64 gtt_base_align; 658 u64 mc_mask; 659 const struct firmware *fw; /* MC firmware */ 660 uint32_t fw_version; 661 struct amdgpu_irq_src vm_fault; 662 uint32_t vram_type; 663 }; 664 665 /* 666 * GPU doorbell structures, functions & helpers 667 */ 668 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 669 { 670 AMDGPU_DOORBELL_KIQ = 0x000, 671 AMDGPU_DOORBELL_HIQ = 0x001, 672 AMDGPU_DOORBELL_DIQ = 0x002, 673 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 674 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 675 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 676 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 677 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 678 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 679 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 680 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 681 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 682 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 683 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 684 AMDGPU_DOORBELL_IH = 0x1E8, 685 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 686 AMDGPU_DOORBELL_INVALID = 0xFFFF 687 } AMDGPU_DOORBELL_ASSIGNMENT; 688 689 struct amdgpu_doorbell { 690 /* doorbell mmio */ 691 resource_size_t base; 692 resource_size_t size; 693 u32 __iomem *ptr; 694 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 695 }; 696 697 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 698 phys_addr_t *aperture_base, 699 size_t *aperture_size, 700 size_t *start_offset); 701 702 /* 703 * IRQS. 704 */ 705 706 struct amdgpu_flip_work { 707 struct work_struct flip_work; 708 struct work_struct unpin_work; 709 struct amdgpu_device *adev; 710 int crtc_id; 711 uint64_t base; 712 struct drm_pending_vblank_event *event; 713 struct amdgpu_bo *old_rbo; 714 struct fence *excl; 715 unsigned shared_count; 716 struct fence **shared; 717 struct fence_cb cb; 718 }; 719 720 721 /* 722 * CP & rings. 723 */ 724 725 struct amdgpu_ib { 726 struct amdgpu_sa_bo *sa_bo; 727 uint32_t length_dw; 728 uint64_t gpu_addr; 729 uint32_t *ptr; 730 struct amdgpu_user_fence *user; 731 struct amdgpu_vm *vm; 732 unsigned vm_id; 733 uint64_t vm_pd_addr; 734 struct amdgpu_ctx *ctx; 735 uint32_t gds_base, gds_size; 736 uint32_t gws_base, gws_size; 737 uint32_t oa_base, oa_size; 738 uint32_t flags; 739 /* resulting sequence number */ 740 uint64_t sequence; 741 }; 742 743 enum amdgpu_ring_type { 744 AMDGPU_RING_TYPE_GFX, 745 AMDGPU_RING_TYPE_COMPUTE, 746 AMDGPU_RING_TYPE_SDMA, 747 AMDGPU_RING_TYPE_UVD, 748 AMDGPU_RING_TYPE_VCE 749 }; 750 751 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 752 753 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 754 struct amdgpu_job **job); 755 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 756 struct amdgpu_job **job); 757 758 void amdgpu_job_free(struct amdgpu_job *job); 759 void amdgpu_job_free_func(struct kref *refcount); 760 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 761 struct amd_sched_entity *entity, void *owner, 762 struct fence **f); 763 void amdgpu_job_timeout_func(struct work_struct *work); 764 765 struct amdgpu_ring { 766 struct amdgpu_device *adev; 767 const struct amdgpu_ring_funcs *funcs; 768 struct amdgpu_fence_driver fence_drv; 769 struct amd_gpu_scheduler sched; 770 771 spinlock_t fence_lock; 772 struct amdgpu_bo *ring_obj; 773 volatile uint32_t *ring; 774 unsigned rptr_offs; 775 u64 next_rptr_gpu_addr; 776 volatile u32 *next_rptr_cpu_addr; 777 unsigned wptr; 778 unsigned wptr_old; 779 unsigned ring_size; 780 unsigned max_dw; 781 int count_dw; 782 uint64_t gpu_addr; 783 uint32_t align_mask; 784 uint32_t ptr_mask; 785 bool ready; 786 u32 nop; 787 u32 idx; 788 u32 me; 789 u32 pipe; 790 u32 queue; 791 struct amdgpu_bo *mqd_obj; 792 u32 doorbell_index; 793 bool use_doorbell; 794 unsigned wptr_offs; 795 unsigned next_rptr_offs; 796 unsigned fence_offs; 797 struct amdgpu_ctx *current_ctx; 798 enum amdgpu_ring_type type; 799 char name[16]; 800 unsigned cond_exe_offs; 801 u64 cond_exe_gpu_addr; 802 volatile u32 *cond_exe_cpu_addr; 803 }; 804 805 /* 806 * VM 807 */ 808 809 /* maximum number of VMIDs */ 810 #define AMDGPU_NUM_VM 16 811 812 /* number of entries in page table */ 813 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 814 815 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 816 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 817 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 818 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 819 820 #define AMDGPU_PTE_VALID (1 << 0) 821 #define AMDGPU_PTE_SYSTEM (1 << 1) 822 #define AMDGPU_PTE_SNOOPED (1 << 2) 823 824 /* VI only */ 825 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 826 827 #define AMDGPU_PTE_READABLE (1 << 5) 828 #define AMDGPU_PTE_WRITEABLE (1 << 6) 829 830 /* PTE (Page Table Entry) fragment field for different page sizes */ 831 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 832 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 833 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 834 835 /* How to programm VM fault handling */ 836 #define AMDGPU_VM_FAULT_STOP_NEVER 0 837 #define AMDGPU_VM_FAULT_STOP_FIRST 1 838 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 839 840 struct amdgpu_vm_pt { 841 struct amdgpu_bo_list_entry entry; 842 uint64_t addr; 843 }; 844 845 struct amdgpu_vm { 846 /* tree of virtual addresses mapped */ 847 struct rb_root va; 848 849 /* protecting invalidated */ 850 spinlock_t status_lock; 851 852 /* BOs moved, but not yet updated in the PT */ 853 struct list_head invalidated; 854 855 /* BOs cleared in the PT because of a move */ 856 struct list_head cleared; 857 858 /* BO mappings freed, but not yet updated in the PT */ 859 struct list_head freed; 860 861 /* contains the page directory */ 862 struct amdgpu_bo *page_directory; 863 unsigned max_pde_used; 864 struct fence *page_directory_fence; 865 866 /* array of page tables, one for each page directory entry */ 867 struct amdgpu_vm_pt *page_tables; 868 869 /* for id and flush management per ring */ 870 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS]; 871 872 /* protecting freed */ 873 spinlock_t freed_lock; 874 875 /* Scheduler entity for page table updates */ 876 struct amd_sched_entity entity; 877 }; 878 879 struct amdgpu_vm_id { 880 struct list_head list; 881 struct fence *first; 882 struct amdgpu_sync active; 883 struct fence *last_flush; 884 atomic_long_t owner; 885 886 uint64_t pd_gpu_addr; 887 /* last flushed PD/PT update */ 888 struct fence *flushed_updates; 889 890 uint32_t gds_base; 891 uint32_t gds_size; 892 uint32_t gws_base; 893 uint32_t gws_size; 894 uint32_t oa_base; 895 uint32_t oa_size; 896 }; 897 898 struct amdgpu_vm_manager { 899 /* Handling of VMIDs */ 900 struct mutex lock; 901 unsigned num_ids; 902 struct list_head ids_lru; 903 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 904 905 uint32_t max_pfn; 906 /* vram base address for page table entry */ 907 u64 vram_base_offset; 908 /* is vm enabled? */ 909 bool enabled; 910 /* vm pte handling */ 911 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 912 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 913 unsigned vm_pte_num_rings; 914 atomic_t vm_pte_next_ring; 915 }; 916 917 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 918 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 919 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 920 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 921 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 922 struct list_head *validated, 923 struct amdgpu_bo_list_entry *entry); 924 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates); 925 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 926 struct amdgpu_vm *vm); 927 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 928 struct amdgpu_sync *sync, struct fence *fence, 929 unsigned *vm_id, uint64_t *vm_pd_addr); 930 int amdgpu_vm_flush(struct amdgpu_ring *ring, 931 unsigned vm_id, uint64_t pd_addr, 932 uint32_t gds_base, uint32_t gds_size, 933 uint32_t gws_base, uint32_t gws_size, 934 uint32_t oa_base, uint32_t oa_size); 935 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id); 936 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 937 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 938 struct amdgpu_vm *vm); 939 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 940 struct amdgpu_vm *vm); 941 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 942 struct amdgpu_sync *sync); 943 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 944 struct amdgpu_bo_va *bo_va, 945 struct ttm_mem_reg *mem); 946 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 947 struct amdgpu_bo *bo); 948 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 949 struct amdgpu_bo *bo); 950 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 951 struct amdgpu_vm *vm, 952 struct amdgpu_bo *bo); 953 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 954 struct amdgpu_bo_va *bo_va, 955 uint64_t addr, uint64_t offset, 956 uint64_t size, uint32_t flags); 957 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 958 struct amdgpu_bo_va *bo_va, 959 uint64_t addr); 960 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 961 struct amdgpu_bo_va *bo_va); 962 963 /* 964 * context related structures 965 */ 966 967 struct amdgpu_ctx_ring { 968 uint64_t sequence; 969 struct fence **fences; 970 struct amd_sched_entity entity; 971 }; 972 973 struct amdgpu_ctx { 974 struct kref refcount; 975 struct amdgpu_device *adev; 976 unsigned reset_counter; 977 spinlock_t ring_lock; 978 struct fence **fences; 979 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 980 }; 981 982 struct amdgpu_ctx_mgr { 983 struct amdgpu_device *adev; 984 struct mutex lock; 985 /* protected by lock */ 986 struct idr ctx_handles; 987 }; 988 989 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 990 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 991 992 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 993 struct fence *fence); 994 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 995 struct amdgpu_ring *ring, uint64_t seq); 996 997 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 998 struct drm_file *filp); 999 1000 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1001 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1002 1003 /* 1004 * file private structure 1005 */ 1006 1007 struct amdgpu_fpriv { 1008 struct amdgpu_vm vm; 1009 struct mutex bo_list_lock; 1010 struct idr bo_list_handles; 1011 struct amdgpu_ctx_mgr ctx_mgr; 1012 }; 1013 1014 /* 1015 * residency list 1016 */ 1017 1018 struct amdgpu_bo_list { 1019 struct mutex lock; 1020 struct amdgpu_bo *gds_obj; 1021 struct amdgpu_bo *gws_obj; 1022 struct amdgpu_bo *oa_obj; 1023 unsigned first_userptr; 1024 unsigned num_entries; 1025 struct amdgpu_bo_list_entry *array; 1026 }; 1027 1028 struct amdgpu_bo_list * 1029 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1030 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 1031 struct list_head *validated); 1032 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1033 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1034 1035 /* 1036 * GFX stuff 1037 */ 1038 #include "clearstate_defs.h" 1039 1040 struct amdgpu_rlc { 1041 /* for power gating */ 1042 struct amdgpu_bo *save_restore_obj; 1043 uint64_t save_restore_gpu_addr; 1044 volatile uint32_t *sr_ptr; 1045 const u32 *reg_list; 1046 u32 reg_list_size; 1047 /* for clear state */ 1048 struct amdgpu_bo *clear_state_obj; 1049 uint64_t clear_state_gpu_addr; 1050 volatile uint32_t *cs_ptr; 1051 const struct cs_section_def *cs_data; 1052 u32 clear_state_size; 1053 /* for cp tables */ 1054 struct amdgpu_bo *cp_table_obj; 1055 uint64_t cp_table_gpu_addr; 1056 volatile uint32_t *cp_table_ptr; 1057 u32 cp_table_size; 1058 }; 1059 1060 struct amdgpu_mec { 1061 struct amdgpu_bo *hpd_eop_obj; 1062 u64 hpd_eop_gpu_addr; 1063 u32 num_pipe; 1064 u32 num_mec; 1065 u32 num_queue; 1066 }; 1067 1068 /* 1069 * GPU scratch registers structures, functions & helpers 1070 */ 1071 struct amdgpu_scratch { 1072 unsigned num_reg; 1073 uint32_t reg_base; 1074 bool free[32]; 1075 uint32_t reg[32]; 1076 }; 1077 1078 /* 1079 * GFX configurations 1080 */ 1081 struct amdgpu_gca_config { 1082 unsigned max_shader_engines; 1083 unsigned max_tile_pipes; 1084 unsigned max_cu_per_sh; 1085 unsigned max_sh_per_se; 1086 unsigned max_backends_per_se; 1087 unsigned max_texture_channel_caches; 1088 unsigned max_gprs; 1089 unsigned max_gs_threads; 1090 unsigned max_hw_contexts; 1091 unsigned sc_prim_fifo_size_frontend; 1092 unsigned sc_prim_fifo_size_backend; 1093 unsigned sc_hiz_tile_fifo_size; 1094 unsigned sc_earlyz_tile_fifo_size; 1095 1096 unsigned num_tile_pipes; 1097 unsigned backend_enable_mask; 1098 unsigned mem_max_burst_length_bytes; 1099 unsigned mem_row_size_in_kb; 1100 unsigned shader_engine_tile_size; 1101 unsigned num_gpus; 1102 unsigned multi_gpu_tile_size; 1103 unsigned mc_arb_ramcfg; 1104 unsigned gb_addr_config; 1105 unsigned num_rbs; 1106 1107 uint32_t tile_mode_array[32]; 1108 uint32_t macrotile_mode_array[16]; 1109 }; 1110 1111 struct amdgpu_gfx { 1112 struct mutex gpu_clock_mutex; 1113 struct amdgpu_gca_config config; 1114 struct amdgpu_rlc rlc; 1115 struct amdgpu_mec mec; 1116 struct amdgpu_scratch scratch; 1117 const struct firmware *me_fw; /* ME firmware */ 1118 uint32_t me_fw_version; 1119 const struct firmware *pfp_fw; /* PFP firmware */ 1120 uint32_t pfp_fw_version; 1121 const struct firmware *ce_fw; /* CE firmware */ 1122 uint32_t ce_fw_version; 1123 const struct firmware *rlc_fw; /* RLC firmware */ 1124 uint32_t rlc_fw_version; 1125 const struct firmware *mec_fw; /* MEC firmware */ 1126 uint32_t mec_fw_version; 1127 const struct firmware *mec2_fw; /* MEC2 firmware */ 1128 uint32_t mec2_fw_version; 1129 uint32_t me_feature_version; 1130 uint32_t ce_feature_version; 1131 uint32_t pfp_feature_version; 1132 uint32_t rlc_feature_version; 1133 uint32_t mec_feature_version; 1134 uint32_t mec2_feature_version; 1135 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1136 unsigned num_gfx_rings; 1137 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1138 unsigned num_compute_rings; 1139 struct amdgpu_irq_src eop_irq; 1140 struct amdgpu_irq_src priv_reg_irq; 1141 struct amdgpu_irq_src priv_inst_irq; 1142 /* gfx status */ 1143 uint32_t gfx_current_status; 1144 /* ce ram size*/ 1145 unsigned ce_ram_size; 1146 }; 1147 1148 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1149 unsigned size, struct amdgpu_ib *ib); 1150 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f); 1151 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1152 struct amdgpu_ib *ib, struct fence *last_vm_update, 1153 struct fence **f); 1154 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1155 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1156 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1157 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1158 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1159 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 1160 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1161 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1162 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1163 uint32_t **data); 1164 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1165 unsigned size, uint32_t *data); 1166 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1167 unsigned ring_size, u32 nop, u32 align_mask, 1168 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1169 enum amdgpu_ring_type ring_type); 1170 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1171 1172 /* 1173 * CS. 1174 */ 1175 struct amdgpu_cs_chunk { 1176 uint32_t chunk_id; 1177 uint32_t length_dw; 1178 uint32_t *kdata; 1179 }; 1180 1181 struct amdgpu_cs_parser { 1182 struct amdgpu_device *adev; 1183 struct drm_file *filp; 1184 struct amdgpu_ctx *ctx; 1185 1186 /* chunks */ 1187 unsigned nchunks; 1188 struct amdgpu_cs_chunk *chunks; 1189 1190 /* scheduler job object */ 1191 struct amdgpu_job *job; 1192 1193 /* buffer objects */ 1194 struct ww_acquire_ctx ticket; 1195 struct amdgpu_bo_list *bo_list; 1196 struct amdgpu_bo_list_entry vm_pd; 1197 struct list_head validated; 1198 struct fence *fence; 1199 uint64_t bytes_moved_threshold; 1200 uint64_t bytes_moved; 1201 1202 /* user fence */ 1203 struct amdgpu_bo_list_entry uf_entry; 1204 }; 1205 1206 struct amdgpu_job { 1207 struct amd_sched_job base; 1208 struct amdgpu_device *adev; 1209 struct amdgpu_ring *ring; 1210 struct amdgpu_sync sync; 1211 struct amdgpu_ib *ibs; 1212 struct fence *fence; /* the hw fence */ 1213 uint32_t num_ibs; 1214 void *owner; 1215 struct amdgpu_user_fence uf; 1216 }; 1217 #define to_amdgpu_job(sched_job) \ 1218 container_of((sched_job), struct amdgpu_job, base) 1219 1220 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1221 uint32_t ib_idx, int idx) 1222 { 1223 return p->job->ibs[ib_idx].ptr[idx]; 1224 } 1225 1226 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1227 uint32_t ib_idx, int idx, 1228 uint32_t value) 1229 { 1230 p->job->ibs[ib_idx].ptr[idx] = value; 1231 } 1232 1233 /* 1234 * Writeback 1235 */ 1236 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1237 1238 struct amdgpu_wb { 1239 struct amdgpu_bo *wb_obj; 1240 volatile uint32_t *wb; 1241 uint64_t gpu_addr; 1242 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1243 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1244 }; 1245 1246 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1247 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1248 1249 1250 1251 enum amdgpu_int_thermal_type { 1252 THERMAL_TYPE_NONE, 1253 THERMAL_TYPE_EXTERNAL, 1254 THERMAL_TYPE_EXTERNAL_GPIO, 1255 THERMAL_TYPE_RV6XX, 1256 THERMAL_TYPE_RV770, 1257 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1258 THERMAL_TYPE_EVERGREEN, 1259 THERMAL_TYPE_SUMO, 1260 THERMAL_TYPE_NI, 1261 THERMAL_TYPE_SI, 1262 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1263 THERMAL_TYPE_CI, 1264 THERMAL_TYPE_KV, 1265 }; 1266 1267 enum amdgpu_dpm_auto_throttle_src { 1268 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1269 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1270 }; 1271 1272 enum amdgpu_dpm_event_src { 1273 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1274 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1275 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1276 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1277 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1278 }; 1279 1280 #define AMDGPU_MAX_VCE_LEVELS 6 1281 1282 enum amdgpu_vce_level { 1283 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1284 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1285 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1286 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1287 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1288 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1289 }; 1290 1291 struct amdgpu_ps { 1292 u32 caps; /* vbios flags */ 1293 u32 class; /* vbios flags */ 1294 u32 class2; /* vbios flags */ 1295 /* UVD clocks */ 1296 u32 vclk; 1297 u32 dclk; 1298 /* VCE clocks */ 1299 u32 evclk; 1300 u32 ecclk; 1301 bool vce_active; 1302 enum amdgpu_vce_level vce_level; 1303 /* asic priv */ 1304 void *ps_priv; 1305 }; 1306 1307 struct amdgpu_dpm_thermal { 1308 /* thermal interrupt work */ 1309 struct work_struct work; 1310 /* low temperature threshold */ 1311 int min_temp; 1312 /* high temperature threshold */ 1313 int max_temp; 1314 /* was last interrupt low to high or high to low */ 1315 bool high_to_low; 1316 /* interrupt source */ 1317 struct amdgpu_irq_src irq; 1318 }; 1319 1320 enum amdgpu_clk_action 1321 { 1322 AMDGPU_SCLK_UP = 1, 1323 AMDGPU_SCLK_DOWN 1324 }; 1325 1326 struct amdgpu_blacklist_clocks 1327 { 1328 u32 sclk; 1329 u32 mclk; 1330 enum amdgpu_clk_action action; 1331 }; 1332 1333 struct amdgpu_clock_and_voltage_limits { 1334 u32 sclk; 1335 u32 mclk; 1336 u16 vddc; 1337 u16 vddci; 1338 }; 1339 1340 struct amdgpu_clock_array { 1341 u32 count; 1342 u32 *values; 1343 }; 1344 1345 struct amdgpu_clock_voltage_dependency_entry { 1346 u32 clk; 1347 u16 v; 1348 }; 1349 1350 struct amdgpu_clock_voltage_dependency_table { 1351 u32 count; 1352 struct amdgpu_clock_voltage_dependency_entry *entries; 1353 }; 1354 1355 union amdgpu_cac_leakage_entry { 1356 struct { 1357 u16 vddc; 1358 u32 leakage; 1359 }; 1360 struct { 1361 u16 vddc1; 1362 u16 vddc2; 1363 u16 vddc3; 1364 }; 1365 }; 1366 1367 struct amdgpu_cac_leakage_table { 1368 u32 count; 1369 union amdgpu_cac_leakage_entry *entries; 1370 }; 1371 1372 struct amdgpu_phase_shedding_limits_entry { 1373 u16 voltage; 1374 u32 sclk; 1375 u32 mclk; 1376 }; 1377 1378 struct amdgpu_phase_shedding_limits_table { 1379 u32 count; 1380 struct amdgpu_phase_shedding_limits_entry *entries; 1381 }; 1382 1383 struct amdgpu_uvd_clock_voltage_dependency_entry { 1384 u32 vclk; 1385 u32 dclk; 1386 u16 v; 1387 }; 1388 1389 struct amdgpu_uvd_clock_voltage_dependency_table { 1390 u8 count; 1391 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1392 }; 1393 1394 struct amdgpu_vce_clock_voltage_dependency_entry { 1395 u32 ecclk; 1396 u32 evclk; 1397 u16 v; 1398 }; 1399 1400 struct amdgpu_vce_clock_voltage_dependency_table { 1401 u8 count; 1402 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1403 }; 1404 1405 struct amdgpu_ppm_table { 1406 u8 ppm_design; 1407 u16 cpu_core_number; 1408 u32 platform_tdp; 1409 u32 small_ac_platform_tdp; 1410 u32 platform_tdc; 1411 u32 small_ac_platform_tdc; 1412 u32 apu_tdp; 1413 u32 dgpu_tdp; 1414 u32 dgpu_ulv_power; 1415 u32 tj_max; 1416 }; 1417 1418 struct amdgpu_cac_tdp_table { 1419 u16 tdp; 1420 u16 configurable_tdp; 1421 u16 tdc; 1422 u16 battery_power_limit; 1423 u16 small_power_limit; 1424 u16 low_cac_leakage; 1425 u16 high_cac_leakage; 1426 u16 maximum_power_delivery_limit; 1427 }; 1428 1429 struct amdgpu_dpm_dynamic_state { 1430 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1431 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1432 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1433 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1434 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1435 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1436 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1437 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1438 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1439 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1440 struct amdgpu_clock_array valid_sclk_values; 1441 struct amdgpu_clock_array valid_mclk_values; 1442 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1443 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1444 u32 mclk_sclk_ratio; 1445 u32 sclk_mclk_delta; 1446 u16 vddc_vddci_delta; 1447 u16 min_vddc_for_pcie_gen2; 1448 struct amdgpu_cac_leakage_table cac_leakage_table; 1449 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1450 struct amdgpu_ppm_table *ppm_table; 1451 struct amdgpu_cac_tdp_table *cac_tdp_table; 1452 }; 1453 1454 struct amdgpu_dpm_fan { 1455 u16 t_min; 1456 u16 t_med; 1457 u16 t_high; 1458 u16 pwm_min; 1459 u16 pwm_med; 1460 u16 pwm_high; 1461 u8 t_hyst; 1462 u32 cycle_delay; 1463 u16 t_max; 1464 u8 control_mode; 1465 u16 default_max_fan_pwm; 1466 u16 default_fan_output_sensitivity; 1467 u16 fan_output_sensitivity; 1468 bool ucode_fan_control; 1469 }; 1470 1471 enum amdgpu_pcie_gen { 1472 AMDGPU_PCIE_GEN1 = 0, 1473 AMDGPU_PCIE_GEN2 = 1, 1474 AMDGPU_PCIE_GEN3 = 2, 1475 AMDGPU_PCIE_GEN_INVALID = 0xffff 1476 }; 1477 1478 enum amdgpu_dpm_forced_level { 1479 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1480 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1481 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1482 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3, 1483 }; 1484 1485 struct amdgpu_vce_state { 1486 /* vce clocks */ 1487 u32 evclk; 1488 u32 ecclk; 1489 /* gpu clocks */ 1490 u32 sclk; 1491 u32 mclk; 1492 u8 clk_idx; 1493 u8 pstate; 1494 }; 1495 1496 struct amdgpu_dpm_funcs { 1497 int (*get_temperature)(struct amdgpu_device *adev); 1498 int (*pre_set_power_state)(struct amdgpu_device *adev); 1499 int (*set_power_state)(struct amdgpu_device *adev); 1500 void (*post_set_power_state)(struct amdgpu_device *adev); 1501 void (*display_configuration_changed)(struct amdgpu_device *adev); 1502 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1503 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1504 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1505 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1506 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1507 bool (*vblank_too_short)(struct amdgpu_device *adev); 1508 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1509 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1510 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1511 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1512 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1513 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1514 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1515 }; 1516 1517 struct amdgpu_dpm { 1518 struct amdgpu_ps *ps; 1519 /* number of valid power states */ 1520 int num_ps; 1521 /* current power state that is active */ 1522 struct amdgpu_ps *current_ps; 1523 /* requested power state */ 1524 struct amdgpu_ps *requested_ps; 1525 /* boot up power state */ 1526 struct amdgpu_ps *boot_ps; 1527 /* default uvd power state */ 1528 struct amdgpu_ps *uvd_ps; 1529 /* vce requirements */ 1530 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1531 enum amdgpu_vce_level vce_level; 1532 enum amd_pm_state_type state; 1533 enum amd_pm_state_type user_state; 1534 u32 platform_caps; 1535 u32 voltage_response_time; 1536 u32 backbias_response_time; 1537 void *priv; 1538 u32 new_active_crtcs; 1539 int new_active_crtc_count; 1540 u32 current_active_crtcs; 1541 int current_active_crtc_count; 1542 struct amdgpu_dpm_dynamic_state dyn_state; 1543 struct amdgpu_dpm_fan fan; 1544 u32 tdp_limit; 1545 u32 near_tdp_limit; 1546 u32 near_tdp_limit_adjusted; 1547 u32 sq_ramping_threshold; 1548 u32 cac_leakage; 1549 u16 tdp_od_limit; 1550 u32 tdp_adjustment; 1551 u16 load_line_slope; 1552 bool power_control; 1553 bool ac_power; 1554 /* special states active */ 1555 bool thermal_active; 1556 bool uvd_active; 1557 bool vce_active; 1558 /* thermal handling */ 1559 struct amdgpu_dpm_thermal thermal; 1560 /* forced levels */ 1561 enum amdgpu_dpm_forced_level forced_level; 1562 }; 1563 1564 struct amdgpu_pm { 1565 struct mutex mutex; 1566 u32 current_sclk; 1567 u32 current_mclk; 1568 u32 default_sclk; 1569 u32 default_mclk; 1570 struct amdgpu_i2c_chan *i2c_bus; 1571 /* internal thermal controller on rv6xx+ */ 1572 enum amdgpu_int_thermal_type int_thermal_type; 1573 struct device *int_hwmon_dev; 1574 /* fan control parameters */ 1575 bool no_fan; 1576 u8 fan_pulses_per_revolution; 1577 u8 fan_min_rpm; 1578 u8 fan_max_rpm; 1579 /* dpm */ 1580 bool dpm_enabled; 1581 bool sysfs_initialized; 1582 struct amdgpu_dpm dpm; 1583 const struct firmware *fw; /* SMC firmware */ 1584 uint32_t fw_version; 1585 const struct amdgpu_dpm_funcs *funcs; 1586 uint32_t pcie_gen_mask; 1587 uint32_t pcie_mlw_mask; 1588 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */ 1589 }; 1590 1591 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1592 1593 /* 1594 * UVD 1595 */ 1596 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1597 #define AMDGPU_MAX_UVD_HANDLES 40 1598 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1599 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1600 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1601 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1602 1603 struct amdgpu_uvd { 1604 struct amdgpu_bo *vcpu_bo; 1605 void *cpu_addr; 1606 uint64_t gpu_addr; 1607 void *saved_bo; 1608 unsigned max_handles; 1609 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1610 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1611 struct delayed_work idle_work; 1612 const struct firmware *fw; /* UVD firmware */ 1613 struct amdgpu_ring ring; 1614 struct amdgpu_irq_src irq; 1615 bool address_64_bit; 1616 struct amd_sched_entity entity; 1617 }; 1618 1619 /* 1620 * VCE 1621 */ 1622 #define AMDGPU_MAX_VCE_HANDLES 16 1623 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1624 1625 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1626 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1627 1628 struct amdgpu_vce { 1629 struct amdgpu_bo *vcpu_bo; 1630 uint64_t gpu_addr; 1631 unsigned fw_version; 1632 unsigned fb_version; 1633 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1634 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1635 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1636 struct delayed_work idle_work; 1637 const struct firmware *fw; /* VCE firmware */ 1638 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1639 struct amdgpu_irq_src irq; 1640 unsigned harvest_config; 1641 struct amd_sched_entity entity; 1642 }; 1643 1644 /* 1645 * SDMA 1646 */ 1647 struct amdgpu_sdma_instance { 1648 /* SDMA firmware */ 1649 const struct firmware *fw; 1650 uint32_t fw_version; 1651 uint32_t feature_version; 1652 1653 struct amdgpu_ring ring; 1654 bool burst_nop; 1655 }; 1656 1657 struct amdgpu_sdma { 1658 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1659 struct amdgpu_irq_src trap_irq; 1660 struct amdgpu_irq_src illegal_inst_irq; 1661 int num_instances; 1662 }; 1663 1664 /* 1665 * Firmware 1666 */ 1667 struct amdgpu_firmware { 1668 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1669 bool smu_load; 1670 struct amdgpu_bo *fw_buf; 1671 unsigned int fw_size; 1672 }; 1673 1674 /* 1675 * Benchmarking 1676 */ 1677 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1678 1679 1680 /* 1681 * Testing 1682 */ 1683 void amdgpu_test_moves(struct amdgpu_device *adev); 1684 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1685 struct amdgpu_ring *cpA, 1686 struct amdgpu_ring *cpB); 1687 void amdgpu_test_syncing(struct amdgpu_device *adev); 1688 1689 /* 1690 * MMU Notifier 1691 */ 1692 #if defined(CONFIG_MMU_NOTIFIER) 1693 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1694 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1695 #else 1696 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1697 { 1698 return -ENODEV; 1699 } 1700 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1701 #endif 1702 1703 /* 1704 * Debugfs 1705 */ 1706 struct amdgpu_debugfs { 1707 const struct drm_info_list *files; 1708 unsigned num_files; 1709 }; 1710 1711 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1712 const struct drm_info_list *files, 1713 unsigned nfiles); 1714 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1715 1716 #if defined(CONFIG_DEBUG_FS) 1717 int amdgpu_debugfs_init(struct drm_minor *minor); 1718 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1719 #endif 1720 1721 /* 1722 * amdgpu smumgr functions 1723 */ 1724 struct amdgpu_smumgr_funcs { 1725 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1726 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1727 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1728 }; 1729 1730 /* 1731 * amdgpu smumgr 1732 */ 1733 struct amdgpu_smumgr { 1734 struct amdgpu_bo *toc_buf; 1735 struct amdgpu_bo *smu_buf; 1736 /* asic priv smu data */ 1737 void *priv; 1738 spinlock_t smu_lock; 1739 /* smumgr functions */ 1740 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1741 /* ucode loading complete flag */ 1742 uint32_t fw_flags; 1743 }; 1744 1745 /* 1746 * ASIC specific register table accessible by UMD 1747 */ 1748 struct amdgpu_allowed_register_entry { 1749 uint32_t reg_offset; 1750 bool untouched; 1751 bool grbm_indexed; 1752 }; 1753 1754 struct amdgpu_cu_info { 1755 uint32_t number; /* total active CU number */ 1756 uint32_t ao_cu_mask; 1757 uint32_t bitmap[4][4]; 1758 }; 1759 1760 1761 /* 1762 * ASIC specific functions. 1763 */ 1764 struct amdgpu_asic_funcs { 1765 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1766 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1767 u8 *bios, u32 length_bytes); 1768 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1769 u32 sh_num, u32 reg_offset, u32 *value); 1770 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1771 int (*reset)(struct amdgpu_device *adev); 1772 /* wait for mc_idle */ 1773 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1774 /* get the reference clock */ 1775 u32 (*get_xclk)(struct amdgpu_device *adev); 1776 /* get the gpu clock counter */ 1777 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1778 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1779 /* MM block clocks */ 1780 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1781 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1782 }; 1783 1784 /* 1785 * IOCTL. 1786 */ 1787 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1788 struct drm_file *filp); 1789 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1790 struct drm_file *filp); 1791 1792 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1793 struct drm_file *filp); 1794 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1795 struct drm_file *filp); 1796 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1797 struct drm_file *filp); 1798 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1799 struct drm_file *filp); 1800 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1801 struct drm_file *filp); 1802 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1803 struct drm_file *filp); 1804 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1805 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1806 1807 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1808 struct drm_file *filp); 1809 1810 /* VRAM scratch page for HDP bug, default vram page */ 1811 struct amdgpu_vram_scratch { 1812 struct amdgpu_bo *robj; 1813 volatile uint32_t *ptr; 1814 u64 gpu_addr; 1815 }; 1816 1817 /* 1818 * ACPI 1819 */ 1820 struct amdgpu_atif_notification_cfg { 1821 bool enabled; 1822 int command_code; 1823 }; 1824 1825 struct amdgpu_atif_notifications { 1826 bool display_switch; 1827 bool expansion_mode_change; 1828 bool thermal_state; 1829 bool forced_power_state; 1830 bool system_power_state; 1831 bool display_conf_change; 1832 bool px_gfx_switch; 1833 bool brightness_change; 1834 bool dgpu_display_event; 1835 }; 1836 1837 struct amdgpu_atif_functions { 1838 bool system_params; 1839 bool sbios_requests; 1840 bool select_active_disp; 1841 bool lid_state; 1842 bool get_tv_standard; 1843 bool set_tv_standard; 1844 bool get_panel_expansion_mode; 1845 bool set_panel_expansion_mode; 1846 bool temperature_change; 1847 bool graphics_device_types; 1848 }; 1849 1850 struct amdgpu_atif { 1851 struct amdgpu_atif_notifications notifications; 1852 struct amdgpu_atif_functions functions; 1853 struct amdgpu_atif_notification_cfg notification_cfg; 1854 struct amdgpu_encoder *encoder_for_bl; 1855 }; 1856 1857 struct amdgpu_atcs_functions { 1858 bool get_ext_state; 1859 bool pcie_perf_req; 1860 bool pcie_dev_rdy; 1861 bool pcie_bus_width; 1862 }; 1863 1864 struct amdgpu_atcs { 1865 struct amdgpu_atcs_functions functions; 1866 }; 1867 1868 /* 1869 * CGS 1870 */ 1871 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1872 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1873 1874 1875 /* GPU virtualization */ 1876 struct amdgpu_virtualization { 1877 bool supports_sr_iov; 1878 }; 1879 1880 /* 1881 * Core structure, functions and helpers. 1882 */ 1883 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1884 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1885 1886 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1887 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1888 1889 struct amdgpu_ip_block_status { 1890 bool valid; 1891 bool sw; 1892 bool hw; 1893 }; 1894 1895 struct amdgpu_device { 1896 struct device *dev; 1897 struct drm_device *ddev; 1898 struct pci_dev *pdev; 1899 1900 #ifdef CONFIG_DRM_AMD_ACP 1901 struct amdgpu_acp acp; 1902 #endif 1903 1904 /* ASIC */ 1905 enum amd_asic_type asic_type; 1906 uint32_t family; 1907 uint32_t rev_id; 1908 uint32_t external_rev_id; 1909 unsigned long flags; 1910 int usec_timeout; 1911 const struct amdgpu_asic_funcs *asic_funcs; 1912 bool shutdown; 1913 bool need_dma32; 1914 bool accel_working; 1915 struct work_struct reset_work; 1916 struct notifier_block acpi_nb; 1917 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1918 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1919 unsigned debugfs_count; 1920 #if defined(CONFIG_DEBUG_FS) 1921 struct dentry *debugfs_regs; 1922 #endif 1923 struct amdgpu_atif atif; 1924 struct amdgpu_atcs atcs; 1925 struct mutex srbm_mutex; 1926 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1927 struct mutex grbm_idx_mutex; 1928 struct dev_pm_domain vga_pm_domain; 1929 bool have_disp_power_ref; 1930 1931 /* BIOS */ 1932 uint8_t *bios; 1933 bool is_atom_bios; 1934 struct amdgpu_bo *stollen_vga_memory; 1935 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1936 1937 /* Register/doorbell mmio */ 1938 resource_size_t rmmio_base; 1939 resource_size_t rmmio_size; 1940 void __iomem *rmmio; 1941 /* protects concurrent MM_INDEX/DATA based register access */ 1942 spinlock_t mmio_idx_lock; 1943 /* protects concurrent SMC based register access */ 1944 spinlock_t smc_idx_lock; 1945 amdgpu_rreg_t smc_rreg; 1946 amdgpu_wreg_t smc_wreg; 1947 /* protects concurrent PCIE register access */ 1948 spinlock_t pcie_idx_lock; 1949 amdgpu_rreg_t pcie_rreg; 1950 amdgpu_wreg_t pcie_wreg; 1951 /* protects concurrent UVD register access */ 1952 spinlock_t uvd_ctx_idx_lock; 1953 amdgpu_rreg_t uvd_ctx_rreg; 1954 amdgpu_wreg_t uvd_ctx_wreg; 1955 /* protects concurrent DIDT register access */ 1956 spinlock_t didt_idx_lock; 1957 amdgpu_rreg_t didt_rreg; 1958 amdgpu_wreg_t didt_wreg; 1959 /* protects concurrent ENDPOINT (audio) register access */ 1960 spinlock_t audio_endpt_idx_lock; 1961 amdgpu_block_rreg_t audio_endpt_rreg; 1962 amdgpu_block_wreg_t audio_endpt_wreg; 1963 void __iomem *rio_mem; 1964 resource_size_t rio_mem_size; 1965 struct amdgpu_doorbell doorbell; 1966 1967 /* clock/pll info */ 1968 struct amdgpu_clock clock; 1969 1970 /* MC */ 1971 struct amdgpu_mc mc; 1972 struct amdgpu_gart gart; 1973 struct amdgpu_dummy_page dummy_page; 1974 struct amdgpu_vm_manager vm_manager; 1975 1976 /* memory management */ 1977 struct amdgpu_mman mman; 1978 struct amdgpu_vram_scratch vram_scratch; 1979 struct amdgpu_wb wb; 1980 atomic64_t vram_usage; 1981 atomic64_t vram_vis_usage; 1982 atomic64_t gtt_usage; 1983 atomic64_t num_bytes_moved; 1984 atomic_t gpu_reset_counter; 1985 1986 /* display */ 1987 struct amdgpu_mode_info mode_info; 1988 struct work_struct hotplug_work; 1989 struct amdgpu_irq_src crtc_irq; 1990 struct amdgpu_irq_src pageflip_irq; 1991 struct amdgpu_irq_src hpd_irq; 1992 1993 /* rings */ 1994 unsigned fence_context; 1995 unsigned num_rings; 1996 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1997 bool ib_pool_ready; 1998 struct amdgpu_sa_manager ring_tmp_bo; 1999 2000 /* interrupts */ 2001 struct amdgpu_irq irq; 2002 2003 /* powerplay */ 2004 struct amd_powerplay powerplay; 2005 bool pp_enabled; 2006 bool pp_force_state_enabled; 2007 2008 /* dpm */ 2009 struct amdgpu_pm pm; 2010 u32 cg_flags; 2011 u32 pg_flags; 2012 2013 /* amdgpu smumgr */ 2014 struct amdgpu_smumgr smu; 2015 2016 /* gfx */ 2017 struct amdgpu_gfx gfx; 2018 2019 /* sdma */ 2020 struct amdgpu_sdma sdma; 2021 2022 /* uvd */ 2023 struct amdgpu_uvd uvd; 2024 2025 /* vce */ 2026 struct amdgpu_vce vce; 2027 2028 /* firmwares */ 2029 struct amdgpu_firmware firmware; 2030 2031 /* GDS */ 2032 struct amdgpu_gds gds; 2033 2034 const struct amdgpu_ip_block_version *ip_blocks; 2035 int num_ip_blocks; 2036 struct amdgpu_ip_block_status *ip_block_status; 2037 struct mutex mn_lock; 2038 DECLARE_HASHTABLE(mn_hash, 7); 2039 2040 /* tracking pinned memory */ 2041 u64 vram_pin_size; 2042 u64 gart_pin_size; 2043 2044 /* amdkfd interface */ 2045 struct kfd_dev *kfd; 2046 2047 struct amdgpu_virtualization virtualization; 2048 }; 2049 2050 bool amdgpu_device_is_px(struct drm_device *dev); 2051 int amdgpu_device_init(struct amdgpu_device *adev, 2052 struct drm_device *ddev, 2053 struct pci_dev *pdev, 2054 uint32_t flags); 2055 void amdgpu_device_fini(struct amdgpu_device *adev); 2056 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2057 2058 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2059 bool always_indirect); 2060 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2061 bool always_indirect); 2062 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2063 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2064 2065 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2066 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2067 2068 /* 2069 * Registers read & write functions. 2070 */ 2071 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2072 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2073 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2074 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2075 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2076 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2077 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2078 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2079 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2080 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2081 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2082 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2084 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2085 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2086 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2087 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2088 #define WREG32_P(reg, val, mask) \ 2089 do { \ 2090 uint32_t tmp_ = RREG32(reg); \ 2091 tmp_ &= (mask); \ 2092 tmp_ |= ((val) & ~(mask)); \ 2093 WREG32(reg, tmp_); \ 2094 } while (0) 2095 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2096 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2097 #define WREG32_PLL_P(reg, val, mask) \ 2098 do { \ 2099 uint32_t tmp_ = RREG32_PLL(reg); \ 2100 tmp_ &= (mask); \ 2101 tmp_ |= ((val) & ~(mask)); \ 2102 WREG32_PLL(reg, tmp_); \ 2103 } while (0) 2104 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2105 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2106 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2107 2108 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2109 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2110 2111 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2112 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2113 2114 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2115 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2116 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2117 2118 #define REG_GET_FIELD(value, reg, field) \ 2119 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2120 2121 /* 2122 * BIOS helpers. 2123 */ 2124 #define RBIOS8(i) (adev->bios[i]) 2125 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2126 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2127 2128 /* 2129 * RING helpers. 2130 */ 2131 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2132 { 2133 if (ring->count_dw <= 0) 2134 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2135 ring->ring[ring->wptr++] = v; 2136 ring->wptr &= ring->ptr_mask; 2137 ring->count_dw--; 2138 } 2139 2140 static inline struct amdgpu_sdma_instance * 2141 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2142 { 2143 struct amdgpu_device *adev = ring->adev; 2144 int i; 2145 2146 for (i = 0; i < adev->sdma.num_instances; i++) 2147 if (&adev->sdma.instance[i].ring == ring) 2148 break; 2149 2150 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2151 return &adev->sdma.instance[i]; 2152 else 2153 return NULL; 2154 } 2155 2156 /* 2157 * ASICs macro. 2158 */ 2159 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2160 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2161 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2162 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2163 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2164 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2165 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2166 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2167 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 2168 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2169 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2170 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2171 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2172 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2173 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags))) 2174 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2175 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2176 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2177 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2178 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2179 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2180 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2181 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2182 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 2183 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2184 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2185 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2186 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2187 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 2188 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 2189 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 2190 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 2191 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2192 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2193 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2194 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2195 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2196 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2197 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2198 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2199 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2200 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2201 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2202 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2203 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2204 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2205 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2206 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2207 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2208 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2209 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2210 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2211 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2212 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2213 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2214 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2215 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2216 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2217 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2218 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2219 2220 #define amdgpu_dpm_get_temperature(adev) \ 2221 ((adev)->pp_enabled ? \ 2222 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \ 2223 (adev)->pm.funcs->get_temperature((adev))) 2224 2225 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 2226 ((adev)->pp_enabled ? \ 2227 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \ 2228 (adev)->pm.funcs->set_fan_control_mode((adev), (m))) 2229 2230 #define amdgpu_dpm_get_fan_control_mode(adev) \ 2231 ((adev)->pp_enabled ? \ 2232 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \ 2233 (adev)->pm.funcs->get_fan_control_mode((adev))) 2234 2235 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 2236 ((adev)->pp_enabled ? \ 2237 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2238 (adev)->pm.funcs->set_fan_speed_percent((adev), (s))) 2239 2240 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 2241 ((adev)->pp_enabled ? \ 2242 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \ 2243 (adev)->pm.funcs->get_fan_speed_percent((adev), (s))) 2244 2245 #define amdgpu_dpm_get_sclk(adev, l) \ 2246 ((adev)->pp_enabled ? \ 2247 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \ 2248 (adev)->pm.funcs->get_sclk((adev), (l))) 2249 2250 #define amdgpu_dpm_get_mclk(adev, l) \ 2251 ((adev)->pp_enabled ? \ 2252 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \ 2253 (adev)->pm.funcs->get_mclk((adev), (l))) 2254 2255 2256 #define amdgpu_dpm_force_performance_level(adev, l) \ 2257 ((adev)->pp_enabled ? \ 2258 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \ 2259 (adev)->pm.funcs->force_performance_level((adev), (l))) 2260 2261 #define amdgpu_dpm_powergate_uvd(adev, g) \ 2262 ((adev)->pp_enabled ? \ 2263 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \ 2264 (adev)->pm.funcs->powergate_uvd((adev), (g))) 2265 2266 #define amdgpu_dpm_powergate_vce(adev, g) \ 2267 ((adev)->pp_enabled ? \ 2268 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \ 2269 (adev)->pm.funcs->powergate_vce((adev), (g))) 2270 2271 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \ 2272 ((adev)->pp_enabled ? \ 2273 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \ 2274 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))) 2275 2276 #define amdgpu_dpm_get_current_power_state(adev) \ 2277 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle) 2278 2279 #define amdgpu_dpm_get_performance_level(adev) \ 2280 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) 2281 2282 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 2283 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data) 2284 2285 #define amdgpu_dpm_get_pp_table(adev, table) \ 2286 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table) 2287 2288 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 2289 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size) 2290 2291 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 2292 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf) 2293 2294 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 2295 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level) 2296 2297 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \ 2298 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output)) 2299 2300 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2301 2302 /* Common functions */ 2303 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2304 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2305 bool amdgpu_card_posted(struct amdgpu_device *adev); 2306 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2307 2308 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2309 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2310 u32 ip_instance, u32 ring, 2311 struct amdgpu_ring **out_ring); 2312 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2313 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2314 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 2315 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2316 uint32_t flags); 2317 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2318 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 2319 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2320 unsigned long end); 2321 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 2322 int *last_invalidated); 2323 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2324 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2325 struct ttm_mem_reg *mem); 2326 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2327 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2328 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2329 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2330 const u32 *registers, 2331 const u32 array_size); 2332 2333 bool amdgpu_device_is_px(struct drm_device *dev); 2334 /* atpx handler */ 2335 #if defined(CONFIG_VGA_SWITCHEROO) 2336 void amdgpu_register_atpx_handler(void); 2337 void amdgpu_unregister_atpx_handler(void); 2338 #else 2339 static inline void amdgpu_register_atpx_handler(void) {} 2340 static inline void amdgpu_unregister_atpx_handler(void) {} 2341 #endif 2342 2343 /* 2344 * KMS 2345 */ 2346 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2347 extern const int amdgpu_max_kms_ioctl; 2348 2349 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2350 int amdgpu_driver_unload_kms(struct drm_device *dev); 2351 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2352 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2353 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2354 struct drm_file *file_priv); 2355 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2356 struct drm_file *file_priv); 2357 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2358 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2359 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2360 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2361 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2362 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2363 int *max_error, 2364 struct timeval *vblank_time, 2365 unsigned flags); 2366 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2367 unsigned long arg); 2368 2369 /* 2370 * functions used by amdgpu_encoder.c 2371 */ 2372 struct amdgpu_afmt_acr { 2373 u32 clock; 2374 2375 int n_32khz; 2376 int cts_32khz; 2377 2378 int n_44_1khz; 2379 int cts_44_1khz; 2380 2381 int n_48khz; 2382 int cts_48khz; 2383 2384 }; 2385 2386 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2387 2388 /* amdgpu_acpi.c */ 2389 #if defined(CONFIG_ACPI) 2390 int amdgpu_acpi_init(struct amdgpu_device *adev); 2391 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2392 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2393 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2394 u8 perf_req, bool advertise); 2395 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2396 #else 2397 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2398 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2399 #endif 2400 2401 struct amdgpu_bo_va_mapping * 2402 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2403 uint64_t addr, struct amdgpu_bo **bo); 2404 2405 #include "amdgpu_object.h" 2406 #endif 2407