1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_aca.h" 111 #include "amdgpu_ras.h" 112 #include "amdgpu_xcp.h" 113 #include "amdgpu_seq64.h" 114 #include "amdgpu_reg_state.h" 115 116 #define MAX_GPU_INSTANCE 64 117 118 struct amdgpu_gpu_instance { 119 struct amdgpu_device *adev; 120 int mgpu_fan_enabled; 121 }; 122 123 struct amdgpu_mgpu_info { 124 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 125 struct mutex mutex; 126 uint32_t num_gpu; 127 uint32_t num_dgpu; 128 uint32_t num_apu; 129 130 /* delayed reset_func for XGMI configuration if necessary */ 131 struct delayed_work delayed_reset_work; 132 bool pending_reset; 133 }; 134 135 enum amdgpu_ss { 136 AMDGPU_SS_DRV_LOAD, 137 AMDGPU_SS_DEV_D0, 138 AMDGPU_SS_DEV_D3, 139 AMDGPU_SS_DRV_UNLOAD 140 }; 141 142 struct amdgpu_hwip_reg_entry { 143 u32 hwip; 144 u32 inst; 145 u32 seg; 146 u32 reg_offset; 147 const char *reg_name; 148 }; 149 150 struct amdgpu_watchdog_timer { 151 bool timeout_fatal_disable; 152 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 153 }; 154 155 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 156 157 /* 158 * Modules parameters. 159 */ 160 extern int amdgpu_modeset; 161 extern unsigned int amdgpu_vram_limit; 162 extern int amdgpu_vis_vram_limit; 163 extern int amdgpu_gart_size; 164 extern int amdgpu_gtt_size; 165 extern int amdgpu_moverate; 166 extern int amdgpu_audio; 167 extern int amdgpu_disp_priority; 168 extern int amdgpu_hw_i2c; 169 extern int amdgpu_pcie_gen2; 170 extern int amdgpu_msi; 171 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 172 extern int amdgpu_dpm; 173 extern int amdgpu_fw_load_type; 174 extern int amdgpu_aspm; 175 extern int amdgpu_runtime_pm; 176 extern uint amdgpu_ip_block_mask; 177 extern int amdgpu_bapm; 178 extern int amdgpu_deep_color; 179 extern int amdgpu_vm_size; 180 extern int amdgpu_vm_block_size; 181 extern int amdgpu_vm_fragment_size; 182 extern int amdgpu_vm_fault_stop; 183 extern int amdgpu_vm_debug; 184 extern int amdgpu_vm_update_mode; 185 extern int amdgpu_exp_hw_support; 186 extern int amdgpu_dc; 187 extern int amdgpu_sched_jobs; 188 extern int amdgpu_sched_hw_submission; 189 extern uint amdgpu_pcie_gen_cap; 190 extern uint amdgpu_pcie_lane_cap; 191 extern u64 amdgpu_cg_mask; 192 extern uint amdgpu_pg_mask; 193 extern uint amdgpu_sdma_phase_quantum; 194 extern char *amdgpu_disable_cu; 195 extern char *amdgpu_virtual_display; 196 extern uint amdgpu_pp_feature_mask; 197 extern uint amdgpu_force_long_training; 198 extern int amdgpu_lbpw; 199 extern int amdgpu_compute_multipipe; 200 extern int amdgpu_gpu_recovery; 201 extern int amdgpu_emu_mode; 202 extern uint amdgpu_smu_memory_pool_size; 203 extern int amdgpu_smu_pptable_id; 204 extern uint amdgpu_dc_feature_mask; 205 extern uint amdgpu_freesync_vid_mode; 206 extern uint amdgpu_dc_debug_mask; 207 extern uint amdgpu_dc_visual_confirm; 208 extern int amdgpu_dm_abm_level; 209 extern int amdgpu_backlight; 210 extern int amdgpu_damage_clips; 211 extern struct amdgpu_mgpu_info mgpu_info; 212 extern int amdgpu_ras_enable; 213 extern uint amdgpu_ras_mask; 214 extern int amdgpu_bad_page_threshold; 215 extern bool amdgpu_ignore_bad_page_threshold; 216 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 217 extern int amdgpu_async_gfx_ring; 218 extern int amdgpu_mcbp; 219 extern int amdgpu_discovery; 220 extern int amdgpu_mes; 221 extern int amdgpu_mes_log_enable; 222 extern int amdgpu_mes_kiq; 223 extern int amdgpu_uni_mes; 224 extern int amdgpu_noretry; 225 extern int amdgpu_force_asic_type; 226 extern int amdgpu_smartshift_bias; 227 extern int amdgpu_use_xgmi_p2p; 228 extern int amdgpu_mtype_local; 229 extern bool enforce_isolation; 230 #ifdef CONFIG_HSA_AMD 231 extern int sched_policy; 232 extern bool debug_evictions; 233 extern bool no_system_mem_limit; 234 extern int halt_if_hws_hang; 235 #else 236 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 237 static const bool __maybe_unused debug_evictions; /* = false */ 238 static const bool __maybe_unused no_system_mem_limit; 239 static const int __maybe_unused halt_if_hws_hang; 240 #endif 241 #ifdef CONFIG_HSA_AMD_P2P 242 extern bool pcie_p2p; 243 #endif 244 245 extern int amdgpu_tmz; 246 extern int amdgpu_reset_method; 247 248 #ifdef CONFIG_DRM_AMDGPU_SI 249 extern int amdgpu_si_support; 250 #endif 251 #ifdef CONFIG_DRM_AMDGPU_CIK 252 extern int amdgpu_cik_support; 253 #endif 254 extern int amdgpu_num_kcq; 255 256 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 257 extern int amdgpu_vcnfw_log; 258 extern int amdgpu_sg_display; 259 extern int amdgpu_umsch_mm; 260 extern int amdgpu_seamless; 261 262 extern int amdgpu_user_partt_mode; 263 extern int amdgpu_agp; 264 265 extern int amdgpu_wbrf; 266 267 #define AMDGPU_VM_MAX_NUM_CTX 4096 268 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 269 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 270 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 271 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 272 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 273 #define AMDGPUFB_CONN_LIMIT 4 274 #define AMDGPU_BIOS_NUM_SCRATCH 16 275 276 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 277 278 /* hard reset data */ 279 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 280 281 /* reset flags */ 282 #define AMDGPU_RESET_GFX (1 << 0) 283 #define AMDGPU_RESET_COMPUTE (1 << 1) 284 #define AMDGPU_RESET_DMA (1 << 2) 285 #define AMDGPU_RESET_CP (1 << 3) 286 #define AMDGPU_RESET_GRBM (1 << 4) 287 #define AMDGPU_RESET_DMA1 (1 << 5) 288 #define AMDGPU_RESET_RLC (1 << 6) 289 #define AMDGPU_RESET_SEM (1 << 7) 290 #define AMDGPU_RESET_IH (1 << 8) 291 #define AMDGPU_RESET_VMC (1 << 9) 292 #define AMDGPU_RESET_MC (1 << 10) 293 #define AMDGPU_RESET_DISPLAY (1 << 11) 294 #define AMDGPU_RESET_UVD (1 << 12) 295 #define AMDGPU_RESET_VCE (1 << 13) 296 #define AMDGPU_RESET_VCE1 (1 << 14) 297 298 /* max cursor sizes (in pixels) */ 299 #define CIK_CURSOR_WIDTH 128 300 #define CIK_CURSOR_HEIGHT 128 301 302 /* smart shift bias level limits */ 303 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 304 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 305 306 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 307 #define AMDGPU_SWCTF_EXTRA_DELAY 50 308 309 struct amdgpu_xcp_mgr; 310 struct amdgpu_device; 311 struct amdgpu_irq_src; 312 struct amdgpu_fpriv; 313 struct amdgpu_bo_va_mapping; 314 struct kfd_vm_fault_info; 315 struct amdgpu_hive_info; 316 struct amdgpu_reset_context; 317 struct amdgpu_reset_control; 318 319 enum amdgpu_cp_irq { 320 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 321 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 322 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 323 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 324 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 325 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 326 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 327 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 328 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 329 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 330 331 AMDGPU_CP_IRQ_LAST 332 }; 333 334 enum amdgpu_thermal_irq { 335 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 336 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 337 338 AMDGPU_THERMAL_IRQ_LAST 339 }; 340 341 enum amdgpu_kiq_irq { 342 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 343 AMDGPU_CP_KIQ_IRQ_LAST 344 }; 345 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 346 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 347 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 348 #define MAX_KIQ_REG_TRY 1000 349 350 int amdgpu_device_ip_set_clockgating_state(void *dev, 351 enum amd_ip_block_type block_type, 352 enum amd_clockgating_state state); 353 int amdgpu_device_ip_set_powergating_state(void *dev, 354 enum amd_ip_block_type block_type, 355 enum amd_powergating_state state); 356 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 357 u64 *flags); 358 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 359 enum amd_ip_block_type block_type); 360 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 361 enum amd_ip_block_type block_type); 362 363 #define AMDGPU_MAX_IP_NUM 16 364 365 struct amdgpu_ip_block_status { 366 bool valid; 367 bool sw; 368 bool hw; 369 bool late_initialized; 370 bool hang; 371 }; 372 373 struct amdgpu_ip_block_version { 374 const enum amd_ip_block_type type; 375 const u32 major; 376 const u32 minor; 377 const u32 rev; 378 const struct amd_ip_funcs *funcs; 379 }; 380 381 struct amdgpu_ip_block { 382 struct amdgpu_ip_block_status status; 383 const struct amdgpu_ip_block_version *version; 384 }; 385 386 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 387 enum amd_ip_block_type type, 388 u32 major, u32 minor); 389 390 struct amdgpu_ip_block * 391 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 392 enum amd_ip_block_type type); 393 394 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 395 const struct amdgpu_ip_block_version *ip_block_version); 396 397 /* 398 * BIOS. 399 */ 400 bool amdgpu_get_bios(struct amdgpu_device *adev); 401 bool amdgpu_read_bios(struct amdgpu_device *adev); 402 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 403 u8 *bios, u32 length_bytes); 404 /* 405 * Clocks 406 */ 407 408 #define AMDGPU_MAX_PPLL 3 409 410 struct amdgpu_clock { 411 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 412 struct amdgpu_pll spll; 413 struct amdgpu_pll mpll; 414 /* 10 Khz units */ 415 uint32_t default_mclk; 416 uint32_t default_sclk; 417 uint32_t default_dispclk; 418 uint32_t current_dispclk; 419 uint32_t dp_extclk; 420 uint32_t max_pixel_clock; 421 }; 422 423 /* sub-allocation manager, it has to be protected by another lock. 424 * By conception this is an helper for other part of the driver 425 * like the indirect buffer or semaphore, which both have their 426 * locking. 427 * 428 * Principe is simple, we keep a list of sub allocation in offset 429 * order (first entry has offset == 0, last entry has the highest 430 * offset). 431 * 432 * When allocating new object we first check if there is room at 433 * the end total_size - (last_object_offset + last_object_size) >= 434 * alloc_size. If so we allocate new object there. 435 * 436 * When there is not enough room at the end, we start waiting for 437 * each sub object until we reach object_offset+object_size >= 438 * alloc_size, this object then become the sub object we return. 439 * 440 * Alignment can't be bigger than page size. 441 * 442 * Hole are not considered for allocation to keep things simple. 443 * Assumption is that there won't be hole (all object on same 444 * alignment). 445 */ 446 447 struct amdgpu_sa_manager { 448 struct drm_suballoc_manager base; 449 struct amdgpu_bo *bo; 450 uint64_t gpu_addr; 451 void *cpu_ptr; 452 }; 453 454 int amdgpu_fence_slab_init(void); 455 void amdgpu_fence_slab_fini(void); 456 457 /* 458 * IRQS. 459 */ 460 461 struct amdgpu_flip_work { 462 struct delayed_work flip_work; 463 struct work_struct unpin_work; 464 struct amdgpu_device *adev; 465 int crtc_id; 466 u32 target_vblank; 467 uint64_t base; 468 struct drm_pending_vblank_event *event; 469 struct amdgpu_bo *old_abo; 470 unsigned shared_count; 471 struct dma_fence **shared; 472 struct dma_fence_cb cb; 473 bool async; 474 }; 475 476 477 /* 478 * file private structure 479 */ 480 481 struct amdgpu_fpriv { 482 struct amdgpu_vm vm; 483 struct amdgpu_bo_va *prt_va; 484 struct amdgpu_bo_va *csa_va; 485 struct amdgpu_bo_va *seq64_va; 486 struct mutex bo_list_lock; 487 struct idr bo_list_handles; 488 struct amdgpu_ctx_mgr ctx_mgr; 489 /** GPU partition selection */ 490 uint32_t xcp_id; 491 }; 492 493 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 494 495 /* 496 * Writeback 497 */ 498 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 499 500 struct amdgpu_wb { 501 struct amdgpu_bo *wb_obj; 502 volatile uint32_t *wb; 503 uint64_t gpu_addr; 504 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 505 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 506 spinlock_t lock; 507 }; 508 509 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 510 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 511 512 /* 513 * Benchmarking 514 */ 515 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 516 517 /* 518 * ASIC specific register table accessible by UMD 519 */ 520 struct amdgpu_allowed_register_entry { 521 uint32_t reg_offset; 522 bool grbm_indexed; 523 }; 524 525 /** 526 * enum amd_reset_method - Methods for resetting AMD GPU devices 527 * 528 * @AMD_RESET_METHOD_NONE: The device will not be reset. 529 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 530 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 531 * any device. 532 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 533 * individually. Suitable only for some discrete GPU, not 534 * available for all ASICs. 535 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 536 * are reset depends on the ASIC. Notably doesn't reset IPs 537 * shared with the CPU on APUs or the memory controllers (so 538 * VRAM is not lost). Not available on all ASICs. 539 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 540 * but without powering off the PCI bus. Suitable only for 541 * discrete GPUs. 542 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 543 * and does a secondary bus reset or FLR, depending on what the 544 * underlying hardware supports. 545 * 546 * Methods available for AMD GPU driver for resetting the device. Not all 547 * methods are suitable for every device. User can override the method using 548 * module parameter `reset_method`. 549 */ 550 enum amd_reset_method { 551 AMD_RESET_METHOD_NONE = -1, 552 AMD_RESET_METHOD_LEGACY = 0, 553 AMD_RESET_METHOD_MODE0, 554 AMD_RESET_METHOD_MODE1, 555 AMD_RESET_METHOD_MODE2, 556 AMD_RESET_METHOD_BACO, 557 AMD_RESET_METHOD_PCI, 558 }; 559 560 struct amdgpu_video_codec_info { 561 u32 codec_type; 562 u32 max_width; 563 u32 max_height; 564 u32 max_pixels_per_frame; 565 u32 max_level; 566 }; 567 568 #define codec_info_build(type, width, height, level) \ 569 .codec_type = type,\ 570 .max_width = width,\ 571 .max_height = height,\ 572 .max_pixels_per_frame = height * width,\ 573 .max_level = level, 574 575 struct amdgpu_video_codecs { 576 const u32 codec_count; 577 const struct amdgpu_video_codec_info *codec_array; 578 }; 579 580 /* 581 * ASIC specific functions. 582 */ 583 struct amdgpu_asic_funcs { 584 bool (*read_disabled_bios)(struct amdgpu_device *adev); 585 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 586 u8 *bios, u32 length_bytes); 587 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 588 u32 sh_num, u32 reg_offset, u32 *value); 589 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 590 int (*reset)(struct amdgpu_device *adev); 591 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 592 /* get the reference clock */ 593 u32 (*get_xclk)(struct amdgpu_device *adev); 594 /* MM block clocks */ 595 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 596 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 597 /* static power management */ 598 int (*get_pcie_lanes)(struct amdgpu_device *adev); 599 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 600 /* get config memsize register */ 601 u32 (*get_config_memsize)(struct amdgpu_device *adev); 602 /* flush hdp write queue */ 603 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 604 /* invalidate hdp read cache */ 605 void (*invalidate_hdp)(struct amdgpu_device *adev, 606 struct amdgpu_ring *ring); 607 /* check if the asic needs a full reset of if soft reset will work */ 608 bool (*need_full_reset)(struct amdgpu_device *adev); 609 /* initialize doorbell layout for specific asic*/ 610 void (*init_doorbell_index)(struct amdgpu_device *adev); 611 /* PCIe bandwidth usage */ 612 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 613 uint64_t *count1); 614 /* do we need to reset the asic at init time (e.g., kexec) */ 615 bool (*need_reset_on_init)(struct amdgpu_device *adev); 616 /* PCIe replay counter */ 617 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 618 /* device supports BACO */ 619 int (*supports_baco)(struct amdgpu_device *adev); 620 /* pre asic_init quirks */ 621 void (*pre_asic_init)(struct amdgpu_device *adev); 622 /* enter/exit umd stable pstate */ 623 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 624 /* query video codecs */ 625 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 626 const struct amdgpu_video_codecs **codecs); 627 /* encode "> 32bits" smn addressing */ 628 u64 (*encode_ext_smn_addressing)(int ext_id); 629 630 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 631 enum amdgpu_reg_state reg_state, void *buf, 632 size_t max_size); 633 }; 634 635 /* 636 * IOCTL. 637 */ 638 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 639 struct drm_file *filp); 640 641 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 642 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 643 struct drm_file *filp); 644 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 645 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 646 struct drm_file *filp); 647 648 /* VRAM scratch page for HDP bug, default vram page */ 649 struct amdgpu_mem_scratch { 650 struct amdgpu_bo *robj; 651 volatile uint32_t *ptr; 652 u64 gpu_addr; 653 }; 654 655 /* 656 * CGS 657 */ 658 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 659 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 660 661 /* 662 * Core structure, functions and helpers. 663 */ 664 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 665 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 666 667 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 668 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 669 670 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 671 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 672 673 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 674 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 675 676 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 677 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 678 679 struct amdgpu_mmio_remap { 680 u32 reg_offset; 681 resource_size_t bus_addr; 682 }; 683 684 /* Define the HW IP blocks will be used in driver , add more if necessary */ 685 enum amd_hw_ip_block_type { 686 GC_HWIP = 1, 687 HDP_HWIP, 688 SDMA0_HWIP, 689 SDMA1_HWIP, 690 SDMA2_HWIP, 691 SDMA3_HWIP, 692 SDMA4_HWIP, 693 SDMA5_HWIP, 694 SDMA6_HWIP, 695 SDMA7_HWIP, 696 LSDMA_HWIP, 697 MMHUB_HWIP, 698 ATHUB_HWIP, 699 NBIO_HWIP, 700 MP0_HWIP, 701 MP1_HWIP, 702 UVD_HWIP, 703 VCN_HWIP = UVD_HWIP, 704 JPEG_HWIP = VCN_HWIP, 705 VCN1_HWIP, 706 VCE_HWIP, 707 VPE_HWIP, 708 DF_HWIP, 709 DCE_HWIP, 710 OSSSYS_HWIP, 711 SMUIO_HWIP, 712 PWR_HWIP, 713 NBIF_HWIP, 714 THM_HWIP, 715 CLK_HWIP, 716 UMC_HWIP, 717 RSMU_HWIP, 718 XGMI_HWIP, 719 DCI_HWIP, 720 PCIE_HWIP, 721 MAX_HWIP 722 }; 723 724 #define HWIP_MAX_INSTANCE 44 725 726 #define HW_ID_MAX 300 727 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 728 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 729 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 730 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 731 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 732 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 733 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 734 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 735 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 736 737 struct amdgpu_ip_map_info { 738 /* Map of logical to actual dev instances/mask */ 739 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 740 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 741 enum amd_hw_ip_block_type block, 742 int8_t inst); 743 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 744 enum amd_hw_ip_block_type block, 745 uint32_t mask); 746 }; 747 748 struct amd_powerplay { 749 void *pp_handle; 750 const struct amd_pm_funcs *pp_funcs; 751 }; 752 753 struct ip_discovery_top; 754 755 /* polaris10 kickers */ 756 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 757 ((rid == 0xE3) || \ 758 (rid == 0xE4) || \ 759 (rid == 0xE5) || \ 760 (rid == 0xE7) || \ 761 (rid == 0xEF))) || \ 762 ((did == 0x6FDF) && \ 763 ((rid == 0xE7) || \ 764 (rid == 0xEF) || \ 765 (rid == 0xFF)))) 766 767 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 768 ((rid == 0xE1) || \ 769 (rid == 0xF7))) 770 771 /* polaris11 kickers */ 772 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 773 ((rid == 0xE0) || \ 774 (rid == 0xE5))) || \ 775 ((did == 0x67FF) && \ 776 ((rid == 0xCF) || \ 777 (rid == 0xEF) || \ 778 (rid == 0xFF)))) 779 780 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 781 ((rid == 0xE2))) 782 783 /* polaris12 kickers */ 784 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 785 ((rid == 0xC0) || \ 786 (rid == 0xC1) || \ 787 (rid == 0xC3) || \ 788 (rid == 0xC7))) || \ 789 ((did == 0x6981) && \ 790 ((rid == 0x00) || \ 791 (rid == 0x01) || \ 792 (rid == 0x10)))) 793 794 struct amdgpu_mqd_prop { 795 uint64_t mqd_gpu_addr; 796 uint64_t hqd_base_gpu_addr; 797 uint64_t rptr_gpu_addr; 798 uint64_t wptr_gpu_addr; 799 uint32_t queue_size; 800 bool use_doorbell; 801 uint32_t doorbell_index; 802 uint64_t eop_gpu_addr; 803 uint32_t hqd_pipe_priority; 804 uint32_t hqd_queue_priority; 805 bool allow_tunneling; 806 bool hqd_active; 807 }; 808 809 struct amdgpu_mqd { 810 unsigned mqd_size; 811 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 812 struct amdgpu_mqd_prop *p); 813 }; 814 815 #define AMDGPU_RESET_MAGIC_NUM 64 816 #define AMDGPU_MAX_DF_PERFMONS 4 817 struct amdgpu_reset_domain; 818 struct amdgpu_fru_info; 819 820 struct amdgpu_reset_info { 821 /* reset dump register */ 822 u32 *reset_dump_reg_list; 823 u32 *reset_dump_reg_value; 824 int num_regs; 825 826 #ifdef CONFIG_DEV_COREDUMP 827 struct amdgpu_coredump_info *coredump_info; 828 #endif 829 }; 830 831 /* 832 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 833 */ 834 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 835 836 struct amdgpu_device { 837 struct device *dev; 838 struct pci_dev *pdev; 839 struct drm_device ddev; 840 841 #ifdef CONFIG_DRM_AMD_ACP 842 struct amdgpu_acp acp; 843 #endif 844 struct amdgpu_hive_info *hive; 845 struct amdgpu_xcp_mgr *xcp_mgr; 846 /* ASIC */ 847 enum amd_asic_type asic_type; 848 uint32_t family; 849 uint32_t rev_id; 850 uint32_t external_rev_id; 851 unsigned long flags; 852 unsigned long apu_flags; 853 int usec_timeout; 854 const struct amdgpu_asic_funcs *asic_funcs; 855 bool shutdown; 856 bool need_swiotlb; 857 bool accel_working; 858 struct notifier_block acpi_nb; 859 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 860 struct debugfs_blob_wrapper debugfs_vbios_blob; 861 struct debugfs_blob_wrapper debugfs_discovery_blob; 862 struct mutex srbm_mutex; 863 /* GRBM index mutex. Protects concurrent access to GRBM index */ 864 struct mutex grbm_idx_mutex; 865 struct dev_pm_domain vga_pm_domain; 866 bool have_disp_power_ref; 867 bool have_atomics_support; 868 869 /* BIOS */ 870 bool is_atom_fw; 871 uint8_t *bios; 872 uint32_t bios_size; 873 uint32_t bios_scratch_reg_offset; 874 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 875 876 /* Register/doorbell mmio */ 877 resource_size_t rmmio_base; 878 resource_size_t rmmio_size; 879 void __iomem *rmmio; 880 /* protects concurrent MM_INDEX/DATA based register access */ 881 spinlock_t mmio_idx_lock; 882 struct amdgpu_mmio_remap rmmio_remap; 883 /* protects concurrent SMC based register access */ 884 spinlock_t smc_idx_lock; 885 amdgpu_rreg_t smc_rreg; 886 amdgpu_wreg_t smc_wreg; 887 /* protects concurrent PCIE register access */ 888 spinlock_t pcie_idx_lock; 889 amdgpu_rreg_t pcie_rreg; 890 amdgpu_wreg_t pcie_wreg; 891 amdgpu_rreg_t pciep_rreg; 892 amdgpu_wreg_t pciep_wreg; 893 amdgpu_rreg_ext_t pcie_rreg_ext; 894 amdgpu_wreg_ext_t pcie_wreg_ext; 895 amdgpu_rreg64_t pcie_rreg64; 896 amdgpu_wreg64_t pcie_wreg64; 897 amdgpu_rreg64_ext_t pcie_rreg64_ext; 898 amdgpu_wreg64_ext_t pcie_wreg64_ext; 899 /* protects concurrent UVD register access */ 900 spinlock_t uvd_ctx_idx_lock; 901 amdgpu_rreg_t uvd_ctx_rreg; 902 amdgpu_wreg_t uvd_ctx_wreg; 903 /* protects concurrent DIDT register access */ 904 spinlock_t didt_idx_lock; 905 amdgpu_rreg_t didt_rreg; 906 amdgpu_wreg_t didt_wreg; 907 /* protects concurrent gc_cac register access */ 908 spinlock_t gc_cac_idx_lock; 909 amdgpu_rreg_t gc_cac_rreg; 910 amdgpu_wreg_t gc_cac_wreg; 911 /* protects concurrent se_cac register access */ 912 spinlock_t se_cac_idx_lock; 913 amdgpu_rreg_t se_cac_rreg; 914 amdgpu_wreg_t se_cac_wreg; 915 /* protects concurrent ENDPOINT (audio) register access */ 916 spinlock_t audio_endpt_idx_lock; 917 amdgpu_block_rreg_t audio_endpt_rreg; 918 amdgpu_block_wreg_t audio_endpt_wreg; 919 struct amdgpu_doorbell doorbell; 920 921 /* clock/pll info */ 922 struct amdgpu_clock clock; 923 924 /* MC */ 925 struct amdgpu_gmc gmc; 926 struct amdgpu_gart gart; 927 dma_addr_t dummy_page_addr; 928 struct amdgpu_vm_manager vm_manager; 929 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 930 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 931 932 /* memory management */ 933 struct amdgpu_mman mman; 934 struct amdgpu_mem_scratch mem_scratch; 935 struct amdgpu_wb wb; 936 atomic64_t num_bytes_moved; 937 atomic64_t num_evictions; 938 atomic64_t num_vram_cpu_page_faults; 939 atomic_t gpu_reset_counter; 940 atomic_t vram_lost_counter; 941 942 /* data for buffer migration throttling */ 943 struct { 944 spinlock_t lock; 945 s64 last_update_us; 946 s64 accum_us; /* accumulated microseconds */ 947 s64 accum_us_vis; /* for visible VRAM */ 948 u32 log2_max_MBps; 949 } mm_stats; 950 951 /* display */ 952 bool enable_virtual_display; 953 struct amdgpu_vkms_output *amdgpu_vkms_output; 954 struct amdgpu_mode_info mode_info; 955 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 956 struct delayed_work hotplug_work; 957 struct amdgpu_irq_src crtc_irq; 958 struct amdgpu_irq_src vline0_irq; 959 struct amdgpu_irq_src vupdate_irq; 960 struct amdgpu_irq_src pageflip_irq; 961 struct amdgpu_irq_src hpd_irq; 962 struct amdgpu_irq_src dmub_trace_irq; 963 struct amdgpu_irq_src dmub_outbox_irq; 964 965 /* rings */ 966 u64 fence_context; 967 unsigned num_rings; 968 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 969 struct dma_fence __rcu *gang_submit; 970 bool ib_pool_ready; 971 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 972 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 973 974 /* interrupts */ 975 struct amdgpu_irq irq; 976 977 /* powerplay */ 978 struct amd_powerplay powerplay; 979 struct amdgpu_pm pm; 980 u64 cg_flags; 981 u32 pg_flags; 982 983 /* nbio */ 984 struct amdgpu_nbio nbio; 985 986 /* hdp */ 987 struct amdgpu_hdp hdp; 988 989 /* smuio */ 990 struct amdgpu_smuio smuio; 991 992 /* mmhub */ 993 struct amdgpu_mmhub mmhub; 994 995 /* gfxhub */ 996 struct amdgpu_gfxhub gfxhub; 997 998 /* gfx */ 999 struct amdgpu_gfx gfx; 1000 1001 /* sdma */ 1002 struct amdgpu_sdma sdma; 1003 1004 /* lsdma */ 1005 struct amdgpu_lsdma lsdma; 1006 1007 /* uvd */ 1008 struct amdgpu_uvd uvd; 1009 1010 /* vce */ 1011 struct amdgpu_vce vce; 1012 1013 /* vcn */ 1014 struct amdgpu_vcn vcn; 1015 1016 /* jpeg */ 1017 struct amdgpu_jpeg jpeg; 1018 1019 /* vpe */ 1020 struct amdgpu_vpe vpe; 1021 1022 /* umsch */ 1023 struct amdgpu_umsch_mm umsch_mm; 1024 bool enable_umsch_mm; 1025 1026 /* firmwares */ 1027 struct amdgpu_firmware firmware; 1028 1029 /* PSP */ 1030 struct psp_context psp; 1031 1032 /* GDS */ 1033 struct amdgpu_gds gds; 1034 1035 /* for userq and VM fences */ 1036 struct amdgpu_seq64 seq64; 1037 1038 /* KFD */ 1039 struct amdgpu_kfd_dev kfd; 1040 1041 /* UMC */ 1042 struct amdgpu_umc umc; 1043 1044 /* display related functionality */ 1045 struct amdgpu_display_manager dm; 1046 1047 /* mes */ 1048 bool enable_mes; 1049 bool enable_mes_kiq; 1050 bool enable_uni_mes; 1051 struct amdgpu_mes mes; 1052 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1053 1054 /* df */ 1055 struct amdgpu_df df; 1056 1057 /* MCA */ 1058 struct amdgpu_mca mca; 1059 1060 /* ACA */ 1061 struct amdgpu_aca aca; 1062 1063 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1064 uint32_t harvest_ip_mask; 1065 int num_ip_blocks; 1066 struct mutex mn_lock; 1067 DECLARE_HASHTABLE(mn_hash, 7); 1068 1069 /* tracking pinned memory */ 1070 atomic64_t vram_pin_size; 1071 atomic64_t visible_pin_size; 1072 atomic64_t gart_pin_size; 1073 1074 /* soc15 register offset based on ip, instance and segment */ 1075 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1076 struct amdgpu_ip_map_info ip_map; 1077 1078 /* delayed work_func for deferring clockgating during resume */ 1079 struct delayed_work delayed_init_work; 1080 1081 struct amdgpu_virt virt; 1082 1083 /* link all shadow bo */ 1084 struct list_head shadow_list; 1085 struct mutex shadow_list_lock; 1086 1087 /* record hw reset is performed */ 1088 bool has_hw_reset; 1089 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1090 1091 /* s3/s4 mask */ 1092 bool in_suspend; 1093 bool in_s3; 1094 bool in_s4; 1095 bool in_s0ix; 1096 /* indicate amdgpu suspension status */ 1097 bool suspend_complete; 1098 1099 enum pp_mp1_state mp1_state; 1100 struct amdgpu_doorbell_index doorbell_index; 1101 1102 struct mutex notifier_lock; 1103 1104 int asic_reset_res; 1105 struct work_struct xgmi_reset_work; 1106 struct list_head reset_list; 1107 1108 long gfx_timeout; 1109 long sdma_timeout; 1110 long video_timeout; 1111 long compute_timeout; 1112 long psp_timeout; 1113 1114 uint64_t unique_id; 1115 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1116 1117 /* enable runtime pm on the device */ 1118 bool in_runpm; 1119 bool has_pr3; 1120 1121 bool ucode_sysfs_en; 1122 1123 struct amdgpu_fru_info *fru_info; 1124 atomic_t throttling_logging_enabled; 1125 struct ratelimit_state throttling_logging_rs; 1126 uint32_t ras_hw_enabled; 1127 uint32_t ras_enabled; 1128 1129 bool no_hw_access; 1130 struct pci_saved_state *pci_state; 1131 pci_channel_state_t pci_channel_state; 1132 1133 /* Track auto wait count on s_barrier settings */ 1134 bool barrier_has_auto_waitcnt; 1135 1136 struct amdgpu_reset_control *reset_cntl; 1137 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1138 1139 bool ram_is_direct_mapped; 1140 1141 struct list_head ras_list; 1142 1143 struct ip_discovery_top *ip_top; 1144 1145 struct amdgpu_reset_domain *reset_domain; 1146 1147 struct mutex benchmark_mutex; 1148 1149 struct amdgpu_reset_info reset_info; 1150 1151 bool scpm_enabled; 1152 uint32_t scpm_status; 1153 1154 struct work_struct reset_work; 1155 1156 bool job_hang; 1157 bool dc_enabled; 1158 /* Mask of active clusters */ 1159 uint32_t aid_mask; 1160 1161 /* Debug */ 1162 bool debug_vm; 1163 bool debug_largebar; 1164 bool debug_disable_soft_recovery; 1165 bool debug_use_vram_fw_buf; 1166 }; 1167 1168 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1169 uint8_t ip, uint8_t inst) 1170 { 1171 /* This considers only major/minor/rev and ignores 1172 * subrevision/variant fields. 1173 */ 1174 return adev->ip_versions[ip][inst] & ~0xFFU; 1175 } 1176 1177 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1178 uint8_t ip, uint8_t inst) 1179 { 1180 /* This returns full version - major/minor/rev/variant/subrevision */ 1181 return adev->ip_versions[ip][inst]; 1182 } 1183 1184 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1185 { 1186 return container_of(ddev, struct amdgpu_device, ddev); 1187 } 1188 1189 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1190 { 1191 return &adev->ddev; 1192 } 1193 1194 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1195 { 1196 return container_of(bdev, struct amdgpu_device, mman.bdev); 1197 } 1198 1199 int amdgpu_device_init(struct amdgpu_device *adev, 1200 uint32_t flags); 1201 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1202 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1203 1204 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1205 1206 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1207 void *buf, size_t size, bool write); 1208 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1209 void *buf, size_t size, bool write); 1210 1211 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1212 void *buf, size_t size, bool write); 1213 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1214 uint32_t inst, uint32_t reg_addr, char reg_name[], 1215 uint32_t expected_value, uint32_t mask); 1216 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1217 uint32_t reg, uint32_t acc_flags); 1218 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1219 u64 reg_addr); 1220 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1221 uint32_t reg, uint32_t acc_flags, 1222 uint32_t xcc_id); 1223 void amdgpu_device_wreg(struct amdgpu_device *adev, 1224 uint32_t reg, uint32_t v, 1225 uint32_t acc_flags); 1226 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1227 u64 reg_addr, u32 reg_data); 1228 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1229 uint32_t reg, uint32_t v, 1230 uint32_t acc_flags, 1231 uint32_t xcc_id); 1232 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1233 uint32_t reg, uint32_t v, uint32_t xcc_id); 1234 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1235 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1236 1237 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1238 u32 reg_addr); 1239 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1240 u32 reg_addr); 1241 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1242 u64 reg_addr); 1243 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1244 u32 reg_addr, u32 reg_data); 1245 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1246 u32 reg_addr, u64 reg_data); 1247 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1248 u64 reg_addr, u64 reg_data); 1249 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1250 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1251 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1252 1253 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1254 1255 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1256 struct amdgpu_reset_context *reset_context); 1257 1258 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1259 struct amdgpu_reset_context *reset_context); 1260 1261 int emu_soc_asic_init(struct amdgpu_device *adev); 1262 1263 /* 1264 * Registers read & write functions. 1265 */ 1266 #define AMDGPU_REGS_NO_KIQ (1<<1) 1267 #define AMDGPU_REGS_RLC (1<<2) 1268 1269 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1270 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1271 1272 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1273 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1274 1275 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1276 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1277 1278 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1279 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1280 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1281 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1282 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1283 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1284 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1285 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1286 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1287 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1288 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1289 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1290 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1291 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1292 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1293 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1294 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1295 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1296 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1297 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1298 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1299 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1300 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1301 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1302 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1303 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1304 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1305 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1306 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1307 #define WREG32_P(reg, val, mask) \ 1308 do { \ 1309 uint32_t tmp_ = RREG32(reg); \ 1310 tmp_ &= (mask); \ 1311 tmp_ |= ((val) & ~(mask)); \ 1312 WREG32(reg, tmp_); \ 1313 } while (0) 1314 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1315 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1316 #define WREG32_PLL_P(reg, val, mask) \ 1317 do { \ 1318 uint32_t tmp_ = RREG32_PLL(reg); \ 1319 tmp_ &= (mask); \ 1320 tmp_ |= ((val) & ~(mask)); \ 1321 WREG32_PLL(reg, tmp_); \ 1322 } while (0) 1323 1324 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1325 do { \ 1326 u32 tmp = RREG32_SMC(_Reg); \ 1327 tmp &= (_Mask); \ 1328 tmp |= ((_Val) & ~(_Mask)); \ 1329 WREG32_SMC(_Reg, tmp); \ 1330 } while (0) 1331 1332 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1333 1334 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1335 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1336 1337 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1338 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1339 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1340 1341 #define REG_GET_FIELD(value, reg, field) \ 1342 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1343 1344 #define WREG32_FIELD(reg, field, val) \ 1345 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1346 1347 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1348 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1349 1350 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1351 /* 1352 * BIOS helpers. 1353 */ 1354 #define RBIOS8(i) (adev->bios[i]) 1355 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1356 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1357 1358 /* 1359 * ASICs macro. 1360 */ 1361 #define amdgpu_asic_set_vga_state(adev, state) \ 1362 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1363 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1364 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1365 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1366 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1367 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1368 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1369 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1370 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1371 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1372 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1373 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1374 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1375 #define amdgpu_asic_flush_hdp(adev, r) \ 1376 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1377 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1378 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1379 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1380 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1381 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1382 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1383 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1384 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1385 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1386 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1387 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1388 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1389 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1390 1391 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1392 1393 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1394 #define for_each_inst(i, inst_mask) \ 1395 for (i = ffs(inst_mask); i-- != 0; \ 1396 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1397 1398 /* Common functions */ 1399 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1400 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1401 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1402 struct amdgpu_job *job, 1403 struct amdgpu_reset_context *reset_context); 1404 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1405 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1406 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1407 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1408 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1409 1410 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1411 u64 num_vis_bytes); 1412 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1413 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1414 const u32 *registers, 1415 const u32 array_size); 1416 1417 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1418 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1419 bool amdgpu_device_supports_px(struct drm_device *dev); 1420 bool amdgpu_device_supports_boco(struct drm_device *dev); 1421 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1422 int amdgpu_device_supports_baco(struct drm_device *dev); 1423 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1424 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1425 struct amdgpu_device *peer_adev); 1426 int amdgpu_device_baco_enter(struct drm_device *dev); 1427 int amdgpu_device_baco_exit(struct drm_device *dev); 1428 1429 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1430 struct amdgpu_ring *ring); 1431 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1432 struct amdgpu_ring *ring); 1433 1434 void amdgpu_device_halt(struct amdgpu_device *adev); 1435 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1436 u32 reg); 1437 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1438 u32 reg, u32 v); 1439 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1440 struct dma_fence *gang); 1441 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1442 1443 /* atpx handler */ 1444 #if defined(CONFIG_VGA_SWITCHEROO) 1445 void amdgpu_register_atpx_handler(void); 1446 void amdgpu_unregister_atpx_handler(void); 1447 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1448 bool amdgpu_is_atpx_hybrid(void); 1449 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1450 bool amdgpu_has_atpx(void); 1451 #else 1452 static inline void amdgpu_register_atpx_handler(void) {} 1453 static inline void amdgpu_unregister_atpx_handler(void) {} 1454 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1455 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1456 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1457 static inline bool amdgpu_has_atpx(void) { return false; } 1458 #endif 1459 1460 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1461 void *amdgpu_atpx_get_dhandle(void); 1462 #else 1463 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1464 #endif 1465 1466 /* 1467 * KMS 1468 */ 1469 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1470 extern const int amdgpu_max_kms_ioctl; 1471 1472 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1473 void amdgpu_driver_unload_kms(struct drm_device *dev); 1474 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1475 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1476 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1477 struct drm_file *file_priv); 1478 void amdgpu_driver_release_kms(struct drm_device *dev); 1479 1480 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1481 int amdgpu_device_prepare(struct drm_device *dev); 1482 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1483 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1484 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1485 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1486 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1487 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1488 struct drm_file *filp); 1489 1490 /* 1491 * functions used by amdgpu_encoder.c 1492 */ 1493 struct amdgpu_afmt_acr { 1494 u32 clock; 1495 1496 int n_32khz; 1497 int cts_32khz; 1498 1499 int n_44_1khz; 1500 int cts_44_1khz; 1501 1502 int n_48khz; 1503 int cts_48khz; 1504 1505 }; 1506 1507 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1508 1509 /* amdgpu_acpi.c */ 1510 1511 struct amdgpu_numa_info { 1512 uint64_t size; 1513 int pxm; 1514 int nid; 1515 }; 1516 1517 /* ATCS Device/Driver State */ 1518 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1519 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1520 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1521 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1522 1523 #if defined(CONFIG_ACPI) 1524 int amdgpu_acpi_init(struct amdgpu_device *adev); 1525 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1526 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1527 bool amdgpu_acpi_is_power_shift_control_supported(void); 1528 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1529 u8 perf_req, bool advertise); 1530 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1531 u8 dev_state, bool drv_state); 1532 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1533 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1534 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1535 u64 *tmr_size); 1536 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1537 struct amdgpu_numa_info *numa_info); 1538 1539 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1540 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1541 void amdgpu_acpi_detect(void); 1542 void amdgpu_acpi_release(void); 1543 #else 1544 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1545 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1546 u64 *tmr_offset, u64 *tmr_size) 1547 { 1548 return -EINVAL; 1549 } 1550 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1551 int xcc_id, 1552 struct amdgpu_numa_info *numa_info) 1553 { 1554 return -EINVAL; 1555 } 1556 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1557 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1558 static inline void amdgpu_acpi_detect(void) { } 1559 static inline void amdgpu_acpi_release(void) { } 1560 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1561 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1562 u8 dev_state, bool drv_state) { return 0; } 1563 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1564 enum amdgpu_ss ss_state) { return 0; } 1565 #endif 1566 1567 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1568 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1569 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1570 void amdgpu_choose_low_power_state(struct amdgpu_device *adev); 1571 #else 1572 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1573 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1574 static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } 1575 #endif 1576 1577 #if defined(CONFIG_DRM_AMD_DC) 1578 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1579 #else 1580 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1581 #endif 1582 1583 1584 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1585 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1586 1587 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1588 pci_channel_state_t state); 1589 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1590 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1591 void amdgpu_pci_resume(struct pci_dev *pdev); 1592 1593 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1594 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1595 1596 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1597 1598 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1599 enum amd_clockgating_state state); 1600 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1601 enum amd_powergating_state state); 1602 1603 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1604 { 1605 return amdgpu_gpu_recovery != 0 && 1606 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1607 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1608 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1609 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1610 } 1611 1612 #include "amdgpu_object.h" 1613 1614 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1615 { 1616 return adev->gmc.tmz_enabled; 1617 } 1618 1619 int amdgpu_in_reset(struct amdgpu_device *adev); 1620 1621 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1622 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1623 extern const struct attribute_group amdgpu_flash_attr_group; 1624 1625 #endif 1626