1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_vpe.h" 83 #include "amdgpu_umsch_mm.h" 84 #include "amdgpu_gmc.h" 85 #include "amdgpu_gfx.h" 86 #include "amdgpu_sdma.h" 87 #include "amdgpu_lsdma.h" 88 #include "amdgpu_nbio.h" 89 #include "amdgpu_hdp.h" 90 #include "amdgpu_dm.h" 91 #include "amdgpu_virt.h" 92 #include "amdgpu_csa.h" 93 #include "amdgpu_mes_ctx.h" 94 #include "amdgpu_gart.h" 95 #include "amdgpu_debugfs.h" 96 #include "amdgpu_job.h" 97 #include "amdgpu_bo_list.h" 98 #include "amdgpu_gem.h" 99 #include "amdgpu_doorbell.h" 100 #include "amdgpu_amdkfd.h" 101 #include "amdgpu_discovery.h" 102 #include "amdgpu_mes.h" 103 #include "amdgpu_umc.h" 104 #include "amdgpu_mmhub.h" 105 #include "amdgpu_gfxhub.h" 106 #include "amdgpu_df.h" 107 #include "amdgpu_smuio.h" 108 #include "amdgpu_fdinfo.h" 109 #include "amdgpu_mca.h" 110 #include "amdgpu_ras.h" 111 #include "amdgpu_xcp.h" 112 #include "amdgpu_seq64.h" 113 #include "amdgpu_reg_state.h" 114 115 #define MAX_GPU_INSTANCE 64 116 117 struct amdgpu_gpu_instance 118 { 119 struct amdgpu_device *adev; 120 int mgpu_fan_enabled; 121 }; 122 123 struct amdgpu_mgpu_info 124 { 125 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 126 struct mutex mutex; 127 uint32_t num_gpu; 128 uint32_t num_dgpu; 129 uint32_t num_apu; 130 131 /* delayed reset_func for XGMI configuration if necessary */ 132 struct delayed_work delayed_reset_work; 133 bool pending_reset; 134 }; 135 136 enum amdgpu_ss { 137 AMDGPU_SS_DRV_LOAD, 138 AMDGPU_SS_DEV_D0, 139 AMDGPU_SS_DEV_D3, 140 AMDGPU_SS_DRV_UNLOAD 141 }; 142 143 struct amdgpu_watchdog_timer 144 { 145 bool timeout_fatal_disable; 146 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 147 }; 148 149 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 150 151 /* 152 * Modules parameters. 153 */ 154 extern int amdgpu_modeset; 155 extern unsigned int amdgpu_vram_limit; 156 extern int amdgpu_vis_vram_limit; 157 extern int amdgpu_gart_size; 158 extern int amdgpu_gtt_size; 159 extern int amdgpu_moverate; 160 extern int amdgpu_audio; 161 extern int amdgpu_disp_priority; 162 extern int amdgpu_hw_i2c; 163 extern int amdgpu_pcie_gen2; 164 extern int amdgpu_msi; 165 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 166 extern int amdgpu_dpm; 167 extern int amdgpu_fw_load_type; 168 extern int amdgpu_aspm; 169 extern int amdgpu_runtime_pm; 170 extern uint amdgpu_ip_block_mask; 171 extern int amdgpu_bapm; 172 extern int amdgpu_deep_color; 173 extern int amdgpu_vm_size; 174 extern int amdgpu_vm_block_size; 175 extern int amdgpu_vm_fragment_size; 176 extern int amdgpu_vm_fault_stop; 177 extern int amdgpu_vm_debug; 178 extern int amdgpu_vm_update_mode; 179 extern int amdgpu_exp_hw_support; 180 extern int amdgpu_dc; 181 extern int amdgpu_sched_jobs; 182 extern int amdgpu_sched_hw_submission; 183 extern uint amdgpu_pcie_gen_cap; 184 extern uint amdgpu_pcie_lane_cap; 185 extern u64 amdgpu_cg_mask; 186 extern uint amdgpu_pg_mask; 187 extern uint amdgpu_sdma_phase_quantum; 188 extern char *amdgpu_disable_cu; 189 extern char *amdgpu_virtual_display; 190 extern uint amdgpu_pp_feature_mask; 191 extern uint amdgpu_force_long_training; 192 extern int amdgpu_lbpw; 193 extern int amdgpu_compute_multipipe; 194 extern int amdgpu_gpu_recovery; 195 extern int amdgpu_emu_mode; 196 extern uint amdgpu_smu_memory_pool_size; 197 extern int amdgpu_smu_pptable_id; 198 extern uint amdgpu_dc_feature_mask; 199 extern uint amdgpu_dc_debug_mask; 200 extern uint amdgpu_dc_visual_confirm; 201 extern uint amdgpu_dm_abm_level; 202 extern int amdgpu_backlight; 203 extern struct amdgpu_mgpu_info mgpu_info; 204 extern int amdgpu_ras_enable; 205 extern uint amdgpu_ras_mask; 206 extern int amdgpu_bad_page_threshold; 207 extern bool amdgpu_ignore_bad_page_threshold; 208 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 209 extern int amdgpu_async_gfx_ring; 210 extern int amdgpu_mcbp; 211 extern int amdgpu_discovery; 212 extern int amdgpu_mes; 213 extern int amdgpu_mes_kiq; 214 extern int amdgpu_noretry; 215 extern int amdgpu_force_asic_type; 216 extern int amdgpu_smartshift_bias; 217 extern int amdgpu_use_xgmi_p2p; 218 extern int amdgpu_mtype_local; 219 extern bool enforce_isolation; 220 #ifdef CONFIG_HSA_AMD 221 extern int sched_policy; 222 extern bool debug_evictions; 223 extern bool no_system_mem_limit; 224 extern int halt_if_hws_hang; 225 #else 226 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 227 static const bool __maybe_unused debug_evictions; /* = false */ 228 static const bool __maybe_unused no_system_mem_limit; 229 static const int __maybe_unused halt_if_hws_hang; 230 #endif 231 #ifdef CONFIG_HSA_AMD_P2P 232 extern bool pcie_p2p; 233 #endif 234 235 extern int amdgpu_tmz; 236 extern int amdgpu_reset_method; 237 238 #ifdef CONFIG_DRM_AMDGPU_SI 239 extern int amdgpu_si_support; 240 #endif 241 #ifdef CONFIG_DRM_AMDGPU_CIK 242 extern int amdgpu_cik_support; 243 #endif 244 extern int amdgpu_num_kcq; 245 246 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 247 extern int amdgpu_vcnfw_log; 248 extern int amdgpu_sg_display; 249 extern int amdgpu_umsch_mm; 250 extern int amdgpu_seamless; 251 252 extern int amdgpu_user_partt_mode; 253 extern int amdgpu_agp; 254 255 extern int amdgpu_wbrf; 256 257 extern int fw_bo_location; 258 259 #define AMDGPU_VM_MAX_NUM_CTX 4096 260 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 261 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 262 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 263 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 264 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 265 #define AMDGPUFB_CONN_LIMIT 4 266 #define AMDGPU_BIOS_NUM_SCRATCH 16 267 268 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 269 270 /* hard reset data */ 271 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 272 273 /* reset flags */ 274 #define AMDGPU_RESET_GFX (1 << 0) 275 #define AMDGPU_RESET_COMPUTE (1 << 1) 276 #define AMDGPU_RESET_DMA (1 << 2) 277 #define AMDGPU_RESET_CP (1 << 3) 278 #define AMDGPU_RESET_GRBM (1 << 4) 279 #define AMDGPU_RESET_DMA1 (1 << 5) 280 #define AMDGPU_RESET_RLC (1 << 6) 281 #define AMDGPU_RESET_SEM (1 << 7) 282 #define AMDGPU_RESET_IH (1 << 8) 283 #define AMDGPU_RESET_VMC (1 << 9) 284 #define AMDGPU_RESET_MC (1 << 10) 285 #define AMDGPU_RESET_DISPLAY (1 << 11) 286 #define AMDGPU_RESET_UVD (1 << 12) 287 #define AMDGPU_RESET_VCE (1 << 13) 288 #define AMDGPU_RESET_VCE1 (1 << 14) 289 290 /* max cursor sizes (in pixels) */ 291 #define CIK_CURSOR_WIDTH 128 292 #define CIK_CURSOR_HEIGHT 128 293 294 /* smart shift bias level limits */ 295 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 296 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 297 298 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 299 #define AMDGPU_SWCTF_EXTRA_DELAY 50 300 301 struct amdgpu_xcp_mgr; 302 struct amdgpu_device; 303 struct amdgpu_irq_src; 304 struct amdgpu_fpriv; 305 struct amdgpu_bo_va_mapping; 306 struct kfd_vm_fault_info; 307 struct amdgpu_hive_info; 308 struct amdgpu_reset_context; 309 struct amdgpu_reset_control; 310 311 enum amdgpu_cp_irq { 312 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 313 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 314 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 315 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 316 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 317 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 318 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 319 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 320 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 321 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 322 323 AMDGPU_CP_IRQ_LAST 324 }; 325 326 enum amdgpu_thermal_irq { 327 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 328 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 329 330 AMDGPU_THERMAL_IRQ_LAST 331 }; 332 333 enum amdgpu_kiq_irq { 334 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 335 AMDGPU_CP_KIQ_IRQ_LAST 336 }; 337 #define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ 338 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 339 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 340 #define MAX_KIQ_REG_TRY 1000 341 342 int amdgpu_device_ip_set_clockgating_state(void *dev, 343 enum amd_ip_block_type block_type, 344 enum amd_clockgating_state state); 345 int amdgpu_device_ip_set_powergating_state(void *dev, 346 enum amd_ip_block_type block_type, 347 enum amd_powergating_state state); 348 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 349 u64 *flags); 350 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 351 enum amd_ip_block_type block_type); 352 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 353 enum amd_ip_block_type block_type); 354 355 #define AMDGPU_MAX_IP_NUM 16 356 357 struct amdgpu_ip_block_status { 358 bool valid; 359 bool sw; 360 bool hw; 361 bool late_initialized; 362 bool hang; 363 }; 364 365 struct amdgpu_ip_block_version { 366 const enum amd_ip_block_type type; 367 const u32 major; 368 const u32 minor; 369 const u32 rev; 370 const struct amd_ip_funcs *funcs; 371 }; 372 373 struct amdgpu_ip_block { 374 struct amdgpu_ip_block_status status; 375 const struct amdgpu_ip_block_version *version; 376 }; 377 378 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 379 enum amd_ip_block_type type, 380 u32 major, u32 minor); 381 382 struct amdgpu_ip_block * 383 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 384 enum amd_ip_block_type type); 385 386 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 387 const struct amdgpu_ip_block_version *ip_block_version); 388 389 /* 390 * BIOS. 391 */ 392 bool amdgpu_get_bios(struct amdgpu_device *adev); 393 bool amdgpu_read_bios(struct amdgpu_device *adev); 394 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 395 u8 *bios, u32 length_bytes); 396 /* 397 * Clocks 398 */ 399 400 #define AMDGPU_MAX_PPLL 3 401 402 struct amdgpu_clock { 403 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 404 struct amdgpu_pll spll; 405 struct amdgpu_pll mpll; 406 /* 10 Khz units */ 407 uint32_t default_mclk; 408 uint32_t default_sclk; 409 uint32_t default_dispclk; 410 uint32_t current_dispclk; 411 uint32_t dp_extclk; 412 uint32_t max_pixel_clock; 413 }; 414 415 /* sub-allocation manager, it has to be protected by another lock. 416 * By conception this is an helper for other part of the driver 417 * like the indirect buffer or semaphore, which both have their 418 * locking. 419 * 420 * Principe is simple, we keep a list of sub allocation in offset 421 * order (first entry has offset == 0, last entry has the highest 422 * offset). 423 * 424 * When allocating new object we first check if there is room at 425 * the end total_size - (last_object_offset + last_object_size) >= 426 * alloc_size. If so we allocate new object there. 427 * 428 * When there is not enough room at the end, we start waiting for 429 * each sub object until we reach object_offset+object_size >= 430 * alloc_size, this object then become the sub object we return. 431 * 432 * Alignment can't be bigger than page size. 433 * 434 * Hole are not considered for allocation to keep things simple. 435 * Assumption is that there won't be hole (all object on same 436 * alignment). 437 */ 438 439 struct amdgpu_sa_manager { 440 struct drm_suballoc_manager base; 441 struct amdgpu_bo *bo; 442 uint64_t gpu_addr; 443 void *cpu_ptr; 444 }; 445 446 int amdgpu_fence_slab_init(void); 447 void amdgpu_fence_slab_fini(void); 448 449 /* 450 * IRQS. 451 */ 452 453 struct amdgpu_flip_work { 454 struct delayed_work flip_work; 455 struct work_struct unpin_work; 456 struct amdgpu_device *adev; 457 int crtc_id; 458 u32 target_vblank; 459 uint64_t base; 460 struct drm_pending_vblank_event *event; 461 struct amdgpu_bo *old_abo; 462 unsigned shared_count; 463 struct dma_fence **shared; 464 struct dma_fence_cb cb; 465 bool async; 466 }; 467 468 469 /* 470 * file private structure 471 */ 472 473 struct amdgpu_fpriv { 474 struct amdgpu_vm vm; 475 struct amdgpu_bo_va *prt_va; 476 struct amdgpu_bo_va *csa_va; 477 struct amdgpu_bo_va *seq64_va; 478 struct mutex bo_list_lock; 479 struct idr bo_list_handles; 480 struct amdgpu_ctx_mgr ctx_mgr; 481 /** GPU partition selection */ 482 uint32_t xcp_id; 483 }; 484 485 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 486 487 /* 488 * Writeback 489 */ 490 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 491 492 struct amdgpu_wb { 493 struct amdgpu_bo *wb_obj; 494 volatile uint32_t *wb; 495 uint64_t gpu_addr; 496 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 497 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 498 }; 499 500 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 501 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 502 503 /* 504 * Benchmarking 505 */ 506 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 507 508 /* 509 * ASIC specific register table accessible by UMD 510 */ 511 struct amdgpu_allowed_register_entry { 512 uint32_t reg_offset; 513 bool grbm_indexed; 514 }; 515 516 /** 517 * enum amd_reset_method - Methods for resetting AMD GPU devices 518 * 519 * @AMD_RESET_METHOD_NONE: The device will not be reset. 520 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 521 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 522 * any device. 523 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 524 * individually. Suitable only for some discrete GPU, not 525 * available for all ASICs. 526 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 527 * are reset depends on the ASIC. Notably doesn't reset IPs 528 * shared with the CPU on APUs or the memory controllers (so 529 * VRAM is not lost). Not available on all ASICs. 530 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 531 * but without powering off the PCI bus. Suitable only for 532 * discrete GPUs. 533 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 534 * and does a secondary bus reset or FLR, depending on what the 535 * underlying hardware supports. 536 * 537 * Methods available for AMD GPU driver for resetting the device. Not all 538 * methods are suitable for every device. User can override the method using 539 * module parameter `reset_method`. 540 */ 541 enum amd_reset_method { 542 AMD_RESET_METHOD_NONE = -1, 543 AMD_RESET_METHOD_LEGACY = 0, 544 AMD_RESET_METHOD_MODE0, 545 AMD_RESET_METHOD_MODE1, 546 AMD_RESET_METHOD_MODE2, 547 AMD_RESET_METHOD_BACO, 548 AMD_RESET_METHOD_PCI, 549 }; 550 551 struct amdgpu_video_codec_info { 552 u32 codec_type; 553 u32 max_width; 554 u32 max_height; 555 u32 max_pixels_per_frame; 556 u32 max_level; 557 }; 558 559 #define codec_info_build(type, width, height, level) \ 560 .codec_type = type,\ 561 .max_width = width,\ 562 .max_height = height,\ 563 .max_pixels_per_frame = height * width,\ 564 .max_level = level, 565 566 struct amdgpu_video_codecs { 567 const u32 codec_count; 568 const struct amdgpu_video_codec_info *codec_array; 569 }; 570 571 /* 572 * ASIC specific functions. 573 */ 574 struct amdgpu_asic_funcs { 575 bool (*read_disabled_bios)(struct amdgpu_device *adev); 576 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 577 u8 *bios, u32 length_bytes); 578 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 579 u32 sh_num, u32 reg_offset, u32 *value); 580 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 581 int (*reset)(struct amdgpu_device *adev); 582 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 583 /* get the reference clock */ 584 u32 (*get_xclk)(struct amdgpu_device *adev); 585 /* MM block clocks */ 586 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 587 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 588 /* static power management */ 589 int (*get_pcie_lanes)(struct amdgpu_device *adev); 590 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 591 /* get config memsize register */ 592 u32 (*get_config_memsize)(struct amdgpu_device *adev); 593 /* flush hdp write queue */ 594 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 595 /* invalidate hdp read cache */ 596 void (*invalidate_hdp)(struct amdgpu_device *adev, 597 struct amdgpu_ring *ring); 598 /* check if the asic needs a full reset of if soft reset will work */ 599 bool (*need_full_reset)(struct amdgpu_device *adev); 600 /* initialize doorbell layout for specific asic*/ 601 void (*init_doorbell_index)(struct amdgpu_device *adev); 602 /* PCIe bandwidth usage */ 603 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 604 uint64_t *count1); 605 /* do we need to reset the asic at init time (e.g., kexec) */ 606 bool (*need_reset_on_init)(struct amdgpu_device *adev); 607 /* PCIe replay counter */ 608 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 609 /* device supports BACO */ 610 bool (*supports_baco)(struct amdgpu_device *adev); 611 /* pre asic_init quirks */ 612 void (*pre_asic_init)(struct amdgpu_device *adev); 613 /* enter/exit umd stable pstate */ 614 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 615 /* query video codecs */ 616 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 617 const struct amdgpu_video_codecs **codecs); 618 /* encode "> 32bits" smn addressing */ 619 u64 (*encode_ext_smn_addressing)(int ext_id); 620 621 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 622 enum amdgpu_reg_state reg_state, void *buf, 623 size_t max_size); 624 }; 625 626 /* 627 * IOCTL. 628 */ 629 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 630 struct drm_file *filp); 631 632 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 633 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 634 struct drm_file *filp); 635 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 636 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 637 struct drm_file *filp); 638 639 /* VRAM scratch page for HDP bug, default vram page */ 640 struct amdgpu_mem_scratch { 641 struct amdgpu_bo *robj; 642 volatile uint32_t *ptr; 643 u64 gpu_addr; 644 }; 645 646 /* 647 * CGS 648 */ 649 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 650 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 651 652 /* 653 * Core structure, functions and helpers. 654 */ 655 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 656 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 657 658 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 659 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 660 661 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 662 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 663 664 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 665 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 666 667 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 668 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 669 670 struct amdgpu_mmio_remap { 671 u32 reg_offset; 672 resource_size_t bus_addr; 673 }; 674 675 /* Define the HW IP blocks will be used in driver , add more if necessary */ 676 enum amd_hw_ip_block_type { 677 GC_HWIP = 1, 678 HDP_HWIP, 679 SDMA0_HWIP, 680 SDMA1_HWIP, 681 SDMA2_HWIP, 682 SDMA3_HWIP, 683 SDMA4_HWIP, 684 SDMA5_HWIP, 685 SDMA6_HWIP, 686 SDMA7_HWIP, 687 LSDMA_HWIP, 688 MMHUB_HWIP, 689 ATHUB_HWIP, 690 NBIO_HWIP, 691 MP0_HWIP, 692 MP1_HWIP, 693 UVD_HWIP, 694 VCN_HWIP = UVD_HWIP, 695 JPEG_HWIP = VCN_HWIP, 696 VCN1_HWIP, 697 VCE_HWIP, 698 VPE_HWIP, 699 DF_HWIP, 700 DCE_HWIP, 701 OSSSYS_HWIP, 702 SMUIO_HWIP, 703 PWR_HWIP, 704 NBIF_HWIP, 705 THM_HWIP, 706 CLK_HWIP, 707 UMC_HWIP, 708 RSMU_HWIP, 709 XGMI_HWIP, 710 DCI_HWIP, 711 PCIE_HWIP, 712 MAX_HWIP 713 }; 714 715 #define HWIP_MAX_INSTANCE 44 716 717 #define HW_ID_MAX 300 718 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 719 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 720 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 721 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 722 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 723 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 724 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 725 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 726 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 727 728 struct amdgpu_ip_map_info { 729 /* Map of logical to actual dev instances/mask */ 730 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 731 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 732 enum amd_hw_ip_block_type block, 733 int8_t inst); 734 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 735 enum amd_hw_ip_block_type block, 736 uint32_t mask); 737 }; 738 739 struct amd_powerplay { 740 void *pp_handle; 741 const struct amd_pm_funcs *pp_funcs; 742 }; 743 744 struct ip_discovery_top; 745 746 /* polaris10 kickers */ 747 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 748 ((rid == 0xE3) || \ 749 (rid == 0xE4) || \ 750 (rid == 0xE5) || \ 751 (rid == 0xE7) || \ 752 (rid == 0xEF))) || \ 753 ((did == 0x6FDF) && \ 754 ((rid == 0xE7) || \ 755 (rid == 0xEF) || \ 756 (rid == 0xFF)))) 757 758 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 759 ((rid == 0xE1) || \ 760 (rid == 0xF7))) 761 762 /* polaris11 kickers */ 763 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 764 ((rid == 0xE0) || \ 765 (rid == 0xE5))) || \ 766 ((did == 0x67FF) && \ 767 ((rid == 0xCF) || \ 768 (rid == 0xEF) || \ 769 (rid == 0xFF)))) 770 771 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 772 ((rid == 0xE2))) 773 774 /* polaris12 kickers */ 775 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 776 ((rid == 0xC0) || \ 777 (rid == 0xC1) || \ 778 (rid == 0xC3) || \ 779 (rid == 0xC7))) || \ 780 ((did == 0x6981) && \ 781 ((rid == 0x00) || \ 782 (rid == 0x01) || \ 783 (rid == 0x10)))) 784 785 struct amdgpu_mqd_prop { 786 uint64_t mqd_gpu_addr; 787 uint64_t hqd_base_gpu_addr; 788 uint64_t rptr_gpu_addr; 789 uint64_t wptr_gpu_addr; 790 uint32_t queue_size; 791 bool use_doorbell; 792 uint32_t doorbell_index; 793 uint64_t eop_gpu_addr; 794 uint32_t hqd_pipe_priority; 795 uint32_t hqd_queue_priority; 796 bool allow_tunneling; 797 bool hqd_active; 798 }; 799 800 struct amdgpu_mqd { 801 unsigned mqd_size; 802 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 803 struct amdgpu_mqd_prop *p); 804 }; 805 806 #define AMDGPU_RESET_MAGIC_NUM 64 807 #define AMDGPU_MAX_DF_PERFMONS 4 808 struct amdgpu_reset_domain; 809 struct amdgpu_fru_info; 810 811 struct amdgpu_reset_info { 812 /* reset dump register */ 813 u32 *reset_dump_reg_list; 814 u32 *reset_dump_reg_value; 815 int num_regs; 816 817 #ifdef CONFIG_DEV_COREDUMP 818 struct amdgpu_coredump_info *coredump_info; 819 #endif 820 }; 821 822 /* 823 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. 824 */ 825 #define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size) 826 827 struct amdgpu_device { 828 struct device *dev; 829 struct pci_dev *pdev; 830 struct drm_device ddev; 831 832 #ifdef CONFIG_DRM_AMD_ACP 833 struct amdgpu_acp acp; 834 #endif 835 struct amdgpu_hive_info *hive; 836 struct amdgpu_xcp_mgr *xcp_mgr; 837 /* ASIC */ 838 enum amd_asic_type asic_type; 839 uint32_t family; 840 uint32_t rev_id; 841 uint32_t external_rev_id; 842 unsigned long flags; 843 unsigned long apu_flags; 844 int usec_timeout; 845 const struct amdgpu_asic_funcs *asic_funcs; 846 bool shutdown; 847 bool need_swiotlb; 848 bool accel_working; 849 struct notifier_block acpi_nb; 850 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 851 struct debugfs_blob_wrapper debugfs_vbios_blob; 852 struct debugfs_blob_wrapper debugfs_discovery_blob; 853 struct mutex srbm_mutex; 854 /* GRBM index mutex. Protects concurrent access to GRBM index */ 855 struct mutex grbm_idx_mutex; 856 struct dev_pm_domain vga_pm_domain; 857 bool have_disp_power_ref; 858 bool have_atomics_support; 859 860 /* BIOS */ 861 bool is_atom_fw; 862 uint8_t *bios; 863 uint32_t bios_size; 864 uint32_t bios_scratch_reg_offset; 865 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 866 867 /* Register/doorbell mmio */ 868 resource_size_t rmmio_base; 869 resource_size_t rmmio_size; 870 void __iomem *rmmio; 871 /* protects concurrent MM_INDEX/DATA based register access */ 872 spinlock_t mmio_idx_lock; 873 struct amdgpu_mmio_remap rmmio_remap; 874 /* protects concurrent SMC based register access */ 875 spinlock_t smc_idx_lock; 876 amdgpu_rreg_t smc_rreg; 877 amdgpu_wreg_t smc_wreg; 878 /* protects concurrent PCIE register access */ 879 spinlock_t pcie_idx_lock; 880 amdgpu_rreg_t pcie_rreg; 881 amdgpu_wreg_t pcie_wreg; 882 amdgpu_rreg_t pciep_rreg; 883 amdgpu_wreg_t pciep_wreg; 884 amdgpu_rreg_ext_t pcie_rreg_ext; 885 amdgpu_wreg_ext_t pcie_wreg_ext; 886 amdgpu_rreg64_t pcie_rreg64; 887 amdgpu_wreg64_t pcie_wreg64; 888 amdgpu_rreg64_ext_t pcie_rreg64_ext; 889 amdgpu_wreg64_ext_t pcie_wreg64_ext; 890 /* protects concurrent UVD register access */ 891 spinlock_t uvd_ctx_idx_lock; 892 amdgpu_rreg_t uvd_ctx_rreg; 893 amdgpu_wreg_t uvd_ctx_wreg; 894 /* protects concurrent DIDT register access */ 895 spinlock_t didt_idx_lock; 896 amdgpu_rreg_t didt_rreg; 897 amdgpu_wreg_t didt_wreg; 898 /* protects concurrent gc_cac register access */ 899 spinlock_t gc_cac_idx_lock; 900 amdgpu_rreg_t gc_cac_rreg; 901 amdgpu_wreg_t gc_cac_wreg; 902 /* protects concurrent se_cac register access */ 903 spinlock_t se_cac_idx_lock; 904 amdgpu_rreg_t se_cac_rreg; 905 amdgpu_wreg_t se_cac_wreg; 906 /* protects concurrent ENDPOINT (audio) register access */ 907 spinlock_t audio_endpt_idx_lock; 908 amdgpu_block_rreg_t audio_endpt_rreg; 909 amdgpu_block_wreg_t audio_endpt_wreg; 910 struct amdgpu_doorbell doorbell; 911 912 /* clock/pll info */ 913 struct amdgpu_clock clock; 914 915 /* MC */ 916 struct amdgpu_gmc gmc; 917 struct amdgpu_gart gart; 918 dma_addr_t dummy_page_addr; 919 struct amdgpu_vm_manager vm_manager; 920 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 921 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 922 923 /* memory management */ 924 struct amdgpu_mman mman; 925 struct amdgpu_mem_scratch mem_scratch; 926 struct amdgpu_wb wb; 927 atomic64_t num_bytes_moved; 928 atomic64_t num_evictions; 929 atomic64_t num_vram_cpu_page_faults; 930 atomic_t gpu_reset_counter; 931 atomic_t vram_lost_counter; 932 933 /* data for buffer migration throttling */ 934 struct { 935 spinlock_t lock; 936 s64 last_update_us; 937 s64 accum_us; /* accumulated microseconds */ 938 s64 accum_us_vis; /* for visible VRAM */ 939 u32 log2_max_MBps; 940 } mm_stats; 941 942 /* display */ 943 bool enable_virtual_display; 944 struct amdgpu_vkms_output *amdgpu_vkms_output; 945 struct amdgpu_mode_info mode_info; 946 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 947 struct delayed_work hotplug_work; 948 struct amdgpu_irq_src crtc_irq; 949 struct amdgpu_irq_src vline0_irq; 950 struct amdgpu_irq_src vupdate_irq; 951 struct amdgpu_irq_src pageflip_irq; 952 struct amdgpu_irq_src hpd_irq; 953 struct amdgpu_irq_src dmub_trace_irq; 954 struct amdgpu_irq_src dmub_outbox_irq; 955 956 /* rings */ 957 u64 fence_context; 958 unsigned num_rings; 959 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 960 struct dma_fence __rcu *gang_submit; 961 bool ib_pool_ready; 962 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 963 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 964 965 /* interrupts */ 966 struct amdgpu_irq irq; 967 968 /* powerplay */ 969 struct amd_powerplay powerplay; 970 struct amdgpu_pm pm; 971 u64 cg_flags; 972 u32 pg_flags; 973 974 /* nbio */ 975 struct amdgpu_nbio nbio; 976 977 /* hdp */ 978 struct amdgpu_hdp hdp; 979 980 /* smuio */ 981 struct amdgpu_smuio smuio; 982 983 /* mmhub */ 984 struct amdgpu_mmhub mmhub; 985 986 /* gfxhub */ 987 struct amdgpu_gfxhub gfxhub; 988 989 /* gfx */ 990 struct amdgpu_gfx gfx; 991 992 /* sdma */ 993 struct amdgpu_sdma sdma; 994 995 /* lsdma */ 996 struct amdgpu_lsdma lsdma; 997 998 /* uvd */ 999 struct amdgpu_uvd uvd; 1000 1001 /* vce */ 1002 struct amdgpu_vce vce; 1003 1004 /* vcn */ 1005 struct amdgpu_vcn vcn; 1006 1007 /* jpeg */ 1008 struct amdgpu_jpeg jpeg; 1009 1010 /* vpe */ 1011 struct amdgpu_vpe vpe; 1012 1013 /* umsch */ 1014 struct amdgpu_umsch_mm umsch_mm; 1015 bool enable_umsch_mm; 1016 1017 /* firmwares */ 1018 struct amdgpu_firmware firmware; 1019 1020 /* PSP */ 1021 struct psp_context psp; 1022 1023 /* GDS */ 1024 struct amdgpu_gds gds; 1025 1026 /* for userq and VM fences */ 1027 struct amdgpu_seq64 seq64; 1028 1029 /* KFD */ 1030 struct amdgpu_kfd_dev kfd; 1031 1032 /* UMC */ 1033 struct amdgpu_umc umc; 1034 1035 /* display related functionality */ 1036 struct amdgpu_display_manager dm; 1037 1038 /* mes */ 1039 bool enable_mes; 1040 bool enable_mes_kiq; 1041 struct amdgpu_mes mes; 1042 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1043 1044 /* df */ 1045 struct amdgpu_df df; 1046 1047 /* MCA */ 1048 struct amdgpu_mca mca; 1049 1050 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1051 uint32_t harvest_ip_mask; 1052 int num_ip_blocks; 1053 struct mutex mn_lock; 1054 DECLARE_HASHTABLE(mn_hash, 7); 1055 1056 /* tracking pinned memory */ 1057 atomic64_t vram_pin_size; 1058 atomic64_t visible_pin_size; 1059 atomic64_t gart_pin_size; 1060 1061 /* soc15 register offset based on ip, instance and segment */ 1062 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1063 struct amdgpu_ip_map_info ip_map; 1064 1065 /* delayed work_func for deferring clockgating during resume */ 1066 struct delayed_work delayed_init_work; 1067 1068 struct amdgpu_virt virt; 1069 1070 /* link all shadow bo */ 1071 struct list_head shadow_list; 1072 struct mutex shadow_list_lock; 1073 1074 /* record hw reset is performed */ 1075 bool has_hw_reset; 1076 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1077 1078 /* s3/s4 mask */ 1079 bool in_suspend; 1080 bool in_s3; 1081 bool in_s4; 1082 bool in_s0ix; 1083 1084 enum pp_mp1_state mp1_state; 1085 struct amdgpu_doorbell_index doorbell_index; 1086 1087 struct mutex notifier_lock; 1088 1089 int asic_reset_res; 1090 struct work_struct xgmi_reset_work; 1091 struct list_head reset_list; 1092 1093 long gfx_timeout; 1094 long sdma_timeout; 1095 long video_timeout; 1096 long compute_timeout; 1097 1098 uint64_t unique_id; 1099 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1100 1101 /* enable runtime pm on the device */ 1102 bool in_runpm; 1103 bool has_pr3; 1104 1105 bool ucode_sysfs_en; 1106 1107 struct amdgpu_fru_info *fru_info; 1108 atomic_t throttling_logging_enabled; 1109 struct ratelimit_state throttling_logging_rs; 1110 uint32_t ras_hw_enabled; 1111 uint32_t ras_enabled; 1112 1113 bool no_hw_access; 1114 struct pci_saved_state *pci_state; 1115 pci_channel_state_t pci_channel_state; 1116 1117 /* Track auto wait count on s_barrier settings */ 1118 bool barrier_has_auto_waitcnt; 1119 1120 struct amdgpu_reset_control *reset_cntl; 1121 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1122 1123 bool ram_is_direct_mapped; 1124 1125 struct list_head ras_list; 1126 1127 struct ip_discovery_top *ip_top; 1128 1129 struct amdgpu_reset_domain *reset_domain; 1130 1131 struct mutex benchmark_mutex; 1132 1133 struct amdgpu_reset_info reset_info; 1134 1135 bool scpm_enabled; 1136 uint32_t scpm_status; 1137 1138 struct work_struct reset_work; 1139 1140 bool job_hang; 1141 bool dc_enabled; 1142 /* Mask of active clusters */ 1143 uint32_t aid_mask; 1144 1145 /* Debug */ 1146 bool debug_vm; 1147 bool debug_largebar; 1148 bool debug_disable_soft_recovery; 1149 }; 1150 1151 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1152 uint8_t ip, uint8_t inst) 1153 { 1154 /* This considers only major/minor/rev and ignores 1155 * subrevision/variant fields. 1156 */ 1157 return adev->ip_versions[ip][inst] & ~0xFFU; 1158 } 1159 1160 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1161 uint8_t ip, uint8_t inst) 1162 { 1163 /* This returns full version - major/minor/rev/variant/subrevision */ 1164 return adev->ip_versions[ip][inst]; 1165 } 1166 1167 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1168 { 1169 return container_of(ddev, struct amdgpu_device, ddev); 1170 } 1171 1172 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1173 { 1174 return &adev->ddev; 1175 } 1176 1177 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1178 { 1179 return container_of(bdev, struct amdgpu_device, mman.bdev); 1180 } 1181 1182 int amdgpu_device_init(struct amdgpu_device *adev, 1183 uint32_t flags); 1184 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1185 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1186 1187 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1188 1189 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1190 void *buf, size_t size, bool write); 1191 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1192 void *buf, size_t size, bool write); 1193 1194 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1195 void *buf, size_t size, bool write); 1196 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1197 uint32_t inst, uint32_t reg_addr, char reg_name[], 1198 uint32_t expected_value, uint32_t mask); 1199 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1200 uint32_t reg, uint32_t acc_flags); 1201 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1202 u64 reg_addr); 1203 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1204 uint32_t reg, uint32_t acc_flags, 1205 uint32_t xcc_id); 1206 void amdgpu_device_wreg(struct amdgpu_device *adev, 1207 uint32_t reg, uint32_t v, 1208 uint32_t acc_flags); 1209 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1210 u64 reg_addr, u32 reg_data); 1211 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1212 uint32_t reg, uint32_t v, 1213 uint32_t acc_flags, 1214 uint32_t xcc_id); 1215 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1216 uint32_t reg, uint32_t v, uint32_t xcc_id); 1217 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1218 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1219 1220 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1221 u32 reg_addr); 1222 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1223 u32 reg_addr); 1224 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1225 u64 reg_addr); 1226 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1227 u32 reg_addr, u32 reg_data); 1228 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1229 u32 reg_addr, u64 reg_data); 1230 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1231 u64 reg_addr, u64 reg_data); 1232 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1233 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1234 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1235 1236 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1237 1238 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1239 struct amdgpu_reset_context *reset_context); 1240 1241 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1242 struct amdgpu_reset_context *reset_context); 1243 1244 int emu_soc_asic_init(struct amdgpu_device *adev); 1245 1246 /* 1247 * Registers read & write functions. 1248 */ 1249 #define AMDGPU_REGS_NO_KIQ (1<<1) 1250 #define AMDGPU_REGS_RLC (1<<2) 1251 1252 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1253 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1254 1255 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1256 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1257 1258 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1259 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1260 1261 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1262 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1263 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1264 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1265 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1266 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1267 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1268 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1269 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1270 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1271 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1272 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1273 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1274 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1275 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1276 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1277 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1278 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1279 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1280 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1281 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1282 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1283 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1284 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1285 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1286 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1287 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1288 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1289 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1290 #define WREG32_P(reg, val, mask) \ 1291 do { \ 1292 uint32_t tmp_ = RREG32(reg); \ 1293 tmp_ &= (mask); \ 1294 tmp_ |= ((val) & ~(mask)); \ 1295 WREG32(reg, tmp_); \ 1296 } while (0) 1297 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1298 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1299 #define WREG32_PLL_P(reg, val, mask) \ 1300 do { \ 1301 uint32_t tmp_ = RREG32_PLL(reg); \ 1302 tmp_ &= (mask); \ 1303 tmp_ |= ((val) & ~(mask)); \ 1304 WREG32_PLL(reg, tmp_); \ 1305 } while (0) 1306 1307 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1308 do { \ 1309 u32 tmp = RREG32_SMC(_Reg); \ 1310 tmp &= (_Mask); \ 1311 tmp |= ((_Val) & ~(_Mask)); \ 1312 WREG32_SMC(_Reg, tmp); \ 1313 } while (0) 1314 1315 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1316 1317 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1318 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1319 1320 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1321 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1322 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1323 1324 #define REG_GET_FIELD(value, reg, field) \ 1325 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1326 1327 #define WREG32_FIELD(reg, field, val) \ 1328 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1329 1330 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1331 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1332 1333 /* 1334 * BIOS helpers. 1335 */ 1336 #define RBIOS8(i) (adev->bios[i]) 1337 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1338 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1339 1340 /* 1341 * ASICs macro. 1342 */ 1343 #define amdgpu_asic_set_vga_state(adev, state) \ 1344 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1345 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1346 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1347 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1348 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1349 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1350 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1351 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1352 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1353 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1354 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1355 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1356 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1357 #define amdgpu_asic_flush_hdp(adev, r) \ 1358 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1359 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1360 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \ 1361 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0)) 1362 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1363 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1364 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1365 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1366 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1367 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1368 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1369 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1370 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1371 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1372 1373 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1374 1375 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1376 #define for_each_inst(i, inst_mask) \ 1377 for (i = ffs(inst_mask); i-- != 0; \ 1378 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1379 1380 /* Common functions */ 1381 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1382 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1383 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1384 struct amdgpu_job *job, 1385 struct amdgpu_reset_context *reset_context); 1386 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1387 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1388 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1389 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1390 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1391 1392 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1393 u64 num_vis_bytes); 1394 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1395 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1396 const u32 *registers, 1397 const u32 array_size); 1398 1399 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1400 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1401 bool amdgpu_device_supports_px(struct drm_device *dev); 1402 bool amdgpu_device_supports_boco(struct drm_device *dev); 1403 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1404 bool amdgpu_device_supports_baco(struct drm_device *dev); 1405 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1406 struct amdgpu_device *peer_adev); 1407 int amdgpu_device_baco_enter(struct drm_device *dev); 1408 int amdgpu_device_baco_exit(struct drm_device *dev); 1409 1410 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1411 struct amdgpu_ring *ring); 1412 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1413 struct amdgpu_ring *ring); 1414 1415 void amdgpu_device_halt(struct amdgpu_device *adev); 1416 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1417 u32 reg); 1418 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1419 u32 reg, u32 v); 1420 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1421 struct dma_fence *gang); 1422 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1423 1424 /* atpx handler */ 1425 #if defined(CONFIG_VGA_SWITCHEROO) 1426 void amdgpu_register_atpx_handler(void); 1427 void amdgpu_unregister_atpx_handler(void); 1428 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1429 bool amdgpu_is_atpx_hybrid(void); 1430 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1431 bool amdgpu_has_atpx(void); 1432 #else 1433 static inline void amdgpu_register_atpx_handler(void) {} 1434 static inline void amdgpu_unregister_atpx_handler(void) {} 1435 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1436 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1437 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1438 static inline bool amdgpu_has_atpx(void) { return false; } 1439 #endif 1440 1441 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1442 void *amdgpu_atpx_get_dhandle(void); 1443 #else 1444 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1445 #endif 1446 1447 /* 1448 * KMS 1449 */ 1450 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1451 extern const int amdgpu_max_kms_ioctl; 1452 1453 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1454 void amdgpu_driver_unload_kms(struct drm_device *dev); 1455 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1456 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1457 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1458 struct drm_file *file_priv); 1459 void amdgpu_driver_release_kms(struct drm_device *dev); 1460 1461 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1462 int amdgpu_device_prepare(struct drm_device *dev); 1463 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1464 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1465 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1466 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1467 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1468 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1469 struct drm_file *filp); 1470 1471 /* 1472 * functions used by amdgpu_encoder.c 1473 */ 1474 struct amdgpu_afmt_acr { 1475 u32 clock; 1476 1477 int n_32khz; 1478 int cts_32khz; 1479 1480 int n_44_1khz; 1481 int cts_44_1khz; 1482 1483 int n_48khz; 1484 int cts_48khz; 1485 1486 }; 1487 1488 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1489 1490 /* amdgpu_acpi.c */ 1491 1492 struct amdgpu_numa_info { 1493 uint64_t size; 1494 int pxm; 1495 int nid; 1496 }; 1497 1498 /* ATCS Device/Driver State */ 1499 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1500 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1501 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1502 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1503 1504 #if defined(CONFIG_ACPI) 1505 int amdgpu_acpi_init(struct amdgpu_device *adev); 1506 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1507 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1508 bool amdgpu_acpi_is_power_shift_control_supported(void); 1509 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1510 u8 perf_req, bool advertise); 1511 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1512 u8 dev_state, bool drv_state); 1513 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1514 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1515 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1516 u64 *tmr_size); 1517 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1518 struct amdgpu_numa_info *numa_info); 1519 1520 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1521 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1522 void amdgpu_acpi_detect(void); 1523 void amdgpu_acpi_release(void); 1524 #else 1525 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1526 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1527 u64 *tmr_offset, u64 *tmr_size) 1528 { 1529 return -EINVAL; 1530 } 1531 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1532 int xcc_id, 1533 struct amdgpu_numa_info *numa_info) 1534 { 1535 return -EINVAL; 1536 } 1537 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1538 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1539 static inline void amdgpu_acpi_detect(void) { } 1540 static inline void amdgpu_acpi_release(void) { } 1541 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1542 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1543 u8 dev_state, bool drv_state) { return 0; } 1544 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1545 enum amdgpu_ss ss_state) { return 0; } 1546 #endif 1547 1548 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1549 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1550 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1551 #else 1552 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1553 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1554 #endif 1555 1556 #if defined(CONFIG_DRM_AMD_DC) 1557 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1558 #else 1559 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1560 #endif 1561 1562 1563 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1564 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1565 1566 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1567 pci_channel_state_t state); 1568 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1569 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1570 void amdgpu_pci_resume(struct pci_dev *pdev); 1571 1572 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1573 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1574 1575 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1576 1577 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1578 enum amd_clockgating_state state); 1579 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1580 enum amd_powergating_state state); 1581 1582 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1583 { 1584 return amdgpu_gpu_recovery != 0 && 1585 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1586 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1587 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1588 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1589 } 1590 1591 #include "amdgpu_object.h" 1592 1593 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1594 { 1595 return adev->gmc.tmz_enabled; 1596 } 1597 1598 int amdgpu_in_reset(struct amdgpu_device *adev); 1599 1600 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1601 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1602 extern const struct attribute_group amdgpu_flash_attr_group; 1603 1604 #endif 1605