1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drm_gem.h> 46 #include <drm/amdgpu_drm.h> 47 48 #include "amd_shared.h" 49 #include "amdgpu_family.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 /* 57 * Modules parameters. 58 */ 59 extern int amdgpu_modeset; 60 extern int amdgpu_vram_limit; 61 extern int amdgpu_gart_size; 62 extern int amdgpu_benchmarking; 63 extern int amdgpu_testing; 64 extern int amdgpu_audio; 65 extern int amdgpu_disp_priority; 66 extern int amdgpu_hw_i2c; 67 extern int amdgpu_pcie_gen2; 68 extern int amdgpu_msi; 69 extern int amdgpu_lockup_timeout; 70 extern int amdgpu_dpm; 71 extern int amdgpu_smc_load_fw; 72 extern int amdgpu_aspm; 73 extern int amdgpu_runtime_pm; 74 extern int amdgpu_hard_reset; 75 extern unsigned amdgpu_ip_block_mask; 76 extern int amdgpu_bapm; 77 extern int amdgpu_deep_color; 78 extern int amdgpu_vm_size; 79 extern int amdgpu_vm_block_size; 80 81 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 82 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 83 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 84 #define AMDGPU_IB_POOL_SIZE 16 85 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 86 #define AMDGPUFB_CONN_LIMIT 4 87 #define AMDGPU_BIOS_NUM_SCRATCH 8 88 89 /* max number of rings */ 90 #define AMDGPU_MAX_RINGS 16 91 #define AMDGPU_MAX_GFX_RINGS 1 92 #define AMDGPU_MAX_COMPUTE_RINGS 8 93 #define AMDGPU_MAX_VCE_RINGS 2 94 95 /* number of hw syncs before falling back on blocking */ 96 #define AMDGPU_NUM_SYNCS 4 97 98 /* hardcode that limit for now */ 99 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 100 101 /* hard reset data */ 102 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 103 104 /* reset flags */ 105 #define AMDGPU_RESET_GFX (1 << 0) 106 #define AMDGPU_RESET_COMPUTE (1 << 1) 107 #define AMDGPU_RESET_DMA (1 << 2) 108 #define AMDGPU_RESET_CP (1 << 3) 109 #define AMDGPU_RESET_GRBM (1 << 4) 110 #define AMDGPU_RESET_DMA1 (1 << 5) 111 #define AMDGPU_RESET_RLC (1 << 6) 112 #define AMDGPU_RESET_SEM (1 << 7) 113 #define AMDGPU_RESET_IH (1 << 8) 114 #define AMDGPU_RESET_VMC (1 << 9) 115 #define AMDGPU_RESET_MC (1 << 10) 116 #define AMDGPU_RESET_DISPLAY (1 << 11) 117 #define AMDGPU_RESET_UVD (1 << 12) 118 #define AMDGPU_RESET_VCE (1 << 13) 119 #define AMDGPU_RESET_VCE1 (1 << 14) 120 121 /* CG block flags */ 122 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 123 #define AMDGPU_CG_BLOCK_MC (1 << 1) 124 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 125 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 126 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 127 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 128 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 129 130 /* CG flags */ 131 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 132 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 133 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 134 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 135 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 136 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 137 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 138 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 139 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 140 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 141 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 142 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 143 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 144 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 145 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 146 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 147 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 148 149 /* PG flags */ 150 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 151 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 152 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 153 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 154 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 155 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 156 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 157 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 158 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 159 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 160 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 161 162 /* GFX current status */ 163 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 164 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 165 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 166 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 167 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 168 169 /* max cursor sizes (in pixels) */ 170 #define CIK_CURSOR_WIDTH 128 171 #define CIK_CURSOR_HEIGHT 128 172 173 struct amdgpu_device; 174 struct amdgpu_fence; 175 struct amdgpu_ib; 176 struct amdgpu_vm; 177 struct amdgpu_ring; 178 struct amdgpu_semaphore; 179 struct amdgpu_cs_parser; 180 struct amdgpu_irq_src; 181 182 enum amdgpu_cp_irq { 183 AMDGPU_CP_IRQ_GFX_EOP = 0, 184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 192 193 AMDGPU_CP_IRQ_LAST 194 }; 195 196 enum amdgpu_sdma_irq { 197 AMDGPU_SDMA_IRQ_TRAP0 = 0, 198 AMDGPU_SDMA_IRQ_TRAP1, 199 200 AMDGPU_SDMA_IRQ_LAST 201 }; 202 203 enum amdgpu_thermal_irq { 204 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 205 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 206 207 AMDGPU_THERMAL_IRQ_LAST 208 }; 209 210 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 211 enum amd_ip_block_type block_type, 212 enum amd_clockgating_state state); 213 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 214 enum amd_ip_block_type block_type, 215 enum amd_powergating_state state); 216 217 struct amdgpu_ip_block_version { 218 enum amd_ip_block_type type; 219 u32 major; 220 u32 minor; 221 u32 rev; 222 const struct amd_ip_funcs *funcs; 223 }; 224 225 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 226 enum amd_ip_block_type type, 227 u32 major, u32 minor); 228 229 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 230 struct amdgpu_device *adev, 231 enum amd_ip_block_type type); 232 233 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 234 struct amdgpu_buffer_funcs { 235 /* maximum bytes in a single operation */ 236 uint32_t copy_max_bytes; 237 238 /* number of dw to reserve per operation */ 239 unsigned copy_num_dw; 240 241 /* used for buffer migration */ 242 void (*emit_copy_buffer)(struct amdgpu_ring *ring, 243 /* src addr in bytes */ 244 uint64_t src_offset, 245 /* dst addr in bytes */ 246 uint64_t dst_offset, 247 /* number of byte to transfer */ 248 uint32_t byte_count); 249 250 /* maximum bytes in a single operation */ 251 uint32_t fill_max_bytes; 252 253 /* number of dw to reserve per operation */ 254 unsigned fill_num_dw; 255 256 /* used for buffer clearing */ 257 void (*emit_fill_buffer)(struct amdgpu_ring *ring, 258 /* value to write to memory */ 259 uint32_t src_data, 260 /* dst addr in bytes */ 261 uint64_t dst_offset, 262 /* number of byte to fill */ 263 uint32_t byte_count); 264 }; 265 266 /* provided by hw blocks that can write ptes, e.g., sdma */ 267 struct amdgpu_vm_pte_funcs { 268 /* copy pte entries from GART */ 269 void (*copy_pte)(struct amdgpu_ib *ib, 270 uint64_t pe, uint64_t src, 271 unsigned count); 272 /* write pte one entry at a time with addr mapping */ 273 void (*write_pte)(struct amdgpu_ib *ib, 274 uint64_t pe, 275 uint64_t addr, unsigned count, 276 uint32_t incr, uint32_t flags); 277 /* for linear pte/pde updates without addr mapping */ 278 void (*set_pte_pde)(struct amdgpu_ib *ib, 279 uint64_t pe, 280 uint64_t addr, unsigned count, 281 uint32_t incr, uint32_t flags); 282 /* pad the indirect buffer to the necessary number of dw */ 283 void (*pad_ib)(struct amdgpu_ib *ib); 284 }; 285 286 /* provided by the gmc block */ 287 struct amdgpu_gart_funcs { 288 /* flush the vm tlb via mmio */ 289 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 290 uint32_t vmid); 291 /* write pte/pde updates using the cpu */ 292 int (*set_pte_pde)(struct amdgpu_device *adev, 293 void *cpu_pt_addr, /* cpu addr of page table */ 294 uint32_t gpu_page_idx, /* pte/pde to update */ 295 uint64_t addr, /* addr to write into pte/pde */ 296 uint32_t flags); /* access flags */ 297 }; 298 299 /* provided by the ih block */ 300 struct amdgpu_ih_funcs { 301 /* ring read/write ptr handling, called from interrupt context */ 302 u32 (*get_wptr)(struct amdgpu_device *adev); 303 void (*decode_iv)(struct amdgpu_device *adev, 304 struct amdgpu_iv_entry *entry); 305 void (*set_rptr)(struct amdgpu_device *adev); 306 }; 307 308 /* provided by hw blocks that expose a ring buffer for commands */ 309 struct amdgpu_ring_funcs { 310 /* ring read/write ptr handling */ 311 u32 (*get_rptr)(struct amdgpu_ring *ring); 312 u32 (*get_wptr)(struct amdgpu_ring *ring); 313 void (*set_wptr)(struct amdgpu_ring *ring); 314 /* validating and patching of IBs */ 315 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 316 /* command emit functions */ 317 void (*emit_ib)(struct amdgpu_ring *ring, 318 struct amdgpu_ib *ib); 319 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 320 uint64_t seq, unsigned flags); 321 bool (*emit_semaphore)(struct amdgpu_ring *ring, 322 struct amdgpu_semaphore *semaphore, 323 bool emit_wait); 324 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 325 uint64_t pd_addr); 326 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 327 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 328 uint32_t gds_base, uint32_t gds_size, 329 uint32_t gws_base, uint32_t gws_size, 330 uint32_t oa_base, uint32_t oa_size); 331 /* testing functions */ 332 int (*test_ring)(struct amdgpu_ring *ring); 333 int (*test_ib)(struct amdgpu_ring *ring); 334 bool (*is_lockup)(struct amdgpu_ring *ring); 335 }; 336 337 /* 338 * BIOS. 339 */ 340 bool amdgpu_get_bios(struct amdgpu_device *adev); 341 bool amdgpu_read_bios(struct amdgpu_device *adev); 342 343 /* 344 * Dummy page 345 */ 346 struct amdgpu_dummy_page { 347 struct page *page; 348 dma_addr_t addr; 349 }; 350 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 351 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 352 353 354 /* 355 * Clocks 356 */ 357 358 #define AMDGPU_MAX_PPLL 3 359 360 struct amdgpu_clock { 361 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 362 struct amdgpu_pll spll; 363 struct amdgpu_pll mpll; 364 /* 10 Khz units */ 365 uint32_t default_mclk; 366 uint32_t default_sclk; 367 uint32_t default_dispclk; 368 uint32_t current_dispclk; 369 uint32_t dp_extclk; 370 uint32_t max_pixel_clock; 371 }; 372 373 /* 374 * Fences. 375 */ 376 struct amdgpu_fence_driver { 377 struct amdgpu_ring *ring; 378 uint64_t gpu_addr; 379 volatile uint32_t *cpu_addr; 380 /* sync_seq is protected by ring emission lock */ 381 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 382 atomic64_t last_seq; 383 bool initialized; 384 bool delayed_irq; 385 struct amdgpu_irq_src *irq_src; 386 unsigned irq_type; 387 struct delayed_work lockup_work; 388 }; 389 390 /* some special values for the owner field */ 391 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 392 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 393 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 394 395 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 396 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 397 398 struct amdgpu_fence { 399 struct fence base; 400 401 /* RB, DMA, etc. */ 402 struct amdgpu_ring *ring; 403 uint64_t seq; 404 405 /* filp or special value for fence creator */ 406 void *owner; 407 408 wait_queue_t fence_wake; 409 }; 410 411 struct amdgpu_user_fence { 412 /* write-back bo */ 413 struct amdgpu_bo *bo; 414 /* write-back address offset to bo start */ 415 uint32_t offset; 416 }; 417 418 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 419 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 420 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 421 422 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 423 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 424 struct amdgpu_irq_src *irq_src, 425 unsigned irq_type); 426 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 427 struct amdgpu_fence **fence); 428 int amdgpu_fence_recreate(struct amdgpu_ring *ring, void *owner, 429 uint64_t seq, struct amdgpu_fence **fence); 430 void amdgpu_fence_process(struct amdgpu_ring *ring); 431 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 432 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 433 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 434 435 bool amdgpu_fence_signaled(struct amdgpu_fence *fence); 436 int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible); 437 int amdgpu_fence_wait_any(struct amdgpu_device *adev, 438 struct amdgpu_fence **fences, 439 bool intr); 440 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); 441 void amdgpu_fence_unref(struct amdgpu_fence **fence); 442 443 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 444 struct amdgpu_ring *ring); 445 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 446 struct amdgpu_ring *ring); 447 448 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, 449 struct amdgpu_fence *b) 450 { 451 if (!a) { 452 return b; 453 } 454 455 if (!b) { 456 return a; 457 } 458 459 BUG_ON(a->ring != b->ring); 460 461 if (a->seq > b->seq) { 462 return a; 463 } else { 464 return b; 465 } 466 } 467 468 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, 469 struct amdgpu_fence *b) 470 { 471 if (!a) { 472 return false; 473 } 474 475 if (!b) { 476 return true; 477 } 478 479 BUG_ON(a->ring != b->ring); 480 481 return a->seq < b->seq; 482 } 483 484 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 485 void *owner, struct amdgpu_fence **fence); 486 487 /* 488 * TTM. 489 */ 490 struct amdgpu_mman { 491 struct ttm_bo_global_ref bo_global_ref; 492 struct drm_global_reference mem_global_ref; 493 struct ttm_bo_device bdev; 494 bool mem_global_referenced; 495 bool initialized; 496 497 #if defined(CONFIG_DEBUG_FS) 498 struct dentry *vram; 499 struct dentry *gtt; 500 #endif 501 502 /* buffer handling */ 503 const struct amdgpu_buffer_funcs *buffer_funcs; 504 struct amdgpu_ring *buffer_funcs_ring; 505 }; 506 507 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 508 uint64_t src_offset, 509 uint64_t dst_offset, 510 uint32_t byte_count, 511 struct reservation_object *resv, 512 struct amdgpu_fence **fence); 513 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 514 515 struct amdgpu_bo_list_entry { 516 struct amdgpu_bo *robj; 517 struct ttm_validate_buffer tv; 518 struct amdgpu_bo_va *bo_va; 519 unsigned prefered_domains; 520 unsigned allowed_domains; 521 uint32_t priority; 522 }; 523 524 struct amdgpu_bo_va_mapping { 525 struct list_head list; 526 struct interval_tree_node it; 527 uint64_t offset; 528 uint32_t flags; 529 }; 530 531 /* bo virtual addresses in a specific vm */ 532 struct amdgpu_bo_va { 533 /* protected by bo being reserved */ 534 struct list_head bo_list; 535 uint64_t addr; 536 struct amdgpu_fence *last_pt_update; 537 unsigned ref_count; 538 539 /* protected by vm mutex */ 540 struct list_head mappings; 541 struct list_head vm_status; 542 543 /* constant after initialization */ 544 struct amdgpu_vm *vm; 545 struct amdgpu_bo *bo; 546 }; 547 548 #define AMDGPU_GEM_DOMAIN_MAX 0x3 549 550 struct amdgpu_bo { 551 /* Protected by gem.mutex */ 552 struct list_head list; 553 /* Protected by tbo.reserved */ 554 u32 initial_domain; 555 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 556 struct ttm_placement placement; 557 struct ttm_buffer_object tbo; 558 struct ttm_bo_kmap_obj kmap; 559 u64 flags; 560 unsigned pin_count; 561 void *kptr; 562 u64 tiling_flags; 563 u64 metadata_flags; 564 void *metadata; 565 u32 metadata_size; 566 /* list of all virtual address to which this bo 567 * is associated to 568 */ 569 struct list_head va; 570 /* Constant after initialization */ 571 struct amdgpu_device *adev; 572 struct drm_gem_object gem_base; 573 574 struct ttm_bo_kmap_obj dma_buf_vmap; 575 pid_t pid; 576 struct amdgpu_mn *mn; 577 struct list_head mn_list; 578 }; 579 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 580 581 void amdgpu_gem_object_free(struct drm_gem_object *obj); 582 int amdgpu_gem_object_open(struct drm_gem_object *obj, 583 struct drm_file *file_priv); 584 void amdgpu_gem_object_close(struct drm_gem_object *obj, 585 struct drm_file *file_priv); 586 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 587 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 588 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 589 struct dma_buf_attachment *attach, 590 struct sg_table *sg); 591 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 592 struct drm_gem_object *gobj, 593 int flags); 594 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 595 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 596 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 597 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 598 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 599 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 600 601 /* sub-allocation manager, it has to be protected by another lock. 602 * By conception this is an helper for other part of the driver 603 * like the indirect buffer or semaphore, which both have their 604 * locking. 605 * 606 * Principe is simple, we keep a list of sub allocation in offset 607 * order (first entry has offset == 0, last entry has the highest 608 * offset). 609 * 610 * When allocating new object we first check if there is room at 611 * the end total_size - (last_object_offset + last_object_size) >= 612 * alloc_size. If so we allocate new object there. 613 * 614 * When there is not enough room at the end, we start waiting for 615 * each sub object until we reach object_offset+object_size >= 616 * alloc_size, this object then become the sub object we return. 617 * 618 * Alignment can't be bigger than page size. 619 * 620 * Hole are not considered for allocation to keep things simple. 621 * Assumption is that there won't be hole (all object on same 622 * alignment). 623 */ 624 struct amdgpu_sa_manager { 625 wait_queue_head_t wq; 626 struct amdgpu_bo *bo; 627 struct list_head *hole; 628 struct list_head flist[AMDGPU_MAX_RINGS]; 629 struct list_head olist; 630 unsigned size; 631 uint64_t gpu_addr; 632 void *cpu_ptr; 633 uint32_t domain; 634 uint32_t align; 635 }; 636 637 struct amdgpu_sa_bo; 638 639 /* sub-allocation buffer */ 640 struct amdgpu_sa_bo { 641 struct list_head olist; 642 struct list_head flist; 643 struct amdgpu_sa_manager *manager; 644 unsigned soffset; 645 unsigned eoffset; 646 struct amdgpu_fence *fence; 647 }; 648 649 /* 650 * GEM objects. 651 */ 652 struct amdgpu_gem { 653 struct mutex mutex; 654 struct list_head objects; 655 }; 656 657 int amdgpu_gem_init(struct amdgpu_device *adev); 658 void amdgpu_gem_fini(struct amdgpu_device *adev); 659 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 660 int alignment, u32 initial_domain, 661 u64 flags, bool kernel, 662 struct drm_gem_object **obj); 663 664 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 665 struct drm_device *dev, 666 struct drm_mode_create_dumb *args); 667 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 668 struct drm_device *dev, 669 uint32_t handle, uint64_t *offset_p); 670 671 /* 672 * Semaphores. 673 */ 674 struct amdgpu_semaphore { 675 struct amdgpu_sa_bo *sa_bo; 676 signed waiters; 677 uint64_t gpu_addr; 678 }; 679 680 int amdgpu_semaphore_create(struct amdgpu_device *adev, 681 struct amdgpu_semaphore **semaphore); 682 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 683 struct amdgpu_semaphore *semaphore); 684 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 685 struct amdgpu_semaphore *semaphore); 686 void amdgpu_semaphore_free(struct amdgpu_device *adev, 687 struct amdgpu_semaphore **semaphore, 688 struct amdgpu_fence *fence); 689 690 /* 691 * Synchronization 692 */ 693 struct amdgpu_sync { 694 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 695 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; 696 struct amdgpu_fence *last_vm_update; 697 }; 698 699 void amdgpu_sync_create(struct amdgpu_sync *sync); 700 void amdgpu_sync_fence(struct amdgpu_sync *sync, 701 struct amdgpu_fence *fence); 702 int amdgpu_sync_resv(struct amdgpu_device *adev, 703 struct amdgpu_sync *sync, 704 struct reservation_object *resv, 705 void *owner); 706 int amdgpu_sync_rings(struct amdgpu_sync *sync, 707 struct amdgpu_ring *ring); 708 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 709 struct amdgpu_fence *fence); 710 711 /* 712 * GART structures, functions & helpers 713 */ 714 struct amdgpu_mc; 715 716 #define AMDGPU_GPU_PAGE_SIZE 4096 717 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 718 #define AMDGPU_GPU_PAGE_SHIFT 12 719 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 720 721 struct amdgpu_gart { 722 dma_addr_t table_addr; 723 struct amdgpu_bo *robj; 724 void *ptr; 725 unsigned num_gpu_pages; 726 unsigned num_cpu_pages; 727 unsigned table_size; 728 struct page **pages; 729 dma_addr_t *pages_addr; 730 bool ready; 731 const struct amdgpu_gart_funcs *gart_funcs; 732 }; 733 734 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 735 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 736 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 737 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 738 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 739 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 740 int amdgpu_gart_init(struct amdgpu_device *adev); 741 void amdgpu_gart_fini(struct amdgpu_device *adev); 742 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 743 int pages); 744 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 745 int pages, struct page **pagelist, 746 dma_addr_t *dma_addr, uint32_t flags); 747 748 /* 749 * GPU MC structures, functions & helpers 750 */ 751 struct amdgpu_mc { 752 resource_size_t aper_size; 753 resource_size_t aper_base; 754 resource_size_t agp_base; 755 /* for some chips with <= 32MB we need to lie 756 * about vram size near mc fb location */ 757 u64 mc_vram_size; 758 u64 visible_vram_size; 759 u64 gtt_size; 760 u64 gtt_start; 761 u64 gtt_end; 762 u64 vram_start; 763 u64 vram_end; 764 unsigned vram_width; 765 u64 real_vram_size; 766 int vram_mtrr; 767 u64 gtt_base_align; 768 u64 mc_mask; 769 const struct firmware *fw; /* MC firmware */ 770 uint32_t fw_version; 771 struct amdgpu_irq_src vm_fault; 772 uint32_t vram_type; 773 }; 774 775 /* 776 * GPU doorbell structures, functions & helpers 777 */ 778 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 779 { 780 AMDGPU_DOORBELL_KIQ = 0x000, 781 AMDGPU_DOORBELL_HIQ = 0x001, 782 AMDGPU_DOORBELL_DIQ = 0x002, 783 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 784 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 785 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 786 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 787 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 788 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 789 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 790 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 791 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 792 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 793 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 794 AMDGPU_DOORBELL_IH = 0x1E8, 795 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 796 AMDGPU_DOORBELL_INVALID = 0xFFFF 797 } AMDGPU_DOORBELL_ASSIGNMENT; 798 799 struct amdgpu_doorbell { 800 /* doorbell mmio */ 801 resource_size_t base; 802 resource_size_t size; 803 u32 __iomem *ptr; 804 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 805 }; 806 807 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 808 phys_addr_t *aperture_base, 809 size_t *aperture_size, 810 size_t *start_offset); 811 812 /* 813 * IRQS. 814 */ 815 816 struct amdgpu_flip_work { 817 struct work_struct flip_work; 818 struct work_struct unpin_work; 819 struct amdgpu_device *adev; 820 int crtc_id; 821 uint64_t base; 822 struct drm_pending_vblank_event *event; 823 struct amdgpu_bo *old_rbo; 824 struct fence *fence; 825 }; 826 827 828 /* 829 * CP & rings. 830 */ 831 832 struct amdgpu_ib { 833 struct amdgpu_sa_bo *sa_bo; 834 uint32_t length_dw; 835 uint64_t gpu_addr; 836 uint32_t *ptr; 837 struct amdgpu_ring *ring; 838 struct amdgpu_fence *fence; 839 struct amdgpu_user_fence *user; 840 struct amdgpu_vm *vm; 841 struct amdgpu_ctx *ctx; 842 struct amdgpu_sync sync; 843 uint32_t gds_base, gds_size; 844 uint32_t gws_base, gws_size; 845 uint32_t oa_base, oa_size; 846 uint32_t flags; 847 }; 848 849 enum amdgpu_ring_type { 850 AMDGPU_RING_TYPE_GFX, 851 AMDGPU_RING_TYPE_COMPUTE, 852 AMDGPU_RING_TYPE_SDMA, 853 AMDGPU_RING_TYPE_UVD, 854 AMDGPU_RING_TYPE_VCE 855 }; 856 857 struct amdgpu_ring { 858 struct amdgpu_device *adev; 859 const struct amdgpu_ring_funcs *funcs; 860 struct amdgpu_fence_driver fence_drv; 861 862 struct mutex *ring_lock; 863 struct amdgpu_bo *ring_obj; 864 volatile uint32_t *ring; 865 unsigned rptr_offs; 866 u64 next_rptr_gpu_addr; 867 volatile u32 *next_rptr_cpu_addr; 868 unsigned wptr; 869 unsigned wptr_old; 870 unsigned ring_size; 871 unsigned ring_free_dw; 872 int count_dw; 873 atomic_t last_rptr; 874 atomic64_t last_activity; 875 uint64_t gpu_addr; 876 uint32_t align_mask; 877 uint32_t ptr_mask; 878 bool ready; 879 u32 nop; 880 u32 idx; 881 u64 last_semaphore_signal_addr; 882 u64 last_semaphore_wait_addr; 883 u32 me; 884 u32 pipe; 885 u32 queue; 886 struct amdgpu_bo *mqd_obj; 887 u32 doorbell_index; 888 bool use_doorbell; 889 unsigned wptr_offs; 890 unsigned next_rptr_offs; 891 unsigned fence_offs; 892 struct amdgpu_ctx *current_ctx; 893 enum amdgpu_ring_type type; 894 char name[16]; 895 }; 896 897 /* 898 * VM 899 */ 900 901 /* maximum number of VMIDs */ 902 #define AMDGPU_NUM_VM 16 903 904 /* number of entries in page table */ 905 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 906 907 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 908 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 909 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 910 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 911 912 #define AMDGPU_PTE_VALID (1 << 0) 913 #define AMDGPU_PTE_SYSTEM (1 << 1) 914 #define AMDGPU_PTE_SNOOPED (1 << 2) 915 916 /* VI only */ 917 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 918 919 #define AMDGPU_PTE_READABLE (1 << 5) 920 #define AMDGPU_PTE_WRITEABLE (1 << 6) 921 922 /* PTE (Page Table Entry) fragment field for different page sizes */ 923 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 924 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 925 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 926 927 struct amdgpu_vm_pt { 928 struct amdgpu_bo *bo; 929 uint64_t addr; 930 }; 931 932 struct amdgpu_vm_id { 933 unsigned id; 934 uint64_t pd_gpu_addr; 935 /* last flushed PD/PT update */ 936 struct amdgpu_fence *flushed_updates; 937 /* last use of vmid */ 938 struct amdgpu_fence *last_id_use; 939 }; 940 941 struct amdgpu_vm { 942 struct mutex mutex; 943 944 struct rb_root va; 945 946 /* protecting invalidated and freed */ 947 spinlock_t status_lock; 948 949 /* BOs moved, but not yet updated in the PT */ 950 struct list_head invalidated; 951 952 /* BOs freed, but not yet updated in the PT */ 953 struct list_head freed; 954 955 /* contains the page directory */ 956 struct amdgpu_bo *page_directory; 957 unsigned max_pde_used; 958 959 /* array of page tables, one for each page directory entry */ 960 struct amdgpu_vm_pt *page_tables; 961 962 /* for id and flush management per ring */ 963 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 964 }; 965 966 struct amdgpu_vm_manager { 967 struct amdgpu_fence *active[AMDGPU_NUM_VM]; 968 uint32_t max_pfn; 969 /* number of VMIDs */ 970 unsigned nvm; 971 /* vram base address for page table entry */ 972 u64 vram_base_offset; 973 /* is vm enabled? */ 974 bool enabled; 975 /* for hw to save the PD addr on suspend/resume */ 976 uint32_t saved_table_addr[AMDGPU_NUM_VM]; 977 /* vm pte handling */ 978 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 979 struct amdgpu_ring *vm_pte_funcs_ring; 980 }; 981 982 /* 983 * context related structures 984 */ 985 986 struct amdgpu_ctx_state { 987 uint64_t flags; 988 uint32_t hangs; 989 }; 990 991 struct amdgpu_ctx { 992 /* call kref_get()before CS start and kref_put() after CS fence signaled */ 993 struct kref refcount; 994 struct amdgpu_fpriv *fpriv; 995 struct amdgpu_ctx_state state; 996 uint32_t id; 997 unsigned reset_counter; 998 }; 999 1000 struct amdgpu_ctx_mgr { 1001 struct amdgpu_device *adev; 1002 struct idr ctx_handles; 1003 /* lock for IDR system */ 1004 struct mutex lock; 1005 }; 1006 1007 /* 1008 * file private structure 1009 */ 1010 1011 struct amdgpu_fpriv { 1012 struct amdgpu_vm vm; 1013 struct mutex bo_list_lock; 1014 struct idr bo_list_handles; 1015 struct amdgpu_ctx_mgr ctx_mgr; 1016 }; 1017 1018 /* 1019 * residency list 1020 */ 1021 1022 struct amdgpu_bo_list { 1023 struct mutex lock; 1024 struct amdgpu_bo *gds_obj; 1025 struct amdgpu_bo *gws_obj; 1026 struct amdgpu_bo *oa_obj; 1027 bool has_userptr; 1028 unsigned num_entries; 1029 struct amdgpu_bo_list_entry *array; 1030 }; 1031 1032 struct amdgpu_bo_list * 1033 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1034 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1035 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1036 1037 /* 1038 * GFX stuff 1039 */ 1040 #include "clearstate_defs.h" 1041 1042 struct amdgpu_rlc { 1043 /* for power gating */ 1044 struct amdgpu_bo *save_restore_obj; 1045 uint64_t save_restore_gpu_addr; 1046 volatile uint32_t *sr_ptr; 1047 const u32 *reg_list; 1048 u32 reg_list_size; 1049 /* for clear state */ 1050 struct amdgpu_bo *clear_state_obj; 1051 uint64_t clear_state_gpu_addr; 1052 volatile uint32_t *cs_ptr; 1053 const struct cs_section_def *cs_data; 1054 u32 clear_state_size; 1055 /* for cp tables */ 1056 struct amdgpu_bo *cp_table_obj; 1057 uint64_t cp_table_gpu_addr; 1058 volatile uint32_t *cp_table_ptr; 1059 u32 cp_table_size; 1060 }; 1061 1062 struct amdgpu_mec { 1063 struct amdgpu_bo *hpd_eop_obj; 1064 u64 hpd_eop_gpu_addr; 1065 u32 num_pipe; 1066 u32 num_mec; 1067 u32 num_queue; 1068 }; 1069 1070 /* 1071 * GPU scratch registers structures, functions & helpers 1072 */ 1073 struct amdgpu_scratch { 1074 unsigned num_reg; 1075 uint32_t reg_base; 1076 bool free[32]; 1077 uint32_t reg[32]; 1078 }; 1079 1080 /* 1081 * GFX configurations 1082 */ 1083 struct amdgpu_gca_config { 1084 unsigned max_shader_engines; 1085 unsigned max_tile_pipes; 1086 unsigned max_cu_per_sh; 1087 unsigned max_sh_per_se; 1088 unsigned max_backends_per_se; 1089 unsigned max_texture_channel_caches; 1090 unsigned max_gprs; 1091 unsigned max_gs_threads; 1092 unsigned max_hw_contexts; 1093 unsigned sc_prim_fifo_size_frontend; 1094 unsigned sc_prim_fifo_size_backend; 1095 unsigned sc_hiz_tile_fifo_size; 1096 unsigned sc_earlyz_tile_fifo_size; 1097 1098 unsigned num_tile_pipes; 1099 unsigned backend_enable_mask; 1100 unsigned mem_max_burst_length_bytes; 1101 unsigned mem_row_size_in_kb; 1102 unsigned shader_engine_tile_size; 1103 unsigned num_gpus; 1104 unsigned multi_gpu_tile_size; 1105 unsigned mc_arb_ramcfg; 1106 unsigned gb_addr_config; 1107 1108 uint32_t tile_mode_array[32]; 1109 uint32_t macrotile_mode_array[16]; 1110 }; 1111 1112 struct amdgpu_gfx { 1113 struct mutex gpu_clock_mutex; 1114 struct amdgpu_gca_config config; 1115 struct amdgpu_rlc rlc; 1116 struct amdgpu_mec mec; 1117 struct amdgpu_scratch scratch; 1118 const struct firmware *me_fw; /* ME firmware */ 1119 uint32_t me_fw_version; 1120 const struct firmware *pfp_fw; /* PFP firmware */ 1121 uint32_t pfp_fw_version; 1122 const struct firmware *ce_fw; /* CE firmware */ 1123 uint32_t ce_fw_version; 1124 const struct firmware *rlc_fw; /* RLC firmware */ 1125 uint32_t rlc_fw_version; 1126 const struct firmware *mec_fw; /* MEC firmware */ 1127 uint32_t mec_fw_version; 1128 const struct firmware *mec2_fw; /* MEC2 firmware */ 1129 uint32_t mec2_fw_version; 1130 uint32_t me_feature_version; 1131 uint32_t ce_feature_version; 1132 uint32_t pfp_feature_version; 1133 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1134 unsigned num_gfx_rings; 1135 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1136 unsigned num_compute_rings; 1137 struct amdgpu_irq_src eop_irq; 1138 struct amdgpu_irq_src priv_reg_irq; 1139 struct amdgpu_irq_src priv_inst_irq; 1140 /* gfx status */ 1141 uint32_t gfx_current_status; 1142 /* sync signal for const engine */ 1143 unsigned ce_sync_offs; 1144 /* ce ram size*/ 1145 unsigned ce_ram_size; 1146 }; 1147 1148 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1149 unsigned size, struct amdgpu_ib *ib); 1150 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1151 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1152 struct amdgpu_ib *ib, void *owner); 1153 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1154 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1155 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1156 /* Ring access between begin & end cannot sleep */ 1157 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1158 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1159 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1160 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1161 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1162 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1163 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1164 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); 1165 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); 1166 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1167 uint32_t **data); 1168 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1169 unsigned size, uint32_t *data); 1170 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1171 unsigned ring_size, u32 nop, u32 align_mask, 1172 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1173 enum amdgpu_ring_type ring_type); 1174 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1175 1176 /* 1177 * CS. 1178 */ 1179 struct amdgpu_cs_chunk { 1180 uint32_t chunk_id; 1181 uint32_t length_dw; 1182 uint32_t *kdata; 1183 void __user *user_ptr; 1184 }; 1185 1186 struct amdgpu_cs_parser { 1187 struct amdgpu_device *adev; 1188 struct drm_file *filp; 1189 struct amdgpu_ctx *ctx; 1190 struct amdgpu_bo_list *bo_list; 1191 /* chunks */ 1192 unsigned nchunks; 1193 struct amdgpu_cs_chunk *chunks; 1194 /* relocations */ 1195 struct amdgpu_bo_list_entry *vm_bos; 1196 struct list_head validated; 1197 1198 struct amdgpu_ib *ibs; 1199 uint32_t num_ibs; 1200 1201 struct ww_acquire_ctx ticket; 1202 1203 /* user fence */ 1204 struct amdgpu_user_fence uf; 1205 }; 1206 1207 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1208 { 1209 return p->ibs[ib_idx].ptr[idx]; 1210 } 1211 1212 /* 1213 * Writeback 1214 */ 1215 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1216 1217 struct amdgpu_wb { 1218 struct amdgpu_bo *wb_obj; 1219 volatile uint32_t *wb; 1220 uint64_t gpu_addr; 1221 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1222 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1223 }; 1224 1225 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1226 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1227 1228 /** 1229 * struct amdgpu_pm - power management datas 1230 * It keeps track of various data needed to take powermanagement decision. 1231 */ 1232 1233 enum amdgpu_pm_state_type { 1234 /* not used for dpm */ 1235 POWER_STATE_TYPE_DEFAULT, 1236 POWER_STATE_TYPE_POWERSAVE, 1237 /* user selectable states */ 1238 POWER_STATE_TYPE_BATTERY, 1239 POWER_STATE_TYPE_BALANCED, 1240 POWER_STATE_TYPE_PERFORMANCE, 1241 /* internal states */ 1242 POWER_STATE_TYPE_INTERNAL_UVD, 1243 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1244 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1245 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1246 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1247 POWER_STATE_TYPE_INTERNAL_BOOT, 1248 POWER_STATE_TYPE_INTERNAL_THERMAL, 1249 POWER_STATE_TYPE_INTERNAL_ACPI, 1250 POWER_STATE_TYPE_INTERNAL_ULV, 1251 POWER_STATE_TYPE_INTERNAL_3DPERF, 1252 }; 1253 1254 enum amdgpu_int_thermal_type { 1255 THERMAL_TYPE_NONE, 1256 THERMAL_TYPE_EXTERNAL, 1257 THERMAL_TYPE_EXTERNAL_GPIO, 1258 THERMAL_TYPE_RV6XX, 1259 THERMAL_TYPE_RV770, 1260 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1261 THERMAL_TYPE_EVERGREEN, 1262 THERMAL_TYPE_SUMO, 1263 THERMAL_TYPE_NI, 1264 THERMAL_TYPE_SI, 1265 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1266 THERMAL_TYPE_CI, 1267 THERMAL_TYPE_KV, 1268 }; 1269 1270 enum amdgpu_dpm_auto_throttle_src { 1271 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1272 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1273 }; 1274 1275 enum amdgpu_dpm_event_src { 1276 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1277 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1278 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1279 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1280 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1281 }; 1282 1283 #define AMDGPU_MAX_VCE_LEVELS 6 1284 1285 enum amdgpu_vce_level { 1286 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1287 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1288 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1289 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1290 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1291 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1292 }; 1293 1294 struct amdgpu_ps { 1295 u32 caps; /* vbios flags */ 1296 u32 class; /* vbios flags */ 1297 u32 class2; /* vbios flags */ 1298 /* UVD clocks */ 1299 u32 vclk; 1300 u32 dclk; 1301 /* VCE clocks */ 1302 u32 evclk; 1303 u32 ecclk; 1304 bool vce_active; 1305 enum amdgpu_vce_level vce_level; 1306 /* asic priv */ 1307 void *ps_priv; 1308 }; 1309 1310 struct amdgpu_dpm_thermal { 1311 /* thermal interrupt work */ 1312 struct work_struct work; 1313 /* low temperature threshold */ 1314 int min_temp; 1315 /* high temperature threshold */ 1316 int max_temp; 1317 /* was last interrupt low to high or high to low */ 1318 bool high_to_low; 1319 /* interrupt source */ 1320 struct amdgpu_irq_src irq; 1321 }; 1322 1323 enum amdgpu_clk_action 1324 { 1325 AMDGPU_SCLK_UP = 1, 1326 AMDGPU_SCLK_DOWN 1327 }; 1328 1329 struct amdgpu_blacklist_clocks 1330 { 1331 u32 sclk; 1332 u32 mclk; 1333 enum amdgpu_clk_action action; 1334 }; 1335 1336 struct amdgpu_clock_and_voltage_limits { 1337 u32 sclk; 1338 u32 mclk; 1339 u16 vddc; 1340 u16 vddci; 1341 }; 1342 1343 struct amdgpu_clock_array { 1344 u32 count; 1345 u32 *values; 1346 }; 1347 1348 struct amdgpu_clock_voltage_dependency_entry { 1349 u32 clk; 1350 u16 v; 1351 }; 1352 1353 struct amdgpu_clock_voltage_dependency_table { 1354 u32 count; 1355 struct amdgpu_clock_voltage_dependency_entry *entries; 1356 }; 1357 1358 union amdgpu_cac_leakage_entry { 1359 struct { 1360 u16 vddc; 1361 u32 leakage; 1362 }; 1363 struct { 1364 u16 vddc1; 1365 u16 vddc2; 1366 u16 vddc3; 1367 }; 1368 }; 1369 1370 struct amdgpu_cac_leakage_table { 1371 u32 count; 1372 union amdgpu_cac_leakage_entry *entries; 1373 }; 1374 1375 struct amdgpu_phase_shedding_limits_entry { 1376 u16 voltage; 1377 u32 sclk; 1378 u32 mclk; 1379 }; 1380 1381 struct amdgpu_phase_shedding_limits_table { 1382 u32 count; 1383 struct amdgpu_phase_shedding_limits_entry *entries; 1384 }; 1385 1386 struct amdgpu_uvd_clock_voltage_dependency_entry { 1387 u32 vclk; 1388 u32 dclk; 1389 u16 v; 1390 }; 1391 1392 struct amdgpu_uvd_clock_voltage_dependency_table { 1393 u8 count; 1394 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1395 }; 1396 1397 struct amdgpu_vce_clock_voltage_dependency_entry { 1398 u32 ecclk; 1399 u32 evclk; 1400 u16 v; 1401 }; 1402 1403 struct amdgpu_vce_clock_voltage_dependency_table { 1404 u8 count; 1405 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1406 }; 1407 1408 struct amdgpu_ppm_table { 1409 u8 ppm_design; 1410 u16 cpu_core_number; 1411 u32 platform_tdp; 1412 u32 small_ac_platform_tdp; 1413 u32 platform_tdc; 1414 u32 small_ac_platform_tdc; 1415 u32 apu_tdp; 1416 u32 dgpu_tdp; 1417 u32 dgpu_ulv_power; 1418 u32 tj_max; 1419 }; 1420 1421 struct amdgpu_cac_tdp_table { 1422 u16 tdp; 1423 u16 configurable_tdp; 1424 u16 tdc; 1425 u16 battery_power_limit; 1426 u16 small_power_limit; 1427 u16 low_cac_leakage; 1428 u16 high_cac_leakage; 1429 u16 maximum_power_delivery_limit; 1430 }; 1431 1432 struct amdgpu_dpm_dynamic_state { 1433 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1434 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1435 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1436 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1437 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1438 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1439 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1440 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1441 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1442 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1443 struct amdgpu_clock_array valid_sclk_values; 1444 struct amdgpu_clock_array valid_mclk_values; 1445 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1446 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1447 u32 mclk_sclk_ratio; 1448 u32 sclk_mclk_delta; 1449 u16 vddc_vddci_delta; 1450 u16 min_vddc_for_pcie_gen2; 1451 struct amdgpu_cac_leakage_table cac_leakage_table; 1452 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1453 struct amdgpu_ppm_table *ppm_table; 1454 struct amdgpu_cac_tdp_table *cac_tdp_table; 1455 }; 1456 1457 struct amdgpu_dpm_fan { 1458 u16 t_min; 1459 u16 t_med; 1460 u16 t_high; 1461 u16 pwm_min; 1462 u16 pwm_med; 1463 u16 pwm_high; 1464 u8 t_hyst; 1465 u32 cycle_delay; 1466 u16 t_max; 1467 u8 control_mode; 1468 u16 default_max_fan_pwm; 1469 u16 default_fan_output_sensitivity; 1470 u16 fan_output_sensitivity; 1471 bool ucode_fan_control; 1472 }; 1473 1474 enum amdgpu_pcie_gen { 1475 AMDGPU_PCIE_GEN1 = 0, 1476 AMDGPU_PCIE_GEN2 = 1, 1477 AMDGPU_PCIE_GEN3 = 2, 1478 AMDGPU_PCIE_GEN_INVALID = 0xffff 1479 }; 1480 1481 enum amdgpu_dpm_forced_level { 1482 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1483 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1484 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1485 }; 1486 1487 struct amdgpu_vce_state { 1488 /* vce clocks */ 1489 u32 evclk; 1490 u32 ecclk; 1491 /* gpu clocks */ 1492 u32 sclk; 1493 u32 mclk; 1494 u8 clk_idx; 1495 u8 pstate; 1496 }; 1497 1498 struct amdgpu_dpm_funcs { 1499 int (*get_temperature)(struct amdgpu_device *adev); 1500 int (*pre_set_power_state)(struct amdgpu_device *adev); 1501 int (*set_power_state)(struct amdgpu_device *adev); 1502 void (*post_set_power_state)(struct amdgpu_device *adev); 1503 void (*display_configuration_changed)(struct amdgpu_device *adev); 1504 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1505 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1506 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1507 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1508 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1509 bool (*vblank_too_short)(struct amdgpu_device *adev); 1510 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1511 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1512 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1513 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1514 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1515 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1516 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1517 }; 1518 1519 struct amdgpu_dpm { 1520 struct amdgpu_ps *ps; 1521 /* number of valid power states */ 1522 int num_ps; 1523 /* current power state that is active */ 1524 struct amdgpu_ps *current_ps; 1525 /* requested power state */ 1526 struct amdgpu_ps *requested_ps; 1527 /* boot up power state */ 1528 struct amdgpu_ps *boot_ps; 1529 /* default uvd power state */ 1530 struct amdgpu_ps *uvd_ps; 1531 /* vce requirements */ 1532 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1533 enum amdgpu_vce_level vce_level; 1534 enum amdgpu_pm_state_type state; 1535 enum amdgpu_pm_state_type user_state; 1536 u32 platform_caps; 1537 u32 voltage_response_time; 1538 u32 backbias_response_time; 1539 void *priv; 1540 u32 new_active_crtcs; 1541 int new_active_crtc_count; 1542 u32 current_active_crtcs; 1543 int current_active_crtc_count; 1544 struct amdgpu_dpm_dynamic_state dyn_state; 1545 struct amdgpu_dpm_fan fan; 1546 u32 tdp_limit; 1547 u32 near_tdp_limit; 1548 u32 near_tdp_limit_adjusted; 1549 u32 sq_ramping_threshold; 1550 u32 cac_leakage; 1551 u16 tdp_od_limit; 1552 u32 tdp_adjustment; 1553 u16 load_line_slope; 1554 bool power_control; 1555 bool ac_power; 1556 /* special states active */ 1557 bool thermal_active; 1558 bool uvd_active; 1559 bool vce_active; 1560 /* thermal handling */ 1561 struct amdgpu_dpm_thermal thermal; 1562 /* forced levels */ 1563 enum amdgpu_dpm_forced_level forced_level; 1564 }; 1565 1566 struct amdgpu_pm { 1567 struct mutex mutex; 1568 u32 current_sclk; 1569 u32 current_mclk; 1570 u32 default_sclk; 1571 u32 default_mclk; 1572 struct amdgpu_i2c_chan *i2c_bus; 1573 /* internal thermal controller on rv6xx+ */ 1574 enum amdgpu_int_thermal_type int_thermal_type; 1575 struct device *int_hwmon_dev; 1576 /* fan control parameters */ 1577 bool no_fan; 1578 u8 fan_pulses_per_revolution; 1579 u8 fan_min_rpm; 1580 u8 fan_max_rpm; 1581 /* dpm */ 1582 bool dpm_enabled; 1583 struct amdgpu_dpm dpm; 1584 const struct firmware *fw; /* SMC firmware */ 1585 uint32_t fw_version; 1586 const struct amdgpu_dpm_funcs *funcs; 1587 }; 1588 1589 /* 1590 * UVD 1591 */ 1592 #define AMDGPU_MAX_UVD_HANDLES 10 1593 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1594 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1595 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1596 1597 struct amdgpu_uvd { 1598 struct amdgpu_bo *vcpu_bo; 1599 void *cpu_addr; 1600 uint64_t gpu_addr; 1601 void *saved_bo; 1602 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1603 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1604 struct delayed_work idle_work; 1605 const struct firmware *fw; /* UVD firmware */ 1606 struct amdgpu_ring ring; 1607 struct amdgpu_irq_src irq; 1608 bool address_64_bit; 1609 }; 1610 1611 /* 1612 * VCE 1613 */ 1614 #define AMDGPU_MAX_VCE_HANDLES 16 1615 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1616 1617 struct amdgpu_vce { 1618 struct amdgpu_bo *vcpu_bo; 1619 uint64_t gpu_addr; 1620 unsigned fw_version; 1621 unsigned fb_version; 1622 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1623 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1624 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1625 struct delayed_work idle_work; 1626 const struct firmware *fw; /* VCE firmware */ 1627 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1628 struct amdgpu_irq_src irq; 1629 }; 1630 1631 /* 1632 * SDMA 1633 */ 1634 struct amdgpu_sdma { 1635 /* SDMA firmware */ 1636 const struct firmware *fw; 1637 uint32_t fw_version; 1638 1639 struct amdgpu_ring ring; 1640 }; 1641 1642 /* 1643 * Firmware 1644 */ 1645 struct amdgpu_firmware { 1646 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1647 bool smu_load; 1648 struct amdgpu_bo *fw_buf; 1649 unsigned int fw_size; 1650 }; 1651 1652 /* 1653 * Benchmarking 1654 */ 1655 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1656 1657 1658 /* 1659 * Testing 1660 */ 1661 void amdgpu_test_moves(struct amdgpu_device *adev); 1662 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1663 struct amdgpu_ring *cpA, 1664 struct amdgpu_ring *cpB); 1665 void amdgpu_test_syncing(struct amdgpu_device *adev); 1666 1667 /* 1668 * MMU Notifier 1669 */ 1670 #if defined(CONFIG_MMU_NOTIFIER) 1671 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1672 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1673 #else 1674 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1675 { 1676 return -ENODEV; 1677 } 1678 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1679 #endif 1680 1681 /* 1682 * Debugfs 1683 */ 1684 struct amdgpu_debugfs { 1685 struct drm_info_list *files; 1686 unsigned num_files; 1687 }; 1688 1689 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1690 struct drm_info_list *files, 1691 unsigned nfiles); 1692 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1693 1694 #if defined(CONFIG_DEBUG_FS) 1695 int amdgpu_debugfs_init(struct drm_minor *minor); 1696 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1697 #endif 1698 1699 /* 1700 * amdgpu smumgr functions 1701 */ 1702 struct amdgpu_smumgr_funcs { 1703 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1704 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1705 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1706 }; 1707 1708 /* 1709 * amdgpu smumgr 1710 */ 1711 struct amdgpu_smumgr { 1712 struct amdgpu_bo *toc_buf; 1713 struct amdgpu_bo *smu_buf; 1714 /* asic priv smu data */ 1715 void *priv; 1716 spinlock_t smu_lock; 1717 /* smumgr functions */ 1718 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1719 /* ucode loading complete flag */ 1720 uint32_t fw_flags; 1721 }; 1722 1723 /* 1724 * ASIC specific register table accessible by UMD 1725 */ 1726 struct amdgpu_allowed_register_entry { 1727 uint32_t reg_offset; 1728 bool untouched; 1729 bool grbm_indexed; 1730 }; 1731 1732 struct amdgpu_cu_info { 1733 uint32_t number; /* total active CU number */ 1734 uint32_t ao_cu_mask; 1735 uint32_t bitmap[4][4]; 1736 }; 1737 1738 1739 /* 1740 * ASIC specific functions. 1741 */ 1742 struct amdgpu_asic_funcs { 1743 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1744 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1745 u32 sh_num, u32 reg_offset, u32 *value); 1746 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1747 int (*reset)(struct amdgpu_device *adev); 1748 /* wait for mc_idle */ 1749 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1750 /* get the reference clock */ 1751 u32 (*get_xclk)(struct amdgpu_device *adev); 1752 /* get the gpu clock counter */ 1753 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1754 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1755 /* MM block clocks */ 1756 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1757 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1758 }; 1759 1760 /* 1761 * IOCTL. 1762 */ 1763 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1764 struct drm_file *filp); 1765 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1766 struct drm_file *filp); 1767 1768 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1769 struct drm_file *filp); 1770 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1771 struct drm_file *filp); 1772 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1773 struct drm_file *filp); 1774 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1775 struct drm_file *filp); 1776 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1777 struct drm_file *filp); 1778 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1779 struct drm_file *filp); 1780 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1781 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1782 1783 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1784 struct drm_file *filp); 1785 1786 /* VRAM scratch page for HDP bug, default vram page */ 1787 struct amdgpu_vram_scratch { 1788 struct amdgpu_bo *robj; 1789 volatile uint32_t *ptr; 1790 u64 gpu_addr; 1791 }; 1792 1793 /* 1794 * ACPI 1795 */ 1796 struct amdgpu_atif_notification_cfg { 1797 bool enabled; 1798 int command_code; 1799 }; 1800 1801 struct amdgpu_atif_notifications { 1802 bool display_switch; 1803 bool expansion_mode_change; 1804 bool thermal_state; 1805 bool forced_power_state; 1806 bool system_power_state; 1807 bool display_conf_change; 1808 bool px_gfx_switch; 1809 bool brightness_change; 1810 bool dgpu_display_event; 1811 }; 1812 1813 struct amdgpu_atif_functions { 1814 bool system_params; 1815 bool sbios_requests; 1816 bool select_active_disp; 1817 bool lid_state; 1818 bool get_tv_standard; 1819 bool set_tv_standard; 1820 bool get_panel_expansion_mode; 1821 bool set_panel_expansion_mode; 1822 bool temperature_change; 1823 bool graphics_device_types; 1824 }; 1825 1826 struct amdgpu_atif { 1827 struct amdgpu_atif_notifications notifications; 1828 struct amdgpu_atif_functions functions; 1829 struct amdgpu_atif_notification_cfg notification_cfg; 1830 struct amdgpu_encoder *encoder_for_bl; 1831 }; 1832 1833 struct amdgpu_atcs_functions { 1834 bool get_ext_state; 1835 bool pcie_perf_req; 1836 bool pcie_dev_rdy; 1837 bool pcie_bus_width; 1838 }; 1839 1840 struct amdgpu_atcs { 1841 struct amdgpu_atcs_functions functions; 1842 }; 1843 1844 int amdgpu_ctx_alloc(struct amdgpu_device *adev,struct amdgpu_fpriv *fpriv, 1845 uint32_t *id,uint32_t flags); 1846 int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv, 1847 uint32_t id); 1848 1849 void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv); 1850 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1851 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1852 1853 extern int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1854 struct drm_file *filp); 1855 1856 /* 1857 * Core structure, functions and helpers. 1858 */ 1859 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1860 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1861 1862 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1863 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1864 1865 struct amdgpu_device { 1866 struct device *dev; 1867 struct drm_device *ddev; 1868 struct pci_dev *pdev; 1869 struct rw_semaphore exclusive_lock; 1870 1871 /* ASIC */ 1872 enum amdgpu_asic_type asic_type; 1873 uint32_t family; 1874 uint32_t rev_id; 1875 uint32_t external_rev_id; 1876 unsigned long flags; 1877 int usec_timeout; 1878 const struct amdgpu_asic_funcs *asic_funcs; 1879 bool shutdown; 1880 bool suspend; 1881 bool need_dma32; 1882 bool accel_working; 1883 bool needs_reset; 1884 struct work_struct reset_work; 1885 struct notifier_block acpi_nb; 1886 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1887 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1888 unsigned debugfs_count; 1889 #if defined(CONFIG_DEBUG_FS) 1890 struct dentry *debugfs_regs; 1891 #endif 1892 struct amdgpu_atif atif; 1893 struct amdgpu_atcs atcs; 1894 struct mutex srbm_mutex; 1895 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1896 struct mutex grbm_idx_mutex; 1897 struct dev_pm_domain vga_pm_domain; 1898 bool have_disp_power_ref; 1899 1900 /* BIOS */ 1901 uint8_t *bios; 1902 bool is_atom_bios; 1903 uint16_t bios_header_start; 1904 struct amdgpu_bo *stollen_vga_memory; 1905 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1906 1907 /* Register/doorbell mmio */ 1908 resource_size_t rmmio_base; 1909 resource_size_t rmmio_size; 1910 void __iomem *rmmio; 1911 /* protects concurrent MM_INDEX/DATA based register access */ 1912 spinlock_t mmio_idx_lock; 1913 /* protects concurrent SMC based register access */ 1914 spinlock_t smc_idx_lock; 1915 amdgpu_rreg_t smc_rreg; 1916 amdgpu_wreg_t smc_wreg; 1917 /* protects concurrent PCIE register access */ 1918 spinlock_t pcie_idx_lock; 1919 amdgpu_rreg_t pcie_rreg; 1920 amdgpu_wreg_t pcie_wreg; 1921 /* protects concurrent UVD register access */ 1922 spinlock_t uvd_ctx_idx_lock; 1923 amdgpu_rreg_t uvd_ctx_rreg; 1924 amdgpu_wreg_t uvd_ctx_wreg; 1925 /* protects concurrent DIDT register access */ 1926 spinlock_t didt_idx_lock; 1927 amdgpu_rreg_t didt_rreg; 1928 amdgpu_wreg_t didt_wreg; 1929 /* protects concurrent ENDPOINT (audio) register access */ 1930 spinlock_t audio_endpt_idx_lock; 1931 amdgpu_block_rreg_t audio_endpt_rreg; 1932 amdgpu_block_wreg_t audio_endpt_wreg; 1933 void __iomem *rio_mem; 1934 resource_size_t rio_mem_size; 1935 struct amdgpu_doorbell doorbell; 1936 1937 /* clock/pll info */ 1938 struct amdgpu_clock clock; 1939 1940 /* MC */ 1941 struct amdgpu_mc mc; 1942 struct amdgpu_gart gart; 1943 struct amdgpu_dummy_page dummy_page; 1944 struct amdgpu_vm_manager vm_manager; 1945 1946 /* memory management */ 1947 struct amdgpu_mman mman; 1948 struct amdgpu_gem gem; 1949 struct amdgpu_vram_scratch vram_scratch; 1950 struct amdgpu_wb wb; 1951 atomic64_t vram_usage; 1952 atomic64_t vram_vis_usage; 1953 atomic64_t gtt_usage; 1954 atomic64_t num_bytes_moved; 1955 atomic_t gpu_reset_counter; 1956 1957 /* display */ 1958 struct amdgpu_mode_info mode_info; 1959 struct work_struct hotplug_work; 1960 struct amdgpu_irq_src crtc_irq; 1961 struct amdgpu_irq_src pageflip_irq; 1962 struct amdgpu_irq_src hpd_irq; 1963 1964 /* rings */ 1965 wait_queue_head_t fence_queue; 1966 unsigned fence_context; 1967 struct mutex ring_lock; 1968 unsigned num_rings; 1969 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1970 bool ib_pool_ready; 1971 struct amdgpu_sa_manager ring_tmp_bo; 1972 1973 /* interrupts */ 1974 struct amdgpu_irq irq; 1975 1976 /* dpm */ 1977 struct amdgpu_pm pm; 1978 u32 cg_flags; 1979 u32 pg_flags; 1980 1981 /* amdgpu smumgr */ 1982 struct amdgpu_smumgr smu; 1983 1984 /* gfx */ 1985 struct amdgpu_gfx gfx; 1986 1987 /* sdma */ 1988 struct amdgpu_sdma sdma[2]; 1989 struct amdgpu_irq_src sdma_trap_irq; 1990 struct amdgpu_irq_src sdma_illegal_inst_irq; 1991 1992 /* uvd */ 1993 bool has_uvd; 1994 struct amdgpu_uvd uvd; 1995 1996 /* vce */ 1997 struct amdgpu_vce vce; 1998 1999 /* firmwares */ 2000 struct amdgpu_firmware firmware; 2001 2002 /* GDS */ 2003 struct amdgpu_gds gds; 2004 2005 const struct amdgpu_ip_block_version *ip_blocks; 2006 int num_ip_blocks; 2007 bool *ip_block_enabled; 2008 struct mutex mn_lock; 2009 DECLARE_HASHTABLE(mn_hash, 7); 2010 2011 /* tracking pinned memory */ 2012 u64 vram_pin_size; 2013 u64 gart_pin_size; 2014 }; 2015 2016 bool amdgpu_device_is_px(struct drm_device *dev); 2017 int amdgpu_device_init(struct amdgpu_device *adev, 2018 struct drm_device *ddev, 2019 struct pci_dev *pdev, 2020 uint32_t flags); 2021 void amdgpu_device_fini(struct amdgpu_device *adev); 2022 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2023 2024 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2025 bool always_indirect); 2026 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2027 bool always_indirect); 2028 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2029 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2030 2031 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2032 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2033 2034 /* 2035 * Cast helper 2036 */ 2037 extern const struct fence_ops amdgpu_fence_ops; 2038 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2039 { 2040 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2041 2042 if (__f->base.ops == &amdgpu_fence_ops) 2043 return __f; 2044 2045 return NULL; 2046 } 2047 2048 /* 2049 * Registers read & write functions. 2050 */ 2051 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2052 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2053 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2054 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2055 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2056 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2057 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2058 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2059 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2060 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2061 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2062 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2063 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2064 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2065 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2066 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2067 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2068 #define WREG32_P(reg, val, mask) \ 2069 do { \ 2070 uint32_t tmp_ = RREG32(reg); \ 2071 tmp_ &= (mask); \ 2072 tmp_ |= ((val) & ~(mask)); \ 2073 WREG32(reg, tmp_); \ 2074 } while (0) 2075 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2076 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2077 #define WREG32_PLL_P(reg, val, mask) \ 2078 do { \ 2079 uint32_t tmp_ = RREG32_PLL(reg); \ 2080 tmp_ &= (mask); \ 2081 tmp_ |= ((val) & ~(mask)); \ 2082 WREG32_PLL(reg, tmp_); \ 2083 } while (0) 2084 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2085 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2086 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2087 2088 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2089 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2090 2091 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2092 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2093 2094 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2095 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2096 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2097 2098 #define REG_GET_FIELD(value, reg, field) \ 2099 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2100 2101 /* 2102 * BIOS helpers. 2103 */ 2104 #define RBIOS8(i) (adev->bios[i]) 2105 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2106 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2107 2108 /* 2109 * RING helpers. 2110 */ 2111 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2112 { 2113 if (ring->count_dw <= 0) 2114 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2115 ring->ring[ring->wptr++] = v; 2116 ring->wptr &= ring->ptr_mask; 2117 ring->count_dw--; 2118 ring->ring_free_dw--; 2119 } 2120 2121 /* 2122 * ASICs macro. 2123 */ 2124 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2125 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2126 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2127 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2128 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2129 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2130 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2131 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2132 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2133 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2134 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2135 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2136 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2137 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2138 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2139 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2140 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2141 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2142 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2143 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) 2144 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2145 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2146 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2147 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2148 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2149 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2150 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2151 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2152 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2153 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2154 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2155 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2156 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2157 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2158 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2159 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2160 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2161 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2162 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2163 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2164 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2165 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2166 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2167 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2168 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2169 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2170 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2171 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2172 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b)) 2173 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b)) 2174 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2175 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2176 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2177 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2178 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2179 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2180 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2181 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2182 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2183 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2184 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2185 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2186 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2187 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2188 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2189 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2190 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2191 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2192 2193 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2194 2195 /* Common functions */ 2196 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2197 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2198 bool amdgpu_card_posted(struct amdgpu_device *adev); 2199 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2200 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2201 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2202 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2203 u32 ip_instance, u32 ring, 2204 struct amdgpu_ring **out_ring); 2205 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2206 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2207 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2208 uint32_t flags); 2209 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2210 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2211 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2212 struct ttm_mem_reg *mem); 2213 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2214 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2215 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2216 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2217 const u32 *registers, 2218 const u32 array_size); 2219 2220 bool amdgpu_device_is_px(struct drm_device *dev); 2221 /* atpx handler */ 2222 #if defined(CONFIG_VGA_SWITCHEROO) 2223 void amdgpu_register_atpx_handler(void); 2224 void amdgpu_unregister_atpx_handler(void); 2225 #else 2226 static inline void amdgpu_register_atpx_handler(void) {} 2227 static inline void amdgpu_unregister_atpx_handler(void) {} 2228 #endif 2229 2230 /* 2231 * KMS 2232 */ 2233 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2234 extern int amdgpu_max_kms_ioctl; 2235 2236 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2237 int amdgpu_driver_unload_kms(struct drm_device *dev); 2238 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2239 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2240 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2241 struct drm_file *file_priv); 2242 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2243 struct drm_file *file_priv); 2244 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2245 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2246 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); 2247 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); 2248 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); 2249 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 2250 int *max_error, 2251 struct timeval *vblank_time, 2252 unsigned flags); 2253 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2254 unsigned long arg); 2255 2256 /* 2257 * vm 2258 */ 2259 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2260 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2261 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2262 struct amdgpu_vm *vm, 2263 struct list_head *head); 2264 struct amdgpu_fence *amdgpu_vm_grab_id(struct amdgpu_ring *ring, 2265 struct amdgpu_vm *vm); 2266 void amdgpu_vm_flush(struct amdgpu_ring *ring, 2267 struct amdgpu_vm *vm, 2268 struct amdgpu_fence *updates); 2269 void amdgpu_vm_fence(struct amdgpu_device *adev, 2270 struct amdgpu_vm *vm, 2271 struct amdgpu_fence *fence); 2272 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2273 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2274 struct amdgpu_vm *vm); 2275 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2276 struct amdgpu_vm *vm); 2277 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2278 struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2279 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2280 struct amdgpu_bo_va *bo_va, 2281 struct ttm_mem_reg *mem); 2282 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2283 struct amdgpu_bo *bo); 2284 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2285 struct amdgpu_bo *bo); 2286 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2287 struct amdgpu_vm *vm, 2288 struct amdgpu_bo *bo); 2289 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2290 struct amdgpu_bo_va *bo_va, 2291 uint64_t addr, uint64_t offset, 2292 uint64_t size, uint32_t flags); 2293 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2294 struct amdgpu_bo_va *bo_va, 2295 uint64_t addr); 2296 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2297 struct amdgpu_bo_va *bo_va); 2298 2299 /* 2300 * functions used by amdgpu_encoder.c 2301 */ 2302 struct amdgpu_afmt_acr { 2303 u32 clock; 2304 2305 int n_32khz; 2306 int cts_32khz; 2307 2308 int n_44_1khz; 2309 int cts_44_1khz; 2310 2311 int n_48khz; 2312 int cts_48khz; 2313 2314 }; 2315 2316 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2317 2318 /* amdgpu_acpi.c */ 2319 #if defined(CONFIG_ACPI) 2320 int amdgpu_acpi_init(struct amdgpu_device *adev); 2321 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2322 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2323 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2324 u8 perf_req, bool advertise); 2325 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2326 #else 2327 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2328 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2329 #endif 2330 2331 struct amdgpu_bo_va_mapping * 2332 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2333 uint64_t addr, struct amdgpu_bo **bo); 2334 2335 #include "amdgpu_object.h" 2336 2337 #endif 2338