1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 54 #include <drm/ttm/ttm_bo.h> 55 #include <drm/ttm/ttm_placement.h> 56 57 #include <drm/amdgpu_drm.h> 58 #include <drm/drm_gem.h> 59 #include <drm/drm_ioctl.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_utils.h" 67 #include "amdgpu_mode.h" 68 #include "amdgpu_ih.h" 69 #include "amdgpu_irq.h" 70 #include "amdgpu_ucode.h" 71 #include "amdgpu_ttm.h" 72 #include "amdgpu_psp.h" 73 #include "amdgpu_gds.h" 74 #include "amdgpu_sync.h" 75 #include "amdgpu_ring.h" 76 #include "amdgpu_vm.h" 77 #include "amdgpu_dpm.h" 78 #include "amdgpu_acp.h" 79 #include "amdgpu_uvd.h" 80 #include "amdgpu_vce.h" 81 #include "amdgpu_vcn.h" 82 #include "amdgpu_jpeg.h" 83 #include "amdgpu_vpe.h" 84 #include "amdgpu_umsch_mm.h" 85 #include "amdgpu_gmc.h" 86 #include "amdgpu_gfx.h" 87 #include "amdgpu_sdma.h" 88 #include "amdgpu_lsdma.h" 89 #include "amdgpu_nbio.h" 90 #include "amdgpu_hdp.h" 91 #include "amdgpu_dm.h" 92 #include "amdgpu_virt.h" 93 #include "amdgpu_csa.h" 94 #include "amdgpu_mes_ctx.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_discovery.h" 103 #include "amdgpu_mes.h" 104 #include "amdgpu_umc.h" 105 #include "amdgpu_mmhub.h" 106 #include "amdgpu_gfxhub.h" 107 #include "amdgpu_df.h" 108 #include "amdgpu_smuio.h" 109 #include "amdgpu_fdinfo.h" 110 #include "amdgpu_mca.h" 111 #include "amdgpu_aca.h" 112 #include "amdgpu_ras.h" 113 #include "amdgpu_cper.h" 114 #include "amdgpu_xcp.h" 115 #include "amdgpu_seq64.h" 116 #include "amdgpu_reg_state.h" 117 #include "amdgpu_userq.h" 118 #include "amdgpu_eviction_fence.h" 119 #if defined(CONFIG_DRM_AMD_ISP) 120 #include "amdgpu_isp.h" 121 #endif 122 123 #define MAX_GPU_INSTANCE 64 124 125 #define GFX_SLICE_PERIOD_MS 250 126 127 struct amdgpu_gpu_instance { 128 struct amdgpu_device *adev; 129 int mgpu_fan_enabled; 130 }; 131 132 struct amdgpu_mgpu_info { 133 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 134 struct mutex mutex; 135 uint32_t num_gpu; 136 uint32_t num_dgpu; 137 uint32_t num_apu; 138 }; 139 140 enum amdgpu_ss { 141 AMDGPU_SS_DRV_LOAD, 142 AMDGPU_SS_DEV_D0, 143 AMDGPU_SS_DEV_D3, 144 AMDGPU_SS_DRV_UNLOAD 145 }; 146 147 struct amdgpu_hwip_reg_entry { 148 u32 hwip; 149 u32 inst; 150 u32 seg; 151 u32 reg_offset; 152 const char *reg_name; 153 }; 154 155 struct amdgpu_watchdog_timer { 156 bool timeout_fatal_disable; 157 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 158 }; 159 160 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 161 162 /* 163 * Modules parameters. 164 */ 165 extern int amdgpu_modeset; 166 extern unsigned int amdgpu_vram_limit; 167 extern int amdgpu_vis_vram_limit; 168 extern int amdgpu_gart_size; 169 extern int amdgpu_gtt_size; 170 extern int amdgpu_moverate; 171 extern int amdgpu_audio; 172 extern int amdgpu_disp_priority; 173 extern int amdgpu_hw_i2c; 174 extern int amdgpu_pcie_gen2; 175 extern int amdgpu_msi; 176 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 177 extern int amdgpu_dpm; 178 extern int amdgpu_fw_load_type; 179 extern int amdgpu_aspm; 180 extern int amdgpu_runtime_pm; 181 extern uint amdgpu_ip_block_mask; 182 extern int amdgpu_bapm; 183 extern int amdgpu_deep_color; 184 extern int amdgpu_vm_size; 185 extern int amdgpu_vm_block_size; 186 extern int amdgpu_vm_fragment_size; 187 extern int amdgpu_vm_fault_stop; 188 extern int amdgpu_vm_debug; 189 extern int amdgpu_vm_update_mode; 190 extern int amdgpu_exp_hw_support; 191 extern int amdgpu_dc; 192 extern int amdgpu_sched_jobs; 193 extern int amdgpu_sched_hw_submission; 194 extern uint amdgpu_pcie_gen_cap; 195 extern uint amdgpu_pcie_lane_cap; 196 extern u64 amdgpu_cg_mask; 197 extern uint amdgpu_pg_mask; 198 extern uint amdgpu_sdma_phase_quantum; 199 extern char *amdgpu_disable_cu; 200 extern char *amdgpu_virtual_display; 201 extern uint amdgpu_pp_feature_mask; 202 extern uint amdgpu_force_long_training; 203 extern int amdgpu_lbpw; 204 extern int amdgpu_compute_multipipe; 205 extern int amdgpu_gpu_recovery; 206 extern int amdgpu_emu_mode; 207 extern uint amdgpu_smu_memory_pool_size; 208 extern int amdgpu_smu_pptable_id; 209 extern uint amdgpu_dc_feature_mask; 210 extern uint amdgpu_freesync_vid_mode; 211 extern uint amdgpu_dc_debug_mask; 212 extern uint amdgpu_dc_visual_confirm; 213 extern int amdgpu_dm_abm_level; 214 extern int amdgpu_backlight; 215 extern int amdgpu_damage_clips; 216 extern struct amdgpu_mgpu_info mgpu_info; 217 extern int amdgpu_ras_enable; 218 extern uint amdgpu_ras_mask; 219 extern int amdgpu_bad_page_threshold; 220 extern bool amdgpu_ignore_bad_page_threshold; 221 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 222 extern int amdgpu_async_gfx_ring; 223 extern int amdgpu_mcbp; 224 extern int amdgpu_discovery; 225 extern int amdgpu_mes; 226 extern int amdgpu_mes_log_enable; 227 extern int amdgpu_mes_kiq; 228 extern int amdgpu_uni_mes; 229 extern int amdgpu_noretry; 230 extern int amdgpu_force_asic_type; 231 extern int amdgpu_smartshift_bias; 232 extern int amdgpu_use_xgmi_p2p; 233 extern int amdgpu_mtype_local; 234 extern int amdgpu_enforce_isolation; 235 #ifdef CONFIG_HSA_AMD 236 extern int sched_policy; 237 extern bool debug_evictions; 238 extern bool no_system_mem_limit; 239 extern int halt_if_hws_hang; 240 extern uint amdgpu_svm_default_granularity; 241 #else 242 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 243 static const bool __maybe_unused debug_evictions; /* = false */ 244 static const bool __maybe_unused no_system_mem_limit; 245 static const int __maybe_unused halt_if_hws_hang; 246 #endif 247 #ifdef CONFIG_HSA_AMD_P2P 248 extern bool pcie_p2p; 249 #endif 250 251 extern int amdgpu_tmz; 252 extern int amdgpu_reset_method; 253 254 #ifdef CONFIG_DRM_AMDGPU_SI 255 extern int amdgpu_si_support; 256 #endif 257 #ifdef CONFIG_DRM_AMDGPU_CIK 258 extern int amdgpu_cik_support; 259 #endif 260 extern int amdgpu_num_kcq; 261 262 #define AMDGPU_VCNFW_LOG_SIZE (32 * 1024) 263 #define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024) 264 extern int amdgpu_vcnfw_log; 265 extern int amdgpu_sg_display; 266 extern int amdgpu_umsch_mm; 267 extern int amdgpu_seamless; 268 extern int amdgpu_umsch_mm_fwlog; 269 270 extern int amdgpu_user_partt_mode; 271 extern int amdgpu_agp; 272 extern int amdgpu_rebar; 273 274 extern int amdgpu_wbrf; 275 extern int amdgpu_user_queue; 276 277 #define AMDGPU_VM_MAX_NUM_CTX 4096 278 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 279 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 280 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 281 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 282 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 283 #define AMDGPUFB_CONN_LIMIT 4 284 #define AMDGPU_BIOS_NUM_SCRATCH 16 285 286 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 287 288 /* hard reset data */ 289 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 290 291 /* reset flags */ 292 #define AMDGPU_RESET_GFX (1 << 0) 293 #define AMDGPU_RESET_COMPUTE (1 << 1) 294 #define AMDGPU_RESET_DMA (1 << 2) 295 #define AMDGPU_RESET_CP (1 << 3) 296 #define AMDGPU_RESET_GRBM (1 << 4) 297 #define AMDGPU_RESET_DMA1 (1 << 5) 298 #define AMDGPU_RESET_RLC (1 << 6) 299 #define AMDGPU_RESET_SEM (1 << 7) 300 #define AMDGPU_RESET_IH (1 << 8) 301 #define AMDGPU_RESET_VMC (1 << 9) 302 #define AMDGPU_RESET_MC (1 << 10) 303 #define AMDGPU_RESET_DISPLAY (1 << 11) 304 #define AMDGPU_RESET_UVD (1 << 12) 305 #define AMDGPU_RESET_VCE (1 << 13) 306 #define AMDGPU_RESET_VCE1 (1 << 14) 307 308 /* reset mask */ 309 #define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */ 310 #define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */ 311 #define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */ 312 #define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */ 313 314 /* max cursor sizes (in pixels) */ 315 #define CIK_CURSOR_WIDTH 128 316 #define CIK_CURSOR_HEIGHT 128 317 318 /* smart shift bias level limits */ 319 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 320 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 321 322 /* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */ 323 #define AMDGPU_SWCTF_EXTRA_DELAY 50 324 325 struct amdgpu_xcp_mgr; 326 struct amdgpu_device; 327 struct amdgpu_irq_src; 328 struct amdgpu_fpriv; 329 struct amdgpu_bo_va_mapping; 330 struct kfd_vm_fault_info; 331 struct amdgpu_hive_info; 332 struct amdgpu_reset_context; 333 struct amdgpu_reset_control; 334 335 enum amdgpu_cp_irq { 336 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 337 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 338 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 339 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 340 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 341 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 342 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 343 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 344 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 345 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 346 347 AMDGPU_CP_IRQ_LAST 348 }; 349 350 enum amdgpu_thermal_irq { 351 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 352 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 353 354 AMDGPU_THERMAL_IRQ_LAST 355 }; 356 357 enum amdgpu_kiq_irq { 358 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 359 AMDGPU_CP_KIQ_IRQ_LAST 360 }; 361 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 362 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 363 #define MAX_KIQ_REG_TRY 1000 364 365 int amdgpu_device_ip_set_clockgating_state(void *dev, 366 enum amd_ip_block_type block_type, 367 enum amd_clockgating_state state); 368 int amdgpu_device_ip_set_powergating_state(void *dev, 369 enum amd_ip_block_type block_type, 370 enum amd_powergating_state state); 371 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 372 u64 *flags); 373 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 374 enum amd_ip_block_type block_type); 375 bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, 376 enum amd_ip_block_type block_type); 377 bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, 378 enum amd_ip_block_type block_type); 379 int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); 380 381 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 382 383 #define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM 384 385 struct amdgpu_ip_block_status { 386 bool valid; 387 bool sw; 388 bool hw; 389 bool late_initialized; 390 bool hang; 391 }; 392 393 struct amdgpu_ip_block_version { 394 const enum amd_ip_block_type type; 395 const u32 major; 396 const u32 minor; 397 const u32 rev; 398 const struct amd_ip_funcs *funcs; 399 }; 400 401 struct amdgpu_ip_block { 402 struct amdgpu_ip_block_status status; 403 const struct amdgpu_ip_block_version *version; 404 struct amdgpu_device *adev; 405 }; 406 407 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 408 enum amd_ip_block_type type, 409 u32 major, u32 minor); 410 411 struct amdgpu_ip_block * 412 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 413 enum amd_ip_block_type type); 414 415 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 416 const struct amdgpu_ip_block_version *ip_block_version); 417 418 /* 419 * BIOS. 420 */ 421 bool amdgpu_get_bios(struct amdgpu_device *adev); 422 bool amdgpu_read_bios(struct amdgpu_device *adev); 423 bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, 424 u8 *bios, u32 length_bytes); 425 void amdgpu_bios_release(struct amdgpu_device *adev); 426 /* 427 * Clocks 428 */ 429 430 #define AMDGPU_MAX_PPLL 3 431 432 struct amdgpu_clock { 433 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 434 struct amdgpu_pll spll; 435 struct amdgpu_pll mpll; 436 /* 10 Khz units */ 437 uint32_t default_mclk; 438 uint32_t default_sclk; 439 uint32_t default_dispclk; 440 uint32_t dp_extclk; 441 uint32_t max_pixel_clock; 442 }; 443 444 /* sub-allocation manager, it has to be protected by another lock. 445 * By conception this is an helper for other part of the driver 446 * like the indirect buffer or semaphore, which both have their 447 * locking. 448 * 449 * Principe is simple, we keep a list of sub allocation in offset 450 * order (first entry has offset == 0, last entry has the highest 451 * offset). 452 * 453 * When allocating new object we first check if there is room at 454 * the end total_size - (last_object_offset + last_object_size) >= 455 * alloc_size. If so we allocate new object there. 456 * 457 * When there is not enough room at the end, we start waiting for 458 * each sub object until we reach object_offset+object_size >= 459 * alloc_size, this object then become the sub object we return. 460 * 461 * Alignment can't be bigger than page size. 462 * 463 * Hole are not considered for allocation to keep things simple. 464 * Assumption is that there won't be hole (all object on same 465 * alignment). 466 */ 467 468 struct amdgpu_sa_manager { 469 struct drm_suballoc_manager base; 470 struct amdgpu_bo *bo; 471 uint64_t gpu_addr; 472 void *cpu_ptr; 473 }; 474 475 /* 476 * IRQS. 477 */ 478 479 struct amdgpu_flip_work { 480 struct delayed_work flip_work; 481 struct work_struct unpin_work; 482 struct amdgpu_device *adev; 483 int crtc_id; 484 u32 target_vblank; 485 uint64_t base; 486 struct drm_pending_vblank_event *event; 487 struct amdgpu_bo *old_abo; 488 unsigned shared_count; 489 struct dma_fence **shared; 490 struct dma_fence_cb cb; 491 bool async; 492 }; 493 494 /* 495 * file private structure 496 */ 497 498 struct amdgpu_fpriv { 499 struct amdgpu_vm vm; 500 struct amdgpu_bo_va *prt_va; 501 struct amdgpu_bo_va *csa_va; 502 struct amdgpu_bo_va *seq64_va; 503 struct mutex bo_list_lock; 504 struct idr bo_list_handles; 505 struct amdgpu_ctx_mgr ctx_mgr; 506 struct amdgpu_userq_mgr userq_mgr; 507 508 /* Eviction fence infra */ 509 struct amdgpu_eviction_fence_mgr evf_mgr; 510 511 /** GPU partition selection */ 512 uint32_t xcp_id; 513 }; 514 515 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 516 517 /* 518 * Writeback 519 */ 520 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 521 522 /** 523 * amdgpu_wb - This struct is used for small GPU memory allocation. 524 * 525 * This struct is used to allocate a small amount of GPU memory that can be 526 * used to shadow certain states into the memory. This is especially useful for 527 * providing easy CPU access to some states without requiring register access 528 * (e.g., if some block is power gated, reading register may be problematic). 529 * 530 * Note: the term writeback was initially used because many of the amdgpu 531 * components had some level of writeback memory, and this struct initially 532 * described those components. 533 */ 534 struct amdgpu_wb { 535 536 /** 537 * @wb_obj: 538 * 539 * Buffer Object used for the writeback memory. 540 */ 541 struct amdgpu_bo *wb_obj; 542 543 /** 544 * @wb: 545 * 546 * Pointer to the first writeback slot. In terms of CPU address 547 * this value can be accessed directly by using the offset as an index. 548 * For the GPU address, it is necessary to use gpu_addr and the offset. 549 */ 550 uint32_t *wb; 551 552 /** 553 * @gpu_addr: 554 * 555 * Writeback base address in the GPU. 556 */ 557 uint64_t gpu_addr; 558 559 /** 560 * @num_wb: 561 * 562 * Number of writeback slots reserved for amdgpu. 563 */ 564 u32 num_wb; 565 566 /** 567 * @used: 568 * 569 * Track the writeback slot already used. 570 */ 571 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 572 573 /** 574 * @lock: 575 * 576 * Protects read and write of the used field array. 577 */ 578 spinlock_t lock; 579 }; 580 581 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 582 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 583 584 /* 585 * Benchmarking 586 */ 587 int amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 588 589 /* 590 * ASIC specific register table accessible by UMD 591 */ 592 struct amdgpu_allowed_register_entry { 593 uint32_t reg_offset; 594 bool grbm_indexed; 595 }; 596 597 /** 598 * enum amd_reset_method - Methods for resetting AMD GPU devices 599 * 600 * @AMD_RESET_METHOD_NONE: The device will not be reset. 601 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs. 602 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the 603 * any device. 604 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.) 605 * individually. Suitable only for some discrete GPU, not 606 * available for all ASICs. 607 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs 608 * are reset depends on the ASIC. Notably doesn't reset IPs 609 * shared with the CPU on APUs or the memory controllers (so 610 * VRAM is not lost). Not available on all ASICs. 611 * @AMD_RESET_LINK: Triggers SW-UP link reset on other GPUs 612 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card 613 * but without powering off the PCI bus. Suitable only for 614 * discrete GPUs. 615 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset 616 * and does a secondary bus reset or FLR, depending on what the 617 * underlying hardware supports. 618 * 619 * Methods available for AMD GPU driver for resetting the device. Not all 620 * methods are suitable for every device. User can override the method using 621 * module parameter `reset_method`. 622 */ 623 enum amd_reset_method { 624 AMD_RESET_METHOD_NONE = -1, 625 AMD_RESET_METHOD_LEGACY = 0, 626 AMD_RESET_METHOD_MODE0, 627 AMD_RESET_METHOD_MODE1, 628 AMD_RESET_METHOD_MODE2, 629 AMD_RESET_METHOD_LINK, 630 AMD_RESET_METHOD_BACO, 631 AMD_RESET_METHOD_PCI, 632 AMD_RESET_METHOD_ON_INIT, 633 }; 634 635 struct amdgpu_video_codec_info { 636 u32 codec_type; 637 u32 max_width; 638 u32 max_height; 639 u32 max_pixels_per_frame; 640 u32 max_level; 641 }; 642 643 #define codec_info_build(type, width, height, level) \ 644 .codec_type = type,\ 645 .max_width = width,\ 646 .max_height = height,\ 647 .max_pixels_per_frame = height * width,\ 648 .max_level = level, 649 650 struct amdgpu_video_codecs { 651 const u32 codec_count; 652 const struct amdgpu_video_codec_info *codec_array; 653 }; 654 655 /* 656 * ASIC specific functions. 657 */ 658 struct amdgpu_asic_funcs { 659 bool (*read_disabled_bios)(struct amdgpu_device *adev); 660 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 661 u8 *bios, u32 length_bytes); 662 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 663 u32 sh_num, u32 reg_offset, u32 *value); 664 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 665 int (*reset)(struct amdgpu_device *adev); 666 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 667 /* get the reference clock */ 668 u32 (*get_xclk)(struct amdgpu_device *adev); 669 /* MM block clocks */ 670 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 671 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 672 /* static power management */ 673 int (*get_pcie_lanes)(struct amdgpu_device *adev); 674 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 675 /* get config memsize register */ 676 u32 (*get_config_memsize)(struct amdgpu_device *adev); 677 /* flush hdp write queue */ 678 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 679 /* invalidate hdp read cache */ 680 void (*invalidate_hdp)(struct amdgpu_device *adev, 681 struct amdgpu_ring *ring); 682 /* check if the asic needs a full reset of if soft reset will work */ 683 bool (*need_full_reset)(struct amdgpu_device *adev); 684 /* initialize doorbell layout for specific asic*/ 685 void (*init_doorbell_index)(struct amdgpu_device *adev); 686 /* PCIe bandwidth usage */ 687 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 688 uint64_t *count1); 689 /* do we need to reset the asic at init time (e.g., kexec) */ 690 bool (*need_reset_on_init)(struct amdgpu_device *adev); 691 /* PCIe replay counter */ 692 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 693 /* device supports BACO */ 694 int (*supports_baco)(struct amdgpu_device *adev); 695 /* pre asic_init quirks */ 696 void (*pre_asic_init)(struct amdgpu_device *adev); 697 /* enter/exit umd stable pstate */ 698 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 699 /* query video codecs */ 700 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 701 const struct amdgpu_video_codecs **codecs); 702 /* encode "> 32bits" smn addressing */ 703 u64 (*encode_ext_smn_addressing)(int ext_id); 704 705 ssize_t (*get_reg_state)(struct amdgpu_device *adev, 706 enum amdgpu_reg_state reg_state, void *buf, 707 size_t max_size); 708 }; 709 710 /* 711 * IOCTL. 712 */ 713 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 714 struct drm_file *filp); 715 716 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 717 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 718 struct drm_file *filp); 719 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 720 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 721 struct drm_file *filp); 722 723 /* VRAM scratch page for HDP bug, default vram page */ 724 struct amdgpu_mem_scratch { 725 struct amdgpu_bo *robj; 726 uint32_t *ptr; 727 u64 gpu_addr; 728 }; 729 730 /* 731 * CGS 732 */ 733 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 734 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 735 736 /* 737 * Core structure, functions and helpers. 738 */ 739 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 740 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 741 742 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); 743 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); 744 745 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 746 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 747 748 typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); 749 typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); 750 751 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 752 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 753 754 struct amdgpu_mmio_remap { 755 u32 reg_offset; 756 resource_size_t bus_addr; 757 struct amdgpu_bo *bo; 758 }; 759 760 /* Define the HW IP blocks will be used in driver , add more if necessary */ 761 enum amd_hw_ip_block_type { 762 GC_HWIP = 1, 763 HDP_HWIP, 764 SDMA0_HWIP, 765 SDMA1_HWIP, 766 SDMA2_HWIP, 767 SDMA3_HWIP, 768 SDMA4_HWIP, 769 SDMA5_HWIP, 770 SDMA6_HWIP, 771 SDMA7_HWIP, 772 LSDMA_HWIP, 773 MMHUB_HWIP, 774 ATHUB_HWIP, 775 NBIO_HWIP, 776 MP0_HWIP, 777 MP1_HWIP, 778 UVD_HWIP, 779 VCN_HWIP = UVD_HWIP, 780 JPEG_HWIP = VCN_HWIP, 781 VCN1_HWIP, 782 VCE_HWIP, 783 VPE_HWIP, 784 DF_HWIP, 785 DCE_HWIP, 786 OSSSYS_HWIP, 787 SMUIO_HWIP, 788 PWR_HWIP, 789 NBIF_HWIP, 790 THM_HWIP, 791 CLK_HWIP, 792 UMC_HWIP, 793 RSMU_HWIP, 794 XGMI_HWIP, 795 DCI_HWIP, 796 PCIE_HWIP, 797 ISP_HWIP, 798 MAX_HWIP 799 }; 800 801 #define HWIP_MAX_INSTANCE 44 802 803 #define HW_ID_MAX 300 804 #define IP_VERSION_FULL(mj, mn, rv, var, srev) \ 805 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) 806 #define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) 807 #define IP_VERSION_MAJ(ver) ((ver) >> 24) 808 #define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) 809 #define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) 810 #define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) 811 #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) 812 #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) 813 814 struct amdgpu_ip_map_info { 815 /* Map of logical to actual dev instances/mask */ 816 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; 817 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, 818 enum amd_hw_ip_block_type block, 819 int8_t inst); 820 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, 821 enum amd_hw_ip_block_type block, 822 uint32_t mask); 823 }; 824 825 enum amdgpu_uid_type { 826 AMDGPU_UID_TYPE_XCD, 827 AMDGPU_UID_TYPE_AID, 828 AMDGPU_UID_TYPE_SOC, 829 AMDGPU_UID_TYPE_MAX 830 }; 831 832 #define AMDGPU_UID_INST_MAX 8 /* max number of instances for each UID type */ 833 834 struct amdgpu_uid { 835 uint64_t uid[AMDGPU_UID_TYPE_MAX][AMDGPU_UID_INST_MAX]; 836 struct amdgpu_device *adev; 837 }; 838 839 struct amd_powerplay { 840 void *pp_handle; 841 const struct amd_pm_funcs *pp_funcs; 842 }; 843 844 /* polaris10 kickers */ 845 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 846 ((rid == 0xE3) || \ 847 (rid == 0xE4) || \ 848 (rid == 0xE5) || \ 849 (rid == 0xE7) || \ 850 (rid == 0xEF))) || \ 851 ((did == 0x6FDF) && \ 852 ((rid == 0xE7) || \ 853 (rid == 0xEF) || \ 854 (rid == 0xFF)))) 855 856 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 857 ((rid == 0xE1) || \ 858 (rid == 0xF7))) 859 860 /* polaris11 kickers */ 861 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 862 ((rid == 0xE0) || \ 863 (rid == 0xE5))) || \ 864 ((did == 0x67FF) && \ 865 ((rid == 0xCF) || \ 866 (rid == 0xEF) || \ 867 (rid == 0xFF)))) 868 869 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 870 ((rid == 0xE2))) 871 872 /* polaris12 kickers */ 873 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 874 ((rid == 0xC0) || \ 875 (rid == 0xC1) || \ 876 (rid == 0xC3) || \ 877 (rid == 0xC7))) || \ 878 ((did == 0x6981) && \ 879 ((rid == 0x00) || \ 880 (rid == 0x01) || \ 881 (rid == 0x10)))) 882 883 struct amdgpu_mqd_prop { 884 uint64_t mqd_gpu_addr; 885 uint64_t hqd_base_gpu_addr; 886 uint64_t rptr_gpu_addr; 887 uint64_t wptr_gpu_addr; 888 uint32_t queue_size; 889 bool use_doorbell; 890 uint32_t doorbell_index; 891 uint64_t eop_gpu_addr; 892 uint32_t hqd_pipe_priority; 893 uint32_t hqd_queue_priority; 894 bool allow_tunneling; 895 bool hqd_active; 896 uint64_t shadow_addr; 897 uint64_t gds_bkup_addr; 898 uint64_t csa_addr; 899 uint64_t fence_address; 900 bool tmz_queue; 901 bool kernel_queue; 902 }; 903 904 struct amdgpu_mqd { 905 unsigned mqd_size; 906 int (*init_mqd)(struct amdgpu_device *adev, void *mqd, 907 struct amdgpu_mqd_prop *p); 908 }; 909 910 struct amdgpu_pcie_reset_ctx { 911 bool in_link_reset; 912 bool occurs_dpc; 913 bool audio_suspended; 914 struct pci_dev *swus; 915 struct pci_saved_state *swus_pcistate; 916 struct pci_saved_state *swds_pcistate; 917 }; 918 919 /* 920 * Custom Init levels could be defined for different situations where a full 921 * initialization of all hardware blocks are not expected. Sample cases are 922 * custom init sequences after resume after S0i3/S3, reset on initialization, 923 * partial reset of blocks etc. Presently, this defines only two levels. Levels 924 * are described in corresponding struct definitions - amdgpu_init_default, 925 * amdgpu_init_minimal_xgmi. 926 */ 927 enum amdgpu_init_lvl_id { 928 AMDGPU_INIT_LEVEL_DEFAULT, 929 AMDGPU_INIT_LEVEL_MINIMAL_XGMI, 930 AMDGPU_INIT_LEVEL_RESET_RECOVERY, 931 }; 932 933 struct amdgpu_init_level { 934 enum amdgpu_init_lvl_id level; 935 uint32_t hwini_ip_block_mask; 936 }; 937 938 #define AMDGPU_RESET_MAGIC_NUM 64 939 #define AMDGPU_MAX_DF_PERFMONS 4 940 struct amdgpu_reset_domain; 941 struct amdgpu_fru_info; 942 943 enum amdgpu_enforce_isolation_mode { 944 AMDGPU_ENFORCE_ISOLATION_DISABLE = 0, 945 AMDGPU_ENFORCE_ISOLATION_ENABLE = 1, 946 AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY = 2, 947 AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER = 3, 948 }; 949 950 struct amdgpu_device { 951 struct device *dev; 952 struct pci_dev *pdev; 953 struct drm_device ddev; 954 955 #ifdef CONFIG_DRM_AMD_ACP 956 struct amdgpu_acp acp; 957 #endif 958 struct amdgpu_hive_info *hive; 959 struct amdgpu_xcp_mgr *xcp_mgr; 960 /* ASIC */ 961 enum amd_asic_type asic_type; 962 uint32_t family; 963 uint32_t rev_id; 964 uint32_t external_rev_id; 965 unsigned long flags; 966 unsigned long apu_flags; 967 int usec_timeout; 968 const struct amdgpu_asic_funcs *asic_funcs; 969 bool shutdown; 970 bool need_swiotlb; 971 bool accel_working; 972 struct notifier_block acpi_nb; 973 struct notifier_block pm_nb; 974 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 975 struct debugfs_blob_wrapper debugfs_vbios_blob; 976 struct mutex srbm_mutex; 977 /* GRBM index mutex. Protects concurrent access to GRBM index */ 978 struct mutex grbm_idx_mutex; 979 struct dev_pm_domain vga_pm_domain; 980 bool have_disp_power_ref; 981 bool have_atomics_support; 982 983 /* BIOS */ 984 bool is_atom_fw; 985 uint8_t *bios; 986 uint32_t bios_size; 987 uint32_t bios_scratch_reg_offset; 988 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 989 990 /* Register/doorbell mmio */ 991 resource_size_t rmmio_base; 992 resource_size_t rmmio_size; 993 void __iomem *rmmio; 994 /* protects concurrent MM_INDEX/DATA based register access */ 995 spinlock_t mmio_idx_lock; 996 struct amdgpu_mmio_remap rmmio_remap; 997 /* protects concurrent SMC based register access */ 998 spinlock_t smc_idx_lock; 999 amdgpu_rreg_t smc_rreg; 1000 amdgpu_wreg_t smc_wreg; 1001 /* protects concurrent PCIE register access */ 1002 spinlock_t pcie_idx_lock; 1003 amdgpu_rreg_t pcie_rreg; 1004 amdgpu_wreg_t pcie_wreg; 1005 amdgpu_rreg_t pciep_rreg; 1006 amdgpu_wreg_t pciep_wreg; 1007 amdgpu_rreg_ext_t pcie_rreg_ext; 1008 amdgpu_wreg_ext_t pcie_wreg_ext; 1009 amdgpu_rreg64_t pcie_rreg64; 1010 amdgpu_wreg64_t pcie_wreg64; 1011 amdgpu_rreg64_ext_t pcie_rreg64_ext; 1012 amdgpu_wreg64_ext_t pcie_wreg64_ext; 1013 /* protects concurrent UVD register access */ 1014 spinlock_t uvd_ctx_idx_lock; 1015 amdgpu_rreg_t uvd_ctx_rreg; 1016 amdgpu_wreg_t uvd_ctx_wreg; 1017 /* protects concurrent DIDT register access */ 1018 spinlock_t didt_idx_lock; 1019 amdgpu_rreg_t didt_rreg; 1020 amdgpu_wreg_t didt_wreg; 1021 /* protects concurrent gc_cac register access */ 1022 spinlock_t gc_cac_idx_lock; 1023 amdgpu_rreg_t gc_cac_rreg; 1024 amdgpu_wreg_t gc_cac_wreg; 1025 /* protects concurrent se_cac register access */ 1026 spinlock_t se_cac_idx_lock; 1027 amdgpu_rreg_t se_cac_rreg; 1028 amdgpu_wreg_t se_cac_wreg; 1029 /* protects concurrent ENDPOINT (audio) register access */ 1030 spinlock_t audio_endpt_idx_lock; 1031 amdgpu_block_rreg_t audio_endpt_rreg; 1032 amdgpu_block_wreg_t audio_endpt_wreg; 1033 struct amdgpu_doorbell doorbell; 1034 1035 /* clock/pll info */ 1036 struct amdgpu_clock clock; 1037 1038 /* MC */ 1039 struct amdgpu_gmc gmc; 1040 struct amdgpu_gart gart; 1041 dma_addr_t dummy_page_addr; 1042 struct amdgpu_vm_manager vm_manager; 1043 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1044 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS); 1045 1046 /* memory management */ 1047 struct amdgpu_mman mman; 1048 struct amdgpu_mem_scratch mem_scratch; 1049 struct amdgpu_wb wb; 1050 atomic64_t num_bytes_moved; 1051 atomic64_t num_evictions; 1052 atomic64_t num_vram_cpu_page_faults; 1053 atomic_t gpu_reset_counter; 1054 atomic_t vram_lost_counter; 1055 1056 /* data for buffer migration throttling */ 1057 struct { 1058 spinlock_t lock; 1059 s64 last_update_us; 1060 s64 accum_us; /* accumulated microseconds */ 1061 s64 accum_us_vis; /* for visible VRAM */ 1062 u32 log2_max_MBps; 1063 } mm_stats; 1064 1065 /* discovery*/ 1066 struct amdgpu_discovery_info discovery; 1067 1068 /* display */ 1069 bool enable_virtual_display; 1070 struct amdgpu_vkms_output *amdgpu_vkms_output; 1071 struct amdgpu_mode_info mode_info; 1072 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 1073 struct delayed_work hotplug_work; 1074 struct amdgpu_irq_src crtc_irq; 1075 struct amdgpu_irq_src vline0_irq; 1076 struct amdgpu_irq_src vupdate_irq; 1077 struct amdgpu_irq_src pageflip_irq; 1078 struct amdgpu_irq_src hpd_irq; 1079 struct amdgpu_irq_src dmub_trace_irq; 1080 struct amdgpu_irq_src dmub_outbox_irq; 1081 1082 /* rings */ 1083 u64 fence_context; 1084 unsigned num_rings; 1085 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1086 struct dma_fence __rcu *gang_submit; 1087 bool ib_pool_ready; 1088 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 1089 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 1090 1091 /* interrupts */ 1092 struct amdgpu_irq irq; 1093 1094 /* powerplay */ 1095 struct amd_powerplay powerplay; 1096 struct amdgpu_pm pm; 1097 u64 cg_flags; 1098 u32 pg_flags; 1099 1100 /* nbio */ 1101 struct amdgpu_nbio nbio; 1102 1103 /* hdp */ 1104 struct amdgpu_hdp hdp; 1105 1106 /* smuio */ 1107 struct amdgpu_smuio smuio; 1108 1109 /* mmhub */ 1110 struct amdgpu_mmhub mmhub; 1111 1112 /* gfxhub */ 1113 struct amdgpu_gfxhub gfxhub; 1114 1115 /* gfx */ 1116 struct amdgpu_gfx gfx; 1117 1118 /* sdma */ 1119 struct amdgpu_sdma sdma; 1120 1121 /* lsdma */ 1122 struct amdgpu_lsdma lsdma; 1123 1124 /* uvd */ 1125 struct amdgpu_uvd uvd; 1126 1127 /* vce */ 1128 struct amdgpu_vce vce; 1129 1130 /* vcn */ 1131 struct amdgpu_vcn vcn; 1132 1133 /* jpeg */ 1134 struct amdgpu_jpeg jpeg; 1135 1136 /* vpe */ 1137 struct amdgpu_vpe vpe; 1138 1139 /* umsch */ 1140 struct amdgpu_umsch_mm umsch_mm; 1141 bool enable_umsch_mm; 1142 1143 /* firmwares */ 1144 struct amdgpu_firmware firmware; 1145 1146 /* PSP */ 1147 struct psp_context psp; 1148 1149 /* GDS */ 1150 struct amdgpu_gds gds; 1151 1152 /* for userq and VM fences */ 1153 struct amdgpu_seq64 seq64; 1154 1155 /* UMC */ 1156 struct amdgpu_umc umc; 1157 1158 /* display related functionality */ 1159 struct amdgpu_display_manager dm; 1160 1161 #if defined(CONFIG_DRM_AMD_ISP) 1162 /* isp */ 1163 struct amdgpu_isp isp; 1164 #endif 1165 1166 /* mes */ 1167 bool enable_mes; 1168 bool enable_mes_kiq; 1169 bool enable_uni_mes; 1170 struct amdgpu_mes mes; 1171 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM]; 1172 const struct amdgpu_userq_funcs *userq_funcs[AMDGPU_HW_IP_NUM]; 1173 1174 /* xarray used to retrieve the user queue fence driver reference 1175 * in the EOP interrupt handler to signal the particular user 1176 * queue fence. 1177 */ 1178 struct xarray userq_xa; 1179 /** 1180 * @userq_doorbell_xa: Global user queue map (doorbell index → queue) 1181 * Key: doorbell_index (unique global identifier for the queue) 1182 * Value: struct amdgpu_usermode_queue 1183 */ 1184 struct xarray userq_doorbell_xa; 1185 1186 /* df */ 1187 struct amdgpu_df df; 1188 1189 /* MCA */ 1190 struct amdgpu_mca mca; 1191 1192 /* ACA */ 1193 struct amdgpu_aca aca; 1194 1195 /* CPER */ 1196 struct amdgpu_cper cper; 1197 1198 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1199 uint32_t harvest_ip_mask; 1200 int num_ip_blocks; 1201 struct mutex mn_lock; 1202 DECLARE_HASHTABLE(mn_hash, 7); 1203 1204 /* tracking pinned memory */ 1205 atomic64_t vram_pin_size; 1206 atomic64_t visible_pin_size; 1207 atomic64_t gart_pin_size; 1208 1209 /* soc15 register offset based on ip, instance and segment */ 1210 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1211 struct amdgpu_ip_map_info ip_map; 1212 1213 /* delayed work_func for deferring clockgating during resume */ 1214 struct delayed_work delayed_init_work; 1215 1216 struct amdgpu_virt virt; 1217 1218 /* record hw reset is performed */ 1219 bool has_hw_reset; 1220 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1221 1222 /* s3/s4 mask */ 1223 bool in_suspend; 1224 bool in_s3; 1225 bool in_s4; 1226 bool in_s0ix; 1227 suspend_state_t last_suspend_state; 1228 1229 enum pp_mp1_state mp1_state; 1230 struct amdgpu_doorbell_index doorbell_index; 1231 1232 struct mutex notifier_lock; 1233 1234 int asic_reset_res; 1235 struct work_struct xgmi_reset_work; 1236 struct list_head reset_list; 1237 1238 long gfx_timeout; 1239 long sdma_timeout; 1240 long video_timeout; 1241 long compute_timeout; 1242 long psp_timeout; 1243 1244 uint64_t unique_id; 1245 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1246 1247 /* enable runtime pm on the device */ 1248 bool in_runpm; 1249 bool has_pr3; 1250 1251 bool ucode_sysfs_en; 1252 1253 struct amdgpu_fru_info *fru_info; 1254 atomic_t throttling_logging_enabled; 1255 struct ratelimit_state throttling_logging_rs; 1256 uint32_t ras_hw_enabled; 1257 uint32_t ras_enabled; 1258 bool ras_default_ecc_enabled; 1259 1260 bool no_hw_access; 1261 struct pci_saved_state *pci_state; 1262 pci_channel_state_t pci_channel_state; 1263 1264 struct amdgpu_pcie_reset_ctx pcie_reset_ctx; 1265 1266 /* Track auto wait count on s_barrier settings */ 1267 bool barrier_has_auto_waitcnt; 1268 1269 struct amdgpu_reset_control *reset_cntl; 1270 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE]; 1271 1272 bool ram_is_direct_mapped; 1273 1274 struct list_head ras_list; 1275 1276 struct amdgpu_reset_domain *reset_domain; 1277 1278 struct mutex benchmark_mutex; 1279 1280 bool scpm_enabled; 1281 uint32_t scpm_status; 1282 1283 struct work_struct reset_work; 1284 1285 bool dc_enabled; 1286 /* Mask of active clusters */ 1287 uint32_t aid_mask; 1288 1289 /* Debug */ 1290 bool debug_vm; 1291 bool debug_largebar; 1292 bool debug_disable_soft_recovery; 1293 bool debug_use_vram_fw_buf; 1294 bool debug_enable_ras_aca; 1295 bool debug_exp_resets; 1296 bool debug_disable_gpu_ring_reset; 1297 bool debug_vm_userptr; 1298 bool debug_disable_ce_logs; 1299 bool debug_enable_ce_cs; 1300 1301 /* Protection for the following isolation structure */ 1302 struct mutex enforce_isolation_mutex; 1303 enum amdgpu_enforce_isolation_mode enforce_isolation[MAX_XCP]; 1304 struct amdgpu_isolation { 1305 void *owner; 1306 struct dma_fence *spearhead; 1307 struct amdgpu_sync active; 1308 struct amdgpu_sync prev; 1309 } isolation[MAX_XCP]; 1310 1311 struct amdgpu_init_level *init_lvl; 1312 1313 /* This flag is used to determine how VRAM allocations are handled for APUs 1314 * in KFD: VRAM or GTT. 1315 */ 1316 bool apu_prefer_gtt; 1317 1318 bool userq_halt_for_enforce_isolation; 1319 struct work_struct userq_reset_work; 1320 struct amdgpu_uid *uid_info; 1321 1322 /* KFD 1323 * Must be last --ends in a flexible-array member. 1324 */ 1325 struct amdgpu_kfd_dev kfd; 1326 }; 1327 1328 static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, 1329 uint8_t ip, uint8_t inst) 1330 { 1331 /* This considers only major/minor/rev and ignores 1332 * subrevision/variant fields. 1333 */ 1334 return adev->ip_versions[ip][inst] & ~0xFFU; 1335 } 1336 1337 static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, 1338 uint8_t ip, uint8_t inst) 1339 { 1340 /* This returns full version - major/minor/rev/variant/subrevision */ 1341 return adev->ip_versions[ip][inst]; 1342 } 1343 1344 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1345 { 1346 return container_of(ddev, struct amdgpu_device, ddev); 1347 } 1348 1349 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1350 { 1351 return &adev->ddev; 1352 } 1353 1354 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1355 { 1356 return container_of(bdev, struct amdgpu_device, mman.bdev); 1357 } 1358 1359 static inline bool amdgpu_is_multi_aid(struct amdgpu_device *adev) 1360 { 1361 return !!adev->aid_mask; 1362 } 1363 1364 int amdgpu_device_init(struct amdgpu_device *adev, 1365 uint32_t flags); 1366 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1367 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1368 1369 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1370 1371 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1372 void *buf, size_t size, bool write); 1373 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1374 void *buf, size_t size, bool write); 1375 1376 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1377 void *buf, size_t size, bool write); 1378 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, 1379 uint32_t inst, uint32_t reg_addr, char reg_name[], 1380 uint32_t expected_value, uint32_t mask); 1381 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1382 uint32_t reg, uint32_t acc_flags); 1383 u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, 1384 u64 reg_addr); 1385 uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, 1386 uint32_t reg, uint32_t acc_flags, 1387 uint32_t xcc_id); 1388 void amdgpu_device_wreg(struct amdgpu_device *adev, 1389 uint32_t reg, uint32_t v, 1390 uint32_t acc_flags); 1391 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, 1392 u64 reg_addr, u32 reg_data); 1393 void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, 1394 uint32_t reg, uint32_t v, 1395 uint32_t acc_flags, 1396 uint32_t xcc_id); 1397 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1398 uint32_t reg, uint32_t v, uint32_t xcc_id); 1399 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1400 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1401 1402 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1403 u32 reg_addr); 1404 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1405 u32 reg_addr); 1406 u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, 1407 u64 reg_addr); 1408 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1409 u32 reg_addr, u32 reg_data); 1410 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1411 u32 reg_addr, u64 reg_data); 1412 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, 1413 u64 reg_addr, u64 reg_data); 1414 u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); 1415 bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 1416 enum amd_asic_type asic_type); 1417 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1418 1419 void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev); 1420 1421 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1422 struct amdgpu_reset_context *reset_context); 1423 1424 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1425 struct amdgpu_reset_context *reset_context); 1426 1427 int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); 1428 1429 int emu_soc_asic_init(struct amdgpu_device *adev); 1430 1431 /* 1432 * Registers read & write functions. 1433 */ 1434 #define AMDGPU_REGS_NO_KIQ (1<<1) 1435 #define AMDGPU_REGS_RLC (1<<2) 1436 1437 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1438 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1439 1440 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0) 1441 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0) 1442 1443 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1444 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1445 1446 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1447 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1448 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1449 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1450 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1451 #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) 1452 #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) 1453 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1454 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1455 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1456 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1457 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) 1458 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) 1459 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1460 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1461 #define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) 1462 #define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) 1463 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1464 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1465 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1466 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1467 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1468 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1469 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1470 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1471 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1472 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1473 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1474 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1475 #define WREG32_P(reg, val, mask) \ 1476 do { \ 1477 uint32_t tmp_ = RREG32(reg); \ 1478 tmp_ &= (mask); \ 1479 tmp_ |= ((val) & ~(mask)); \ 1480 WREG32(reg, tmp_); \ 1481 } while (0) 1482 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1483 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1484 #define WREG32_PLL_P(reg, val, mask) \ 1485 do { \ 1486 uint32_t tmp_ = RREG32_PLL(reg); \ 1487 tmp_ &= (mask); \ 1488 tmp_ |= ((val) & ~(mask)); \ 1489 WREG32_PLL(reg, tmp_); \ 1490 } while (0) 1491 1492 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1493 do { \ 1494 u32 tmp = RREG32_SMC(_Reg); \ 1495 tmp &= (_Mask); \ 1496 tmp |= ((_Val) & ~(_Mask)); \ 1497 WREG32_SMC(_Reg, tmp); \ 1498 } while (0) 1499 1500 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1501 1502 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1503 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1504 1505 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1506 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1507 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1508 1509 #define REG_GET_FIELD(value, reg, field) \ 1510 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1511 1512 #define WREG32_FIELD(reg, field, val) \ 1513 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1514 1515 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1516 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1517 1518 #define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l)) 1519 /* 1520 * BIOS helpers. 1521 */ 1522 #define RBIOS8(i) (adev->bios[i]) 1523 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1524 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1525 1526 /* 1527 * ASICs macro. 1528 */ 1529 #define amdgpu_asic_set_vga_state(adev, state) \ 1530 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0) 1531 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1532 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1533 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1534 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1535 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1536 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1537 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1538 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1539 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1540 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1541 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1542 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1543 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1544 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1545 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1546 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1547 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1548 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1549 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1550 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1551 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1552 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1553 1554 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)) 1555 1556 #define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i)) 1557 #define for_each_inst(i, inst_mask) \ 1558 for (i = ffs(inst_mask); i-- != 0; \ 1559 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1))) 1560 1561 /* Common functions */ 1562 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1563 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1564 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1565 struct amdgpu_job *job, 1566 struct amdgpu_reset_context *reset_context); 1567 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1568 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1569 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1570 bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev); 1571 bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); 1572 1573 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1574 u64 num_vis_bytes); 1575 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1576 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1577 const u32 *registers, 1578 const u32 array_size); 1579 1580 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1581 int amdgpu_device_link_reset(struct amdgpu_device *adev); 1582 bool amdgpu_device_supports_atpx(struct amdgpu_device *adev); 1583 bool amdgpu_device_supports_px(struct amdgpu_device *adev); 1584 bool amdgpu_device_supports_boco(struct amdgpu_device *adev); 1585 bool amdgpu_device_supports_smart_shift(struct amdgpu_device *adev); 1586 int amdgpu_device_supports_baco(struct amdgpu_device *adev); 1587 void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev); 1588 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1589 struct amdgpu_device *peer_adev); 1590 int amdgpu_device_baco_enter(struct amdgpu_device *adev); 1591 int amdgpu_device_baco_exit(struct amdgpu_device *adev); 1592 1593 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1594 struct amdgpu_ring *ring); 1595 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1596 struct amdgpu_ring *ring); 1597 1598 void amdgpu_device_halt(struct amdgpu_device *adev); 1599 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, 1600 u32 reg); 1601 void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, 1602 u32 reg, u32 v); 1603 struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); 1604 struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, 1605 struct dma_fence *gang); 1606 struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, 1607 struct amdgpu_ring *ring, 1608 struct amdgpu_job *job); 1609 bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); 1610 ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); 1611 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); 1612 1613 /* atpx handler */ 1614 #if defined(CONFIG_VGA_SWITCHEROO) 1615 void amdgpu_register_atpx_handler(void); 1616 void amdgpu_unregister_atpx_handler(void); 1617 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1618 bool amdgpu_is_atpx_hybrid(void); 1619 bool amdgpu_has_atpx(void); 1620 #else 1621 static inline void amdgpu_register_atpx_handler(void) {} 1622 static inline void amdgpu_unregister_atpx_handler(void) {} 1623 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1624 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1625 static inline bool amdgpu_has_atpx(void) { return false; } 1626 #endif 1627 1628 /* 1629 * KMS 1630 */ 1631 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1632 extern const int amdgpu_max_kms_ioctl; 1633 1634 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1635 void amdgpu_driver_unload_kms(struct drm_device *dev); 1636 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1637 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1638 struct drm_file *file_priv); 1639 void amdgpu_driver_release_kms(struct drm_device *dev); 1640 1641 int amdgpu_device_prepare(struct drm_device *dev); 1642 void amdgpu_device_complete(struct drm_device *dev); 1643 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1644 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1645 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1646 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1647 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1648 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1649 struct drm_file *filp); 1650 1651 /* 1652 * functions used by amdgpu_encoder.c 1653 */ 1654 struct amdgpu_afmt_acr { 1655 u32 clock; 1656 1657 int n_32khz; 1658 int cts_32khz; 1659 1660 int n_44_1khz; 1661 int cts_44_1khz; 1662 1663 int n_48khz; 1664 int cts_48khz; 1665 1666 }; 1667 1668 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1669 1670 /* amdgpu_acpi.c */ 1671 1672 struct amdgpu_numa_info { 1673 uint64_t size; 1674 int pxm; 1675 int nid; 1676 }; 1677 1678 /* ATCS Device/Driver State */ 1679 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1680 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1681 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1682 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1683 1684 #if defined(CONFIG_ACPI) 1685 int amdgpu_acpi_init(struct amdgpu_device *adev); 1686 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1687 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1688 bool amdgpu_acpi_is_power_shift_control_supported(void); 1689 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1690 u8 perf_req, bool advertise); 1691 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1692 u8 dev_state, bool drv_state); 1693 int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1694 enum amdgpu_ss ss_state); 1695 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1696 int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, 1697 u64 *tmr_size); 1698 int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, 1699 struct amdgpu_numa_info *numa_info); 1700 1701 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1702 bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); 1703 void amdgpu_acpi_detect(void); 1704 void amdgpu_acpi_release(void); 1705 #else 1706 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1707 static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, 1708 u64 *tmr_offset, u64 *tmr_size) 1709 { 1710 return -EINVAL; 1711 } 1712 static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, 1713 int xcc_id, 1714 struct amdgpu_numa_info *numa_info) 1715 { 1716 return -EINVAL; 1717 } 1718 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1719 static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } 1720 static inline void amdgpu_acpi_detect(void) { } 1721 static inline void amdgpu_acpi_release(void) { } 1722 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1723 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1724 u8 dev_state, bool drv_state) { return 0; } 1725 static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, 1726 enum amdgpu_ss ss_state) 1727 { 1728 return 0; 1729 } 1730 static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } 1731 #endif 1732 1733 #if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND) 1734 bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev); 1735 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1736 #else 1737 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1738 static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; } 1739 #endif 1740 1741 #if defined(CONFIG_DRM_AMD_ISP) 1742 int amdgpu_acpi_get_isp4_dev(struct acpi_device **dev); 1743 #endif 1744 1745 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1746 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1747 1748 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1749 pci_channel_state_t state); 1750 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1751 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1752 void amdgpu_pci_resume(struct pci_dev *pdev); 1753 1754 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1755 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1756 1757 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1758 1759 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1760 enum amd_clockgating_state state); 1761 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1762 enum amd_powergating_state state); 1763 1764 static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev) 1765 { 1766 return amdgpu_gpu_recovery != 0 && 1767 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT && 1768 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT && 1769 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT && 1770 adev->video_timeout != MAX_SCHEDULE_TIMEOUT; 1771 } 1772 1773 #include "amdgpu_object.h" 1774 1775 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1776 { 1777 return adev->gmc.tmz_enabled; 1778 } 1779 1780 int amdgpu_in_reset(struct amdgpu_device *adev); 1781 1782 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 1783 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 1784 extern const struct attribute_group amdgpu_flash_attr_group; 1785 1786 void amdgpu_set_init_level(struct amdgpu_device *adev, 1787 enum amdgpu_init_lvl_id lvl); 1788 1789 static inline int amdgpu_device_bus_status_check(struct amdgpu_device *adev) 1790 { 1791 u32 status; 1792 int r; 1793 1794 r = pci_read_config_dword(adev->pdev, PCI_COMMAND, &status); 1795 if (r || PCI_POSSIBLE_ERROR(status)) { 1796 dev_err(adev->dev, "device lost from bus!"); 1797 return -ENODEV; 1798 } 1799 1800 return 0; 1801 } 1802 1803 void amdgpu_device_set_uid(struct amdgpu_uid *uid_info, 1804 enum amdgpu_uid_type type, uint8_t inst, 1805 uint64_t uid); 1806 uint64_t amdgpu_device_get_uid(struct amdgpu_uid *uid_info, 1807 enum amdgpu_uid_type type, uint8_t inst); 1808 #endif 1809