1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "aldebaran.h" 25 #include "amdgpu_reset.h" 26 #include "amdgpu_amdkfd.h" 27 #include "amdgpu_dpm.h" 28 #include "amdgpu_job.h" 29 #include "amdgpu_ring.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_xgmi.h" 33 34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) 35 { 36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 37 38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 39 adev->gmc.xgmi.connected_to_cpu)) 40 return true; 41 42 return false; 43 } 44 45 static struct amdgpu_reset_handler * 46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, 47 struct amdgpu_reset_context *reset_context) 48 { 49 struct amdgpu_reset_handler *handler; 50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 51 int i; 52 53 if (reset_context->method != AMD_RESET_METHOD_NONE) { 54 dev_dbg(adev->dev, "Getting reset handler for method %d\n", 55 reset_context->method); 56 for_each_handler(i, handler, reset_ctl) { 57 if (handler->reset_method == reset_context->method) 58 return handler; 59 } 60 } 61 62 if (aldebaran_is_mode2_default(reset_ctl)) { 63 for_each_handler(i, handler, reset_ctl) { 64 if (handler->reset_method == AMD_RESET_METHOD_MODE2) { 65 reset_context->method = AMD_RESET_METHOD_MODE2; 66 return handler; 67 } 68 } 69 } 70 71 dev_dbg(adev->dev, "Reset handler not found!\n"); 72 73 return NULL; 74 } 75 76 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) 77 { 78 int r, i; 79 80 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 81 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 82 83 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 84 if (!(adev->ip_blocks[i].version->type == 85 AMD_IP_BLOCK_TYPE_GFX || 86 adev->ip_blocks[i].version->type == 87 AMD_IP_BLOCK_TYPE_SDMA)) 88 continue; 89 90 r = adev->ip_blocks[i].version->funcs->suspend(adev); 91 92 if (r) { 93 dev_err(adev->dev, 94 "suspend of IP block <%s> failed %d\n", 95 adev->ip_blocks[i].version->funcs->name, r); 96 return r; 97 } 98 99 adev->ip_blocks[i].status.hw = false; 100 } 101 102 return r; 103 } 104 105 static int 106 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, 107 struct amdgpu_reset_context *reset_context) 108 { 109 int r = 0; 110 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 111 112 dev_dbg(adev->dev, "Aldebaran prepare hw context\n"); 113 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ 114 if (!amdgpu_sriov_vf(adev)) 115 r = aldebaran_mode2_suspend_ip(adev); 116 117 return r; 118 } 119 120 static void aldebaran_async_reset(struct work_struct *work) 121 { 122 struct amdgpu_reset_handler *handler; 123 struct amdgpu_reset_control *reset_ctl = 124 container_of(work, struct amdgpu_reset_control, reset_work); 125 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 126 int i; 127 128 for_each_handler(i, handler, reset_ctl) { 129 if (handler->reset_method == reset_ctl->active_reset) { 130 dev_dbg(adev->dev, "Resetting device\n"); 131 handler->do_reset(adev); 132 break; 133 } 134 } 135 } 136 137 static int aldebaran_mode2_reset(struct amdgpu_device *adev) 138 { 139 /* disable BM */ 140 pci_clear_master(adev->pdev); 141 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev); 142 return adev->asic_reset_res; 143 } 144 145 static int 146 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 147 struct amdgpu_reset_context *reset_context) 148 { 149 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 150 struct list_head *reset_device_list = reset_context->reset_device_list; 151 struct amdgpu_device *tmp_adev = NULL; 152 int r = 0; 153 154 dev_dbg(adev->dev, "aldebaran perform hw reset\n"); 155 156 if (reset_device_list == NULL) 157 return -EINVAL; 158 159 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 160 reset_context->hive == NULL) { 161 /* Wrong context, return error */ 162 return -EINVAL; 163 } 164 165 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 166 mutex_lock(&tmp_adev->reset_cntl->reset_lock); 167 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; 168 } 169 /* 170 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch 171 * them together so that they can be completed asynchronously on multiple nodes 172 */ 173 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 174 /* For XGMI run all resets in parallel to speed up the process */ 175 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 176 if (!queue_work(system_unbound_wq, 177 &tmp_adev->reset_cntl->reset_work)) 178 r = -EALREADY; 179 } else 180 r = aldebaran_mode2_reset(tmp_adev); 181 if (r) { 182 dev_err(tmp_adev->dev, 183 "ASIC reset failed with error, %d for drm dev, %s", 184 r, adev_to_drm(tmp_adev)->unique); 185 break; 186 } 187 } 188 189 /* For XGMI wait for all resets to complete before proceed */ 190 if (!r) { 191 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 192 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 193 flush_work(&tmp_adev->reset_cntl->reset_work); 194 r = tmp_adev->asic_reset_res; 195 if (r) 196 break; 197 } 198 } 199 } 200 201 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 202 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); 203 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; 204 } 205 206 return r; 207 } 208 209 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 210 { 211 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM]; 212 struct amdgpu_firmware_info *ucode; 213 struct amdgpu_ip_block *cmn_block; 214 int ucode_count = 0; 215 int i, r; 216 217 dev_dbg(adev->dev, "Reloading ucodes after reset\n"); 218 for (i = 0; i < adev->firmware.max_ucodes; i++) { 219 ucode = &adev->firmware.ucode[i]; 220 if (!ucode->fw) 221 continue; 222 switch (ucode->ucode_id) { 223 case AMDGPU_UCODE_ID_SDMA0: 224 case AMDGPU_UCODE_ID_SDMA1: 225 case AMDGPU_UCODE_ID_SDMA2: 226 case AMDGPU_UCODE_ID_SDMA3: 227 case AMDGPU_UCODE_ID_SDMA4: 228 case AMDGPU_UCODE_ID_SDMA5: 229 case AMDGPU_UCODE_ID_SDMA6: 230 case AMDGPU_UCODE_ID_SDMA7: 231 case AMDGPU_UCODE_ID_CP_MEC1: 232 case AMDGPU_UCODE_ID_CP_MEC1_JT: 233 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 234 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 235 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 236 case AMDGPU_UCODE_ID_RLC_G: 237 ucode_list[ucode_count++] = ucode; 238 break; 239 default: 240 break; 241 } 242 } 243 244 /* Reinit NBIF block */ 245 cmn_block = 246 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON); 247 if (unlikely(!cmn_block)) { 248 dev_err(adev->dev, "Failed to get BIF handle\n"); 249 return -EINVAL; 250 } 251 r = cmn_block->version->funcs->resume(adev); 252 if (r) 253 return r; 254 255 /* Reinit GFXHUB */ 256 adev->gfxhub.funcs->init(adev); 257 r = adev->gfxhub.funcs->gart_enable(adev); 258 if (r) { 259 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n"); 260 return r; 261 } 262 263 /* Reload GFX firmware */ 264 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count); 265 if (r) { 266 dev_err(adev->dev, "GFX ucode load failed after reset\n"); 267 return r; 268 } 269 270 /* Resume RLC, FW needs RLC alive to complete reset process */ 271 adev->gfx.rlc.funcs->resume(adev); 272 273 /* Wait for FW reset event complete */ 274 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0); 275 if (r) { 276 dev_err(adev->dev, 277 "Failed to get response from firmware after reset\n"); 278 return r; 279 } 280 281 for (i = 0; i < adev->num_ip_blocks; i++) { 282 if (!(adev->ip_blocks[i].version->type == 283 AMD_IP_BLOCK_TYPE_GFX || 284 adev->ip_blocks[i].version->type == 285 AMD_IP_BLOCK_TYPE_SDMA)) 286 continue; 287 r = adev->ip_blocks[i].version->funcs->resume(adev); 288 if (r) { 289 dev_err(adev->dev, 290 "resume of IP block <%s> failed %d\n", 291 adev->ip_blocks[i].version->funcs->name, r); 292 return r; 293 } 294 295 adev->ip_blocks[i].status.hw = true; 296 } 297 298 for (i = 0; i < adev->num_ip_blocks; i++) { 299 if (!(adev->ip_blocks[i].version->type == 300 AMD_IP_BLOCK_TYPE_GFX || 301 adev->ip_blocks[i].version->type == 302 AMD_IP_BLOCK_TYPE_SDMA || 303 adev->ip_blocks[i].version->type == 304 AMD_IP_BLOCK_TYPE_COMMON)) 305 continue; 306 307 if (adev->ip_blocks[i].version->funcs->late_init) { 308 r = adev->ip_blocks[i].version->funcs->late_init( 309 (void *)adev); 310 if (r) { 311 dev_err(adev->dev, 312 "late_init of IP block <%s> failed %d after reset\n", 313 adev->ip_blocks[i].version->funcs->name, 314 r); 315 return r; 316 } 317 } 318 adev->ip_blocks[i].status.late_initialized = true; 319 } 320 321 amdgpu_ras_set_error_query_ready(adev, true); 322 323 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); 324 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); 325 326 return r; 327 } 328 329 static int 330 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 331 struct amdgpu_reset_context *reset_context) 332 { 333 struct list_head *reset_device_list = reset_context->reset_device_list; 334 struct amdgpu_device *tmp_adev = NULL; 335 int r; 336 337 if (reset_device_list == NULL) 338 return -EINVAL; 339 340 if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] == 341 IP_VERSION(13, 0, 2) && 342 reset_context->hive == NULL) { 343 /* Wrong context, return error */ 344 return -EINVAL; 345 } 346 347 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 348 dev_info(tmp_adev->dev, 349 "GPU reset succeeded, trying to resume\n"); 350 r = aldebaran_mode2_restore_ip(tmp_adev); 351 if (r) 352 goto end; 353 354 /* 355 * Add this ASIC as tracked as reset was already 356 * complete successfully. 357 */ 358 amdgpu_register_gpu_instance(tmp_adev); 359 360 /* Resume RAS */ 361 amdgpu_ras_resume(tmp_adev); 362 363 /* Update PSP FW topology after reset */ 364 if (reset_context->hive && 365 tmp_adev->gmc.xgmi.num_physical_nodes > 1) 366 r = amdgpu_xgmi_update_topology(reset_context->hive, 367 tmp_adev); 368 369 if (!r) { 370 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); 371 372 r = amdgpu_ib_ring_tests(tmp_adev); 373 if (r) { 374 dev_err(tmp_adev->dev, 375 "ib ring test failed (%d).\n", r); 376 r = -EAGAIN; 377 tmp_adev->asic_reset_res = r; 378 goto end; 379 } 380 } 381 } 382 383 end: 384 return r; 385 } 386 387 static struct amdgpu_reset_handler aldebaran_mode2_handler = { 388 .reset_method = AMD_RESET_METHOD_MODE2, 389 .prepare_env = NULL, 390 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext, 391 .perform_reset = aldebaran_mode2_perform_reset, 392 .restore_hwcontext = aldebaran_mode2_restore_hwcontext, 393 .restore_env = NULL, 394 .do_reset = aldebaran_mode2_reset, 395 }; 396 397 static struct amdgpu_reset_handler 398 *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = { 399 &aldebaran_mode2_handler, 400 }; 401 402 int aldebaran_reset_init(struct amdgpu_device *adev) 403 { 404 struct amdgpu_reset_control *reset_ctl; 405 406 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL); 407 if (!reset_ctl) 408 return -ENOMEM; 409 410 reset_ctl->handle = adev; 411 reset_ctl->async_reset = aldebaran_async_reset; 412 reset_ctl->active_reset = AMD_RESET_METHOD_NONE; 413 reset_ctl->get_reset_handler = aldebaran_get_reset_handler; 414 415 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); 416 /* Only mode2 is handled through reset control now */ 417 reset_ctl->reset_handlers = &aldebaran_rst_handlers; 418 419 adev->reset_cntl = reset_ctl; 420 421 return 0; 422 } 423 424 int aldebaran_reset_fini(struct amdgpu_device *adev) 425 { 426 kfree(adev->reset_cntl); 427 adev->reset_cntl = NULL; 428 return 0; 429 } 430