1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "aldebaran.h" 25 #include "amdgpu_reset.h" 26 #include "amdgpu_amdkfd.h" 27 #include "amdgpu_dpm.h" 28 #include "amdgpu_job.h" 29 #include "amdgpu_ring.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_xgmi.h" 33 34 static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl) 35 { 36 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 37 38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 39 adev->gmc.xgmi.connected_to_cpu)) 40 return true; 41 42 return false; 43 } 44 45 static struct amdgpu_reset_handler * 46 aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, 47 struct amdgpu_reset_context *reset_context) 48 { 49 struct amdgpu_reset_handler *handler; 50 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 51 int i; 52 53 if (reset_context->method == AMD_RESET_METHOD_NONE) { 54 if (aldebaran_is_mode2_default(reset_ctl)) 55 reset_context->method = AMD_RESET_METHOD_MODE2; 56 else 57 reset_context->method = amdgpu_asic_reset_method(adev); 58 } 59 60 if (reset_context->method != AMD_RESET_METHOD_NONE) { 61 dev_dbg(adev->dev, "Getting reset handler for method %d\n", 62 reset_context->method); 63 for_each_handler(i, handler, reset_ctl) { 64 if (handler->reset_method == reset_context->method) 65 return handler; 66 } 67 } 68 69 dev_dbg(adev->dev, "Reset handler not found!\n"); 70 71 return NULL; 72 } 73 74 static inline uint32_t aldebaran_get_ip_block_mask(struct amdgpu_device *adev) 75 { 76 uint32_t ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GFX) | 77 BIT(AMD_IP_BLOCK_TYPE_SDMA); 78 79 if (adev->aid_mask) 80 ip_block_mask |= BIT(AMD_IP_BLOCK_TYPE_IH); 81 82 return ip_block_mask; 83 } 84 85 static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) 86 { 87 uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev); 88 uint32_t ip_block; 89 int r, i; 90 91 /* Skip suspend of SDMA IP versions >= 4.4.2. They are multi-aid */ 92 if (adev->aid_mask) 93 ip_block_mask &= ~BIT(AMD_IP_BLOCK_TYPE_SDMA); 94 95 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); 96 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); 97 98 for (i = adev->num_ip_blocks - 1; i >= 0; i--) { 99 ip_block = BIT(adev->ip_blocks[i].version->type); 100 if (!(ip_block_mask & ip_block)) 101 continue; 102 103 r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]); 104 if (r) 105 return r; 106 } 107 108 return 0; 109 } 110 111 static int 112 aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl, 113 struct amdgpu_reset_context *reset_context) 114 { 115 int r = 0; 116 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 117 118 dev_dbg(adev->dev, "Aldebaran prepare hw context\n"); 119 /* Don't suspend on bare metal if we are not going to HW reset the ASIC */ 120 if (!amdgpu_sriov_vf(adev)) 121 r = aldebaran_mode2_suspend_ip(adev); 122 123 return r; 124 } 125 126 static void aldebaran_async_reset(struct work_struct *work) 127 { 128 struct amdgpu_reset_handler *handler; 129 struct amdgpu_reset_control *reset_ctl = 130 container_of(work, struct amdgpu_reset_control, reset_work); 131 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 132 int i; 133 134 for_each_handler(i, handler, reset_ctl) { 135 if (handler->reset_method == reset_ctl->active_reset) { 136 dev_dbg(adev->dev, "Resetting device\n"); 137 handler->do_reset(adev); 138 break; 139 } 140 } 141 } 142 143 static int aldebaran_mode2_reset(struct amdgpu_device *adev) 144 { 145 /* disable BM */ 146 pci_clear_master(adev->pdev); 147 adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev); 148 return adev->asic_reset_res; 149 } 150 151 static int 152 aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 153 struct amdgpu_reset_context *reset_context) 154 { 155 struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; 156 struct list_head *reset_device_list = reset_context->reset_device_list; 157 struct amdgpu_device *tmp_adev = NULL; 158 int r = 0; 159 160 dev_dbg(adev->dev, "aldebaran perform hw reset\n"); 161 162 if (reset_device_list == NULL) 163 return -EINVAL; 164 165 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && 166 reset_context->hive == NULL) { 167 /* Wrong context, return error */ 168 return -EINVAL; 169 } 170 171 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 172 mutex_lock(&tmp_adev->reset_cntl->reset_lock); 173 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2; 174 } 175 /* 176 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch 177 * them together so that they can be completed asynchronously on multiple nodes 178 */ 179 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 180 /* For XGMI run all resets in parallel to speed up the process */ 181 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 182 if (!queue_work(system_unbound_wq, 183 &tmp_adev->reset_cntl->reset_work)) 184 r = -EALREADY; 185 } else 186 r = aldebaran_mode2_reset(tmp_adev); 187 if (r) { 188 dev_err(tmp_adev->dev, 189 "ASIC reset failed with error, %d for drm dev, %s", 190 r, adev_to_drm(tmp_adev)->unique); 191 break; 192 } 193 } 194 195 /* For XGMI wait for all resets to complete before proceed */ 196 if (!r) { 197 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 198 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { 199 flush_work(&tmp_adev->reset_cntl->reset_work); 200 r = tmp_adev->asic_reset_res; 201 if (r) 202 break; 203 } 204 } 205 } 206 207 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 208 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); 209 tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; 210 } 211 212 return r; 213 } 214 215 static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) 216 { 217 struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM]; 218 uint32_t ip_block_mask = aldebaran_get_ip_block_mask(adev); 219 struct amdgpu_firmware_info *ucode; 220 struct amdgpu_ip_block *cmn_block; 221 struct amdgpu_ip_block *ih_block; 222 int ucode_count = 0; 223 int i, r; 224 225 dev_dbg(adev->dev, "Reloading ucodes after reset\n"); 226 for (i = 0; i < adev->firmware.max_ucodes; i++) { 227 ucode = &adev->firmware.ucode[i]; 228 if (!ucode->fw) 229 continue; 230 switch (ucode->ucode_id) { 231 case AMDGPU_UCODE_ID_SDMA0: 232 case AMDGPU_UCODE_ID_SDMA1: 233 case AMDGPU_UCODE_ID_SDMA2: 234 case AMDGPU_UCODE_ID_SDMA3: 235 case AMDGPU_UCODE_ID_SDMA4: 236 case AMDGPU_UCODE_ID_SDMA5: 237 case AMDGPU_UCODE_ID_SDMA6: 238 case AMDGPU_UCODE_ID_SDMA7: 239 case AMDGPU_UCODE_ID_CP_MEC1: 240 case AMDGPU_UCODE_ID_CP_MEC1_JT: 241 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 242 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 243 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 244 case AMDGPU_UCODE_ID_RLC_G: 245 ucode_list[ucode_count++] = ucode; 246 break; 247 default: 248 break; 249 } 250 } 251 252 /* Reinit NBIF block */ 253 cmn_block = 254 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON); 255 if (unlikely(!cmn_block)) { 256 dev_err(adev->dev, "Failed to get BIF handle\n"); 257 return -EINVAL; 258 } 259 r = amdgpu_ip_block_resume(cmn_block); 260 if (r) 261 return r; 262 263 if (ip_block_mask & BIT(AMD_IP_BLOCK_TYPE_IH)) { 264 ih_block = amdgpu_device_ip_get_ip_block(adev, 265 AMD_IP_BLOCK_TYPE_IH); 266 if (unlikely(!ih_block)) { 267 dev_err(adev->dev, "Failed to get IH handle\n"); 268 return -EINVAL; 269 } 270 r = amdgpu_ip_block_resume(ih_block); 271 if (r) 272 return r; 273 } 274 275 /* Reinit GFXHUB */ 276 adev->gfxhub.funcs->init(adev); 277 r = adev->gfxhub.funcs->gart_enable(adev); 278 if (r) { 279 dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n"); 280 return r; 281 } 282 283 /* Reload GFX firmware */ 284 r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count); 285 if (r) { 286 dev_err(adev->dev, "GFX ucode load failed after reset\n"); 287 return r; 288 } 289 290 /* Resume RLC, FW needs RLC alive to complete reset process */ 291 adev->gfx.rlc.funcs->resume(adev); 292 293 /* Wait for FW reset event complete */ 294 r = amdgpu_dpm_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0); 295 if (r) { 296 dev_err(adev->dev, 297 "Failed to get response from firmware after reset\n"); 298 return r; 299 } 300 301 for (i = 0; i < adev->num_ip_blocks; i++) { 302 if (!(adev->ip_blocks[i].version->type == 303 AMD_IP_BLOCK_TYPE_GFX || 304 adev->ip_blocks[i].version->type == 305 AMD_IP_BLOCK_TYPE_SDMA)) 306 continue; 307 308 r = amdgpu_ip_block_resume(&adev->ip_blocks[i]); 309 if (r) 310 return r; 311 } 312 313 for (i = 0; i < adev->num_ip_blocks; i++) { 314 if (!(adev->ip_blocks[i].version->type == 315 AMD_IP_BLOCK_TYPE_GFX || 316 adev->ip_blocks[i].version->type == 317 AMD_IP_BLOCK_TYPE_SDMA || 318 adev->ip_blocks[i].version->type == 319 AMD_IP_BLOCK_TYPE_COMMON)) 320 continue; 321 322 if (adev->ip_blocks[i].version->funcs->late_init) { 323 r = adev->ip_blocks[i].version->funcs->late_init( 324 &adev->ip_blocks[i]); 325 if (r) { 326 dev_err(adev->dev, 327 "late_init of IP block <%s> failed %d after reset\n", 328 adev->ip_blocks[i].version->funcs->name, 329 r); 330 return r; 331 } 332 } 333 adev->ip_blocks[i].status.late_initialized = true; 334 } 335 336 amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE); 337 amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE); 338 339 return r; 340 } 341 342 static int 343 aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, 344 struct amdgpu_reset_context *reset_context) 345 { 346 struct list_head *reset_device_list = reset_context->reset_device_list; 347 struct amdgpu_device *tmp_adev = NULL; 348 struct amdgpu_ras *con; 349 int r; 350 351 if (reset_device_list == NULL) 352 return -EINVAL; 353 354 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) == 355 IP_VERSION(13, 0, 2) && 356 reset_context->hive == NULL) { 357 /* Wrong context, return error */ 358 return -EINVAL; 359 } 360 361 list_for_each_entry(tmp_adev, reset_device_list, reset_list) { 362 amdgpu_set_init_level(tmp_adev, 363 AMDGPU_INIT_LEVEL_RESET_RECOVERY); 364 dev_info(tmp_adev->dev, 365 "GPU reset succeeded, trying to resume\n"); 366 /*TBD: Ideally should clear only GFX, SDMA blocks*/ 367 amdgpu_ras_clear_err_state(tmp_adev); 368 r = aldebaran_mode2_restore_ip(tmp_adev); 369 if (r) 370 goto end; 371 372 /* 373 * Add this ASIC as tracked as reset was already 374 * complete successfully. 375 */ 376 amdgpu_register_gpu_instance(tmp_adev); 377 378 /* Resume RAS, ecc_irq */ 379 con = amdgpu_ras_get_context(tmp_adev); 380 if (!amdgpu_sriov_vf(tmp_adev) && con) { 381 if (tmp_adev->sdma.ras && 382 tmp_adev->sdma.ras->ras_block.ras_late_init) { 383 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, 384 &tmp_adev->sdma.ras->ras_block.ras_comm); 385 if (r) { 386 dev_err(tmp_adev->dev, "SDMA failed to execute ras_late_init! ret:%d\n", r); 387 goto end; 388 } 389 } 390 391 if (tmp_adev->gfx.ras && 392 tmp_adev->gfx.ras->ras_block.ras_late_init) { 393 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, 394 &tmp_adev->gfx.ras->ras_block.ras_comm); 395 if (r) { 396 dev_err(tmp_adev->dev, "GFX failed to execute ras_late_init! ret:%d\n", r); 397 goto end; 398 } 399 } 400 } 401 402 amdgpu_ras_resume(tmp_adev); 403 404 /* Update PSP FW topology after reset */ 405 if (reset_context->hive && 406 tmp_adev->gmc.xgmi.num_physical_nodes > 1) 407 r = amdgpu_xgmi_update_topology(reset_context->hive, 408 tmp_adev); 409 410 if (!r) { 411 amdgpu_set_init_level(tmp_adev, 412 AMDGPU_INIT_LEVEL_DEFAULT); 413 amdgpu_irq_gpu_reset_resume_helper(tmp_adev); 414 415 r = amdgpu_ib_ring_tests(tmp_adev); 416 if (r) { 417 dev_err(tmp_adev->dev, 418 "ib ring test failed (%d).\n", r); 419 r = -EAGAIN; 420 tmp_adev->asic_reset_res = r; 421 goto end; 422 } 423 } 424 } 425 426 end: 427 return r; 428 } 429 430 static struct amdgpu_reset_handler aldebaran_mode2_handler = { 431 .reset_method = AMD_RESET_METHOD_MODE2, 432 .prepare_env = NULL, 433 .prepare_hwcontext = aldebaran_mode2_prepare_hwcontext, 434 .perform_reset = aldebaran_mode2_perform_reset, 435 .restore_hwcontext = aldebaran_mode2_restore_hwcontext, 436 .restore_env = NULL, 437 .do_reset = aldebaran_mode2_reset, 438 }; 439 440 static struct amdgpu_reset_handler 441 *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = { 442 &aldebaran_mode2_handler, 443 &xgmi_reset_on_init_handler, 444 }; 445 446 int aldebaran_reset_init(struct amdgpu_device *adev) 447 { 448 struct amdgpu_reset_control *reset_ctl; 449 450 reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL); 451 if (!reset_ctl) 452 return -ENOMEM; 453 454 reset_ctl->handle = adev; 455 reset_ctl->async_reset = aldebaran_async_reset; 456 reset_ctl->active_reset = AMD_RESET_METHOD_NONE; 457 reset_ctl->get_reset_handler = aldebaran_get_reset_handler; 458 459 INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset); 460 /* Only mode2 is handled through reset control now */ 461 reset_ctl->reset_handlers = &aldebaran_rst_handlers; 462 463 adev->reset_cntl = reset_ctl; 464 465 return 0; 466 } 467 468 int aldebaran_reset_fini(struct amdgpu_device *adev) 469 { 470 kfree(adev->reset_cntl); 471 adev->reset_cntl = NULL; 472 return 0; 473 } 474