1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx Zynq GPIO device driver 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/spinlock.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/of.h> 19 20 #define DRIVER_NAME "zynq-gpio" 21 22 /* Maximum banks */ 23 #define ZYNQ_GPIO_MAX_BANK 4 24 #define ZYNQMP_GPIO_MAX_BANK 6 25 #define VERSAL_GPIO_MAX_BANK 4 26 #define PMC_GPIO_MAX_BANK 5 27 #define VERSAL_UNUSED_BANKS 2 28 29 #define ZYNQ_GPIO_BANK0_NGPIO 32 30 #define ZYNQ_GPIO_BANK1_NGPIO 22 31 #define ZYNQ_GPIO_BANK2_NGPIO 32 32 #define ZYNQ_GPIO_BANK3_NGPIO 32 33 34 #define ZYNQMP_GPIO_BANK0_NGPIO 26 35 #define ZYNQMP_GPIO_BANK1_NGPIO 26 36 #define ZYNQMP_GPIO_BANK2_NGPIO 26 37 #define ZYNQMP_GPIO_BANK3_NGPIO 32 38 #define ZYNQMP_GPIO_BANK4_NGPIO 32 39 #define ZYNQMP_GPIO_BANK5_NGPIO 32 40 41 #define ZYNQ_GPIO_NR_GPIOS 118 42 #define ZYNQMP_GPIO_NR_GPIOS 174 43 44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 45 #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 47 #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) 48 #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 50 #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) 51 #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 53 #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) 54 #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 56 #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) 57 #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 59 #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) 60 #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) 62 63 /* Register offsets for the GPIO device */ 64 /* LSW Mask & Data -WO */ 65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) 66 /* MSW Mask & Data -WO */ 67 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) 68 /* Data Register-RW */ 69 #define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK)) 70 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) 71 /* Direction mode reg-RW */ 72 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) 73 /* Output enable reg-RW */ 74 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) 75 /* Interrupt mask reg-RO */ 76 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) 77 /* Interrupt enable reg-WO */ 78 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) 79 /* Interrupt disable reg-WO */ 80 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) 81 /* Interrupt status reg-RO */ 82 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) 83 /* Interrupt type reg-RW */ 84 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) 85 /* Interrupt polarity reg-RW */ 86 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) 87 /* Interrupt on any, reg-RW */ 88 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) 89 90 /* Disable all interrupts mask */ 91 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF 92 93 /* Mid pin number of a bank */ 94 #define ZYNQ_GPIO_MID_PIN_NUM 16 95 96 /* GPIO upper 16 bit mask */ 97 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 98 99 /* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */ 100 #define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0) 101 #define GPIO_QUIRK_DATA_RO_BUG BIT(1) 102 #define GPIO_QUIRK_VERSAL BIT(2) 103 104 struct gpio_regs { 105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK]; 106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK]; 107 u32 dirm[ZYNQMP_GPIO_MAX_BANK]; 108 u32 outen[ZYNQMP_GPIO_MAX_BANK]; 109 u32 int_en[ZYNQMP_GPIO_MAX_BANK]; 110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK]; 111 u32 int_type[ZYNQMP_GPIO_MAX_BANK]; 112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK]; 113 u32 int_any[ZYNQMP_GPIO_MAX_BANK]; 114 }; 115 116 /** 117 * struct zynq_gpio - gpio device private data structure 118 * @chip: instance of the gpio_chip 119 * @base_addr: base address of the GPIO device 120 * @clk: clock resource for this controller 121 * @irq: interrupt for the GPIO device 122 * @p_data: pointer to platform data 123 * @context: context registers 124 * @dirlock: lock used for direction in/out synchronization 125 */ 126 struct zynq_gpio { 127 struct gpio_chip chip; 128 void __iomem *base_addr; 129 struct clk *clk; 130 int irq; 131 const struct zynq_platform_data *p_data; 132 struct gpio_regs context; 133 spinlock_t dirlock; /* lock */ 134 }; 135 136 /** 137 * struct zynq_platform_data - zynq gpio platform data structure 138 * @label: string to store in gpio->label 139 * @quirks: Flags is used to identify the platform 140 * @ngpio: max number of gpio pins 141 * @max_bank: maximum number of gpio banks 142 * @bank_min: this array represents bank's min pin 143 * @bank_max: this array represents bank's max pin 144 */ 145 struct zynq_platform_data { 146 const char *label; 147 u32 quirks; 148 u16 ngpio; 149 int max_bank; 150 int bank_min[ZYNQMP_GPIO_MAX_BANK]; 151 int bank_max[ZYNQMP_GPIO_MAX_BANK]; 152 }; 153 154 static const struct irq_chip zynq_gpio_level_irqchip; 155 static const struct irq_chip zynq_gpio_edge_irqchip; 156 157 /** 158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp 159 * @gpio: Pointer to driver data struct 160 * 161 * Return: 0 if zynqmp, 1 if zynq. 162 */ 163 static int zynq_gpio_is_zynq(struct zynq_gpio *gpio) 164 { 165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ); 166 } 167 168 /** 169 * gpio_data_ro_bug - test if HW bug exists or not 170 * @gpio: Pointer to driver data struct 171 * 172 * Return: 0 if bug doesnot exist, 1 if bug exists. 173 */ 174 static int gpio_data_ro_bug(struct zynq_gpio *gpio) 175 { 176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG); 177 } 178 179 /** 180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank 181 * for a given pin in the GPIO device 182 * @pin_num: gpio pin number within the device 183 * @bank_num: an output parameter used to return the bank number of the gpio 184 * pin 185 * @bank_pin_num: an output parameter used to return pin number within a bank 186 * for the given gpio pin 187 * @gpio: gpio device data structure 188 * 189 * Returns the bank number and pin offset within the bank. 190 */ 191 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, 192 unsigned int *bank_num, 193 unsigned int *bank_pin_num, 194 struct zynq_gpio *gpio) 195 { 196 int bank; 197 198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) { 199 if ((pin_num >= gpio->p_data->bank_min[bank]) && 200 (pin_num <= gpio->p_data->bank_max[bank])) { 201 *bank_num = bank; 202 *bank_pin_num = pin_num - 203 gpio->p_data->bank_min[bank]; 204 return; 205 } 206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) 207 bank = bank + VERSAL_UNUSED_BANKS; 208 } 209 210 /* default */ 211 WARN(true, "invalid GPIO pin number: %u", pin_num); 212 *bank_num = 0; 213 *bank_pin_num = 0; 214 } 215 216 /** 217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device 218 * @chip: gpio_chip instance to be worked on 219 * @pin: gpio pin number within the device 220 * 221 * This function reads the state of the specified pin of the GPIO device. 222 * 223 * Return: 0 if the pin is low, 1 if pin is high. 224 */ 225 static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin) 226 { 227 u32 data; 228 unsigned int bank_num, bank_pin_num; 229 struct zynq_gpio *gpio = gpiochip_get_data(chip); 230 231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 232 233 if (gpio_data_ro_bug(gpio)) { 234 if (zynq_gpio_is_zynq(gpio)) { 235 if (bank_num <= 1) { 236 data = readl_relaxed(gpio->base_addr + 237 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 238 } else { 239 data = readl_relaxed(gpio->base_addr + 240 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 241 } 242 } else { 243 if (bank_num <= 2) { 244 data = readl_relaxed(gpio->base_addr + 245 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 246 } else { 247 data = readl_relaxed(gpio->base_addr + 248 ZYNQ_GPIO_DATA_OFFSET(bank_num)); 249 } 250 } 251 } else { 252 data = readl_relaxed(gpio->base_addr + 253 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); 254 } 255 return (data >> bank_pin_num) & 1; 256 } 257 258 /** 259 * zynq_gpio_set_value - Modify the state of the pin with specified value 260 * @chip: gpio_chip instance to be worked on 261 * @pin: gpio pin number within the device 262 * @state: value used to modify the state of the specified pin 263 * 264 * This function calculates the register offset (i.e to lower 16 bits or 265 * upper 16 bits) based on the given pin number and sets the state of a 266 * gpio pin to the specified value. The state is either 0 or non-zero. 267 */ 268 static int zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, 269 int state) 270 { 271 unsigned int reg_offset, bank_num, bank_pin_num; 272 struct zynq_gpio *gpio = gpiochip_get_data(chip); 273 274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 275 276 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { 277 /* only 16 data bits in bit maskable reg */ 278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; 279 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); 280 } else { 281 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); 282 } 283 284 /* 285 * get the 32 bit value to be written to the mask/data register where 286 * the upper 16 bits is the mask and lower 16 bits is the data 287 */ 288 state = !!state; 289 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & 290 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); 291 292 writel_relaxed(state, gpio->base_addr + reg_offset); 293 294 return 0; 295 } 296 297 /** 298 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input 299 * @chip: gpio_chip instance to be worked on 300 * @pin: gpio pin number within the device 301 * 302 * This function uses the read-modify-write sequence to set the direction of 303 * the gpio pin as input. 304 * 305 * Return: 0 always 306 */ 307 static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) 308 { 309 u32 reg; 310 unsigned int bank_num, bank_pin_num; 311 unsigned long flags; 312 struct zynq_gpio *gpio = gpiochip_get_data(chip); 313 314 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 315 316 /* 317 * On zynq bank 0 pins 7 and 8 are special and cannot be used 318 * as inputs. 319 */ 320 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 && 321 (bank_pin_num == 7 || bank_pin_num == 8)) 322 return -EINVAL; 323 324 /* clear the bit in direction mode reg to set the pin as input */ 325 spin_lock_irqsave(&gpio->dirlock, flags); 326 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 327 reg &= ~BIT(bank_pin_num); 328 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 329 spin_unlock_irqrestore(&gpio->dirlock, flags); 330 331 return 0; 332 } 333 334 /** 335 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output 336 * @chip: gpio_chip instance to be worked on 337 * @pin: gpio pin number within the device 338 * @state: value to be written to specified pin 339 * 340 * This function sets the direction of specified GPIO pin as output, configures 341 * the Output Enable register for the pin and uses zynq_gpio_set to set 342 * the state of the pin to the value specified. 343 * 344 * Return: 0 always 345 */ 346 static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, 347 int state) 348 { 349 u32 reg; 350 unsigned int bank_num, bank_pin_num; 351 unsigned long flags; 352 struct zynq_gpio *gpio = gpiochip_get_data(chip); 353 354 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 355 356 /* set the GPIO pin as output */ 357 spin_lock_irqsave(&gpio->dirlock, flags); 358 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 359 reg |= BIT(bank_pin_num); 360 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 361 362 /* configure the output enable reg for the pin */ 363 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 364 reg |= BIT(bank_pin_num); 365 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); 366 spin_unlock_irqrestore(&gpio->dirlock, flags); 367 368 /* set the state of the pin */ 369 zynq_gpio_set_value(chip, pin, state); 370 return 0; 371 } 372 373 /** 374 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin 375 * @chip: gpio_chip instance to be worked on 376 * @pin: gpio pin number within the device 377 * 378 * This function returns the direction of the specified GPIO. 379 * 380 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN 381 */ 382 static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 383 { 384 u32 reg; 385 unsigned int bank_num, bank_pin_num; 386 struct zynq_gpio *gpio = gpiochip_get_data(chip); 387 388 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); 389 390 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 391 392 if (reg & BIT(bank_pin_num)) 393 return GPIO_LINE_DIRECTION_OUT; 394 395 return GPIO_LINE_DIRECTION_IN; 396 } 397 398 /** 399 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin 400 * @irq_data: per irq and chip data passed down to chip functions 401 * 402 * This function calculates gpio pin number from irq number and sets the 403 * bit in the Interrupt Disable register of the corresponding bank to disable 404 * interrupts for that pin. 405 */ 406 static void zynq_gpio_irq_mask(struct irq_data *irq_data) 407 { 408 unsigned int device_pin_num, bank_num, bank_pin_num; 409 const unsigned long offset = irqd_to_hwirq(irq_data); 410 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data); 411 struct zynq_gpio *gpio = 412 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 413 414 gpiochip_disable_irq(chip, offset); 415 device_pin_num = irq_data->hwirq; 416 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 417 writel_relaxed(BIT(bank_pin_num), 418 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 419 } 420 421 /** 422 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin 423 * @irq_data: irq data containing irq number of gpio pin for the interrupt 424 * to enable 425 * 426 * This function calculates the gpio pin number from irq number and sets the 427 * bit in the Interrupt Enable register of the corresponding bank to enable 428 * interrupts for that pin. 429 */ 430 static void zynq_gpio_irq_unmask(struct irq_data *irq_data) 431 { 432 unsigned int device_pin_num, bank_num, bank_pin_num; 433 const unsigned long offset = irqd_to_hwirq(irq_data); 434 struct gpio_chip *chip = irq_data_get_irq_chip_data(irq_data); 435 struct zynq_gpio *gpio = 436 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 437 438 gpiochip_enable_irq(chip, offset); 439 device_pin_num = irq_data->hwirq; 440 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 441 writel_relaxed(BIT(bank_pin_num), 442 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 443 } 444 445 /** 446 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin 447 * @irq_data: irq data containing irq number of gpio pin for the interrupt 448 * to ack 449 * 450 * This function calculates gpio pin number from irq number and sets the bit 451 * in the Interrupt Status Register of the corresponding bank, to ACK the irq. 452 */ 453 static void zynq_gpio_irq_ack(struct irq_data *irq_data) 454 { 455 unsigned int device_pin_num, bank_num, bank_pin_num; 456 struct zynq_gpio *gpio = 457 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 458 459 device_pin_num = irq_data->hwirq; 460 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 461 writel_relaxed(BIT(bank_pin_num), 462 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 463 } 464 465 /** 466 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin 467 * @irq_data: irq data containing irq number of gpio pin for the interrupt 468 * to enable 469 * 470 * Clears the INTSTS bit and unmasks the given interrupt. 471 */ 472 static void zynq_gpio_irq_enable(struct irq_data *irq_data) 473 { 474 /* 475 * The Zynq GPIO controller does not disable interrupt detection when 476 * the interrupt is masked and only disables the propagation of the 477 * interrupt. This means when the controller detects an interrupt 478 * condition while the interrupt is logically disabled it will propagate 479 * that interrupt event once the interrupt is enabled. This will cause 480 * the interrupt consumer to see spurious interrupts to prevent this 481 * first make sure that the interrupt is not asserted and then enable 482 * it. 483 */ 484 zynq_gpio_irq_ack(irq_data); 485 zynq_gpio_irq_unmask(irq_data); 486 } 487 488 /** 489 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin 490 * @irq_data: irq data containing irq number of gpio pin 491 * @type: interrupt type that is to be set for the gpio pin 492 * 493 * This function gets the gpio pin number and its bank from the gpio pin number 494 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers. 495 * 496 * Return: 0, negative error otherwise. 497 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0; 498 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0; 499 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1; 500 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA; 501 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA 502 */ 503 static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 504 { 505 u32 int_type, int_pol, int_any; 506 unsigned int device_pin_num, bank_num, bank_pin_num; 507 struct zynq_gpio *gpio = 508 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data)); 509 510 device_pin_num = irq_data->hwirq; 511 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio); 512 513 int_type = readl_relaxed(gpio->base_addr + 514 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 515 int_pol = readl_relaxed(gpio->base_addr + 516 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 517 int_any = readl_relaxed(gpio->base_addr + 518 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 519 520 /* 521 * based on the type requested, configure the INT_TYPE, INT_POLARITY 522 * and INT_ANY registers 523 */ 524 switch (type) { 525 case IRQ_TYPE_EDGE_RISING: 526 int_type |= BIT(bank_pin_num); 527 int_pol |= BIT(bank_pin_num); 528 int_any &= ~BIT(bank_pin_num); 529 break; 530 case IRQ_TYPE_EDGE_FALLING: 531 int_type |= BIT(bank_pin_num); 532 int_pol &= ~BIT(bank_pin_num); 533 int_any &= ~BIT(bank_pin_num); 534 break; 535 case IRQ_TYPE_EDGE_BOTH: 536 int_type |= BIT(bank_pin_num); 537 int_any |= BIT(bank_pin_num); 538 break; 539 case IRQ_TYPE_LEVEL_HIGH: 540 int_type &= ~BIT(bank_pin_num); 541 int_pol |= BIT(bank_pin_num); 542 break; 543 case IRQ_TYPE_LEVEL_LOW: 544 int_type &= ~BIT(bank_pin_num); 545 int_pol &= ~BIT(bank_pin_num); 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 writel_relaxed(int_type, 552 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 553 writel_relaxed(int_pol, 554 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 555 writel_relaxed(int_any, 556 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 557 558 if (type & IRQ_TYPE_LEVEL_MASK) 559 irq_set_chip_handler_name_locked(irq_data, 560 &zynq_gpio_level_irqchip, 561 handle_fasteoi_irq, NULL); 562 else 563 irq_set_chip_handler_name_locked(irq_data, 564 &zynq_gpio_edge_irqchip, 565 handle_level_irq, NULL); 566 567 return 0; 568 } 569 570 static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on) 571 { 572 struct zynq_gpio *gpio = 573 gpiochip_get_data(irq_data_get_irq_chip_data(data)); 574 575 irq_set_irq_wake(gpio->irq, on); 576 577 return 0; 578 } 579 580 static int zynq_gpio_irq_reqres(struct irq_data *d) 581 { 582 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 583 int ret; 584 585 ret = pm_runtime_resume_and_get(chip->parent); 586 if (ret < 0) 587 return ret; 588 589 return gpiochip_reqres_irq(chip, d->hwirq); 590 } 591 592 static void zynq_gpio_irq_relres(struct irq_data *d) 593 { 594 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 595 596 gpiochip_relres_irq(chip, d->hwirq); 597 pm_runtime_put(chip->parent); 598 } 599 600 /* irq chip descriptor */ 601 static const struct irq_chip zynq_gpio_level_irqchip = { 602 .name = DRIVER_NAME, 603 .irq_enable = zynq_gpio_irq_enable, 604 .irq_eoi = zynq_gpio_irq_ack, 605 .irq_mask = zynq_gpio_irq_mask, 606 .irq_unmask = zynq_gpio_irq_unmask, 607 .irq_set_type = zynq_gpio_set_irq_type, 608 .irq_set_wake = zynq_gpio_set_wake, 609 .irq_request_resources = zynq_gpio_irq_reqres, 610 .irq_release_resources = zynq_gpio_irq_relres, 611 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | 612 IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 613 }; 614 615 static const struct irq_chip zynq_gpio_edge_irqchip = { 616 .name = DRIVER_NAME, 617 .irq_enable = zynq_gpio_irq_enable, 618 .irq_ack = zynq_gpio_irq_ack, 619 .irq_mask = zynq_gpio_irq_mask, 620 .irq_unmask = zynq_gpio_irq_unmask, 621 .irq_set_type = zynq_gpio_set_irq_type, 622 .irq_set_wake = zynq_gpio_set_wake, 623 .irq_request_resources = zynq_gpio_irq_reqres, 624 .irq_release_resources = zynq_gpio_irq_relres, 625 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 626 }; 627 628 static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio, 629 unsigned int bank_num, 630 unsigned long pending) 631 { 632 unsigned int bank_offset = gpio->p_data->bank_min[bank_num]; 633 struct irq_domain *irqdomain = gpio->chip.irq.domain; 634 int offset; 635 636 if (!pending) 637 return; 638 639 for_each_set_bit(offset, &pending, 32) 640 generic_handle_domain_irq(irqdomain, offset + bank_offset); 641 } 642 643 /** 644 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device 645 * @desc: irq descriptor instance of the 'irq' 646 * 647 * This function reads the Interrupt Status Register of each bank to get the 648 * gpio pin number which has triggered an interrupt. It then acks the triggered 649 * interrupt and calls the pin specific handler set by the higher layer 650 * application for that pin. 651 * Note: A bug is reported if no handler is set for the gpio pin. 652 */ 653 static void zynq_gpio_irqhandler(struct irq_desc *desc) 654 { 655 u32 int_sts, int_enb; 656 unsigned int bank_num; 657 struct zynq_gpio *gpio = 658 gpiochip_get_data(irq_desc_get_handler_data(desc)); 659 struct irq_chip *irqchip = irq_desc_get_chip(desc); 660 661 chained_irq_enter(irqchip, desc); 662 663 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 664 int_sts = readl_relaxed(gpio->base_addr + 665 ZYNQ_GPIO_INTSTS_OFFSET(bank_num)); 666 int_enb = readl_relaxed(gpio->base_addr + 667 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 668 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb); 669 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) 670 bank_num = bank_num + VERSAL_UNUSED_BANKS; 671 } 672 673 chained_irq_exit(irqchip, desc); 674 } 675 676 static void zynq_gpio_save_context(struct zynq_gpio *gpio) 677 { 678 unsigned int bank_num; 679 680 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 681 gpio->context.datalsw[bank_num] = 682 readl_relaxed(gpio->base_addr + 683 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 684 gpio->context.datamsw[bank_num] = 685 readl_relaxed(gpio->base_addr + 686 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 687 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr + 688 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 689 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr + 690 ZYNQ_GPIO_INTMASK_OFFSET(bank_num)); 691 gpio->context.int_type[bank_num] = 692 readl_relaxed(gpio->base_addr + 693 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 694 gpio->context.int_polarity[bank_num] = 695 readl_relaxed(gpio->base_addr + 696 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 697 gpio->context.int_any[bank_num] = 698 readl_relaxed(gpio->base_addr + 699 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 700 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) 701 bank_num = bank_num + VERSAL_UNUSED_BANKS; 702 } 703 } 704 705 static void zynq_gpio_restore_context(struct zynq_gpio *gpio) 706 { 707 unsigned int bank_num; 708 709 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 710 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 711 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 712 writel_relaxed(gpio->context.datalsw[bank_num], 713 gpio->base_addr + 714 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num)); 715 writel_relaxed(gpio->context.datamsw[bank_num], 716 gpio->base_addr + 717 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num)); 718 writel_relaxed(gpio->context.dirm[bank_num], 719 gpio->base_addr + 720 ZYNQ_GPIO_DIRM_OFFSET(bank_num)); 721 writel_relaxed(gpio->context.int_type[bank_num], 722 gpio->base_addr + 723 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num)); 724 writel_relaxed(gpio->context.int_polarity[bank_num], 725 gpio->base_addr + 726 ZYNQ_GPIO_INTPOL_OFFSET(bank_num)); 727 writel_relaxed(gpio->context.int_any[bank_num], 728 gpio->base_addr + 729 ZYNQ_GPIO_INTANY_OFFSET(bank_num)); 730 writel_relaxed(~(gpio->context.int_en[bank_num]), 731 gpio->base_addr + 732 ZYNQ_GPIO_INTEN_OFFSET(bank_num)); 733 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) 734 bank_num = bank_num + VERSAL_UNUSED_BANKS; 735 } 736 } 737 738 static int __maybe_unused zynq_gpio_suspend(struct device *dev) 739 { 740 struct zynq_gpio *gpio = dev_get_drvdata(dev); 741 struct irq_data *data = irq_get_irq_data(gpio->irq); 742 743 if (!data) { 744 dev_err(dev, "irq_get_irq_data() failed\n"); 745 return -EINVAL; 746 } 747 748 if (!device_may_wakeup(dev)) 749 disable_irq(gpio->irq); 750 751 if (!irqd_is_wakeup_set(data)) { 752 zynq_gpio_save_context(gpio); 753 return pm_runtime_force_suspend(dev); 754 } 755 756 return 0; 757 } 758 759 static int __maybe_unused zynq_gpio_resume(struct device *dev) 760 { 761 struct zynq_gpio *gpio = dev_get_drvdata(dev); 762 struct irq_data *data = irq_get_irq_data(gpio->irq); 763 int ret; 764 765 if (!data) { 766 dev_err(dev, "irq_get_irq_data() failed\n"); 767 return -EINVAL; 768 } 769 770 if (!device_may_wakeup(dev)) 771 enable_irq(gpio->irq); 772 773 if (!irqd_is_wakeup_set(data)) { 774 ret = pm_runtime_force_resume(dev); 775 zynq_gpio_restore_context(gpio); 776 return ret; 777 } 778 779 return 0; 780 } 781 782 static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev) 783 { 784 struct zynq_gpio *gpio = dev_get_drvdata(dev); 785 786 clk_disable_unprepare(gpio->clk); 787 788 return 0; 789 } 790 791 static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev) 792 { 793 struct zynq_gpio *gpio = dev_get_drvdata(dev); 794 795 return clk_prepare_enable(gpio->clk); 796 } 797 798 static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset) 799 { 800 int ret; 801 802 ret = pm_runtime_get_sync(chip->parent); 803 804 /* 805 * If the device is already active pm_runtime_get() will return 1 on 806 * success, but gpio_request still needs to return 0. 807 */ 808 return ret < 0 ? ret : 0; 809 } 810 811 static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset) 812 { 813 pm_runtime_put(chip->parent); 814 } 815 816 static const struct dev_pm_ops zynq_gpio_dev_pm_ops = { 817 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume) 818 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend, 819 zynq_gpio_runtime_resume, NULL) 820 }; 821 822 static const struct zynq_platform_data versal_gpio_def = { 823 .label = "versal_gpio", 824 .quirks = GPIO_QUIRK_VERSAL, 825 .ngpio = 58, 826 .max_bank = VERSAL_GPIO_MAX_BANK, 827 .bank_min[0] = 0, 828 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ 829 .bank_min[3] = 26, 830 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */ 831 }; 832 833 static const struct zynq_platform_data pmc_gpio_def = { 834 .label = "pmc_gpio", 835 .ngpio = 116, 836 .max_bank = PMC_GPIO_MAX_BANK, 837 .bank_min[0] = 0, 838 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */ 839 .bank_min[1] = 26, 840 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */ 841 .bank_min[3] = 52, 842 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */ 843 .bank_min[4] = 84, 844 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */ 845 }; 846 847 static const struct zynq_platform_data zynqmp_gpio_def = { 848 .label = "zynqmp_gpio", 849 .quirks = GPIO_QUIRK_DATA_RO_BUG, 850 .ngpio = ZYNQMP_GPIO_NR_GPIOS, 851 .max_bank = ZYNQMP_GPIO_MAX_BANK, 852 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), 853 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), 854 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), 855 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), 856 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), 857 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), 858 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), 859 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), 860 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), 861 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), 862 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), 863 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), 864 }; 865 866 static const struct zynq_platform_data zynq_gpio_def = { 867 .label = "zynq_gpio", 868 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG, 869 .ngpio = ZYNQ_GPIO_NR_GPIOS, 870 .max_bank = ZYNQ_GPIO_MAX_BANK, 871 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), 872 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), 873 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), 874 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), 875 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), 876 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), 877 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), 878 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), 879 }; 880 881 static const struct of_device_id zynq_gpio_of_match[] = { 882 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def }, 883 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def }, 884 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def }, 885 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def }, 886 { /* end of table */ } 887 }; 888 MODULE_DEVICE_TABLE(of, zynq_gpio_of_match); 889 890 /** 891 * zynq_gpio_probe - Initialization method for a zynq_gpio device 892 * @pdev: platform device instance 893 * 894 * This function allocates memory resources for the gpio device and registers 895 * all the banks of the device. It will also set up interrupts for the gpio 896 * pins. 897 * Note: Interrupts are disabled for all the banks during initialization. 898 * 899 * Return: 0 on success, negative error otherwise. 900 */ 901 static int zynq_gpio_probe(struct platform_device *pdev) 902 { 903 int ret, bank_num; 904 struct zynq_gpio *gpio; 905 struct gpio_chip *chip; 906 struct gpio_irq_chip *girq; 907 const struct of_device_id *match; 908 909 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 910 if (!gpio) 911 return -ENOMEM; 912 913 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node); 914 if (!match) { 915 dev_err(&pdev->dev, "of_match_node() failed\n"); 916 return -EINVAL; 917 } 918 gpio->p_data = match->data; 919 platform_set_drvdata(pdev, gpio); 920 921 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0); 922 if (IS_ERR(gpio->base_addr)) 923 return PTR_ERR(gpio->base_addr); 924 925 gpio->irq = platform_get_irq(pdev, 0); 926 if (gpio->irq < 0) 927 return gpio->irq; 928 929 /* configure the gpio chip */ 930 chip = &gpio->chip; 931 chip->label = gpio->p_data->label; 932 chip->owner = THIS_MODULE; 933 chip->parent = &pdev->dev; 934 chip->get = zynq_gpio_get_value; 935 chip->set = zynq_gpio_set_value; 936 chip->request = zynq_gpio_request; 937 chip->free = zynq_gpio_free; 938 chip->direction_input = zynq_gpio_dir_in; 939 chip->direction_output = zynq_gpio_dir_out; 940 chip->get_direction = zynq_gpio_get_direction; 941 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio"); 942 chip->ngpio = gpio->p_data->ngpio; 943 944 /* Retrieve GPIO clock */ 945 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); 946 if (IS_ERR(gpio->clk)) 947 return dev_err_probe(&pdev->dev, PTR_ERR(gpio->clk), "input clock not found.\n"); 948 949 spin_lock_init(&gpio->dirlock); 950 951 pm_runtime_set_active(&pdev->dev); 952 pm_runtime_enable(&pdev->dev); 953 ret = pm_runtime_resume_and_get(&pdev->dev); 954 if (ret < 0) 955 goto err_pm_dis; 956 957 /* disable interrupts for all banks */ 958 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) { 959 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr + 960 ZYNQ_GPIO_INTDIS_OFFSET(bank_num)); 961 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL) 962 bank_num = bank_num + VERSAL_UNUSED_BANKS; 963 } 964 965 /* Set up the GPIO irqchip */ 966 girq = &chip->irq; 967 gpio_irq_chip_set_chip(girq, &zynq_gpio_edge_irqchip); 968 girq->parent_handler = zynq_gpio_irqhandler; 969 girq->num_parents = 1; 970 girq->parents = devm_kcalloc(&pdev->dev, 1, 971 sizeof(*girq->parents), 972 GFP_KERNEL); 973 if (!girq->parents) { 974 ret = -ENOMEM; 975 goto err_pm_put; 976 } 977 girq->parents[0] = gpio->irq; 978 girq->default_type = IRQ_TYPE_NONE; 979 girq->handler = handle_level_irq; 980 981 /* report a bug if gpio chip registration fails */ 982 ret = gpiochip_add_data(chip, gpio); 983 if (ret) { 984 dev_err(&pdev->dev, "Failed to add gpio chip\n"); 985 goto err_pm_put; 986 } 987 988 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY); 989 device_init_wakeup(&pdev->dev, 1); 990 pm_runtime_put(&pdev->dev); 991 992 return 0; 993 994 err_pm_put: 995 pm_runtime_put(&pdev->dev); 996 err_pm_dis: 997 pm_runtime_disable(&pdev->dev); 998 999 return ret; 1000 } 1001 1002 /** 1003 * zynq_gpio_remove - Driver removal function 1004 * @pdev: platform device instance 1005 * 1006 * Return: 0 always 1007 */ 1008 static void zynq_gpio_remove(struct platform_device *pdev) 1009 { 1010 struct zynq_gpio *gpio = platform_get_drvdata(pdev); 1011 int ret; 1012 1013 ret = pm_runtime_get_sync(&pdev->dev); 1014 if (ret < 0) 1015 dev_warn(&pdev->dev, "pm_runtime_get_sync() Failed\n"); 1016 device_init_wakeup(&pdev->dev, 0); 1017 gpiochip_remove(&gpio->chip); 1018 device_set_wakeup_capable(&pdev->dev, 0); 1019 pm_runtime_disable(&pdev->dev); 1020 } 1021 1022 static struct platform_driver zynq_gpio_driver = { 1023 .driver = { 1024 .name = DRIVER_NAME, 1025 .pm = &zynq_gpio_dev_pm_ops, 1026 .of_match_table = zynq_gpio_of_match, 1027 }, 1028 .probe = zynq_gpio_probe, 1029 .remove = zynq_gpio_remove, 1030 }; 1031 1032 module_platform_driver(zynq_gpio_driver); 1033 1034 MODULE_AUTHOR("Xilinx Inc."); 1035 MODULE_DESCRIPTION("Zynq GPIO driver"); 1036 MODULE_LICENSE("GPL"); 1037