1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO controller in LSI ZEVIO SoCs. 4 * 5 * Author: Fabian Vogt <fabian@ritter-vogt.de> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/errno.h> 10 #include <linux/init.h> 11 #include <linux/io.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/platform_device.h> 14 #include <linux/property.h> 15 #include <linux/slab.h> 16 #include <linux/spinlock.h> 17 18 #include <linux/gpio/driver.h> 19 20 /* 21 * Memory layout: 22 * This chip has four gpio sections, each controls 8 GPIOs. 23 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10. 24 * Disclaimer: Reverse engineered! 25 * For more information refer to: 26 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29 27 * 28 * 0x00-0x3F: Section 0 29 * +0x00: Masked interrupt status (read-only) 30 * +0x04: R: Interrupt status W: Reset interrupt status 31 * +0x08: R: Interrupt mask W: Mask interrupt 32 * +0x0C: W: Unmask interrupt (write-only) 33 * +0x10: Direction: I/O=1/0 34 * +0x14: Output 35 * +0x18: Input (read-only) 36 * +0x20: R: Level interrupt W: Set as level interrupt 37 * 0x40-0x7F: Section 1 38 * 0x80-0xBF: Section 2 39 * 0xC0-0xFF: Section 3 40 */ 41 42 #define ZEVIO_GPIO_SECTION_SIZE 0x40 43 44 /* Offsets to various registers */ 45 #define ZEVIO_GPIO_INT_MASKED_STATUS 0x00 46 #define ZEVIO_GPIO_INT_STATUS 0x04 47 #define ZEVIO_GPIO_INT_UNMASK 0x08 48 #define ZEVIO_GPIO_INT_MASK 0x0C 49 #define ZEVIO_GPIO_DIRECTION 0x10 50 #define ZEVIO_GPIO_OUTPUT 0x14 51 #define ZEVIO_GPIO_INPUT 0x18 52 #define ZEVIO_GPIO_INT_STICKY 0x20 53 54 /* Bit number of GPIO in its section */ 55 #define ZEVIO_GPIO_BIT(gpio) (gpio&7) 56 57 struct zevio_gpio { 58 struct gpio_chip chip; 59 spinlock_t lock; 60 void __iomem *regs; 61 }; 62 63 static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, 64 unsigned port_offset) 65 { 66 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; 67 return readl(IOMEM(c->regs + section_offset + port_offset)); 68 } 69 70 static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, 71 unsigned port_offset, u32 val) 72 { 73 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; 74 writel(val, IOMEM(c->regs + section_offset + port_offset)); 75 } 76 77 /* Functions for struct gpio_chip */ 78 static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) 79 { 80 struct zevio_gpio *controller = gpiochip_get_data(chip); 81 u32 val, dir; 82 83 spin_lock(&controller->lock); 84 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 85 if (dir & BIT(ZEVIO_GPIO_BIT(pin))) 86 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); 87 else 88 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 89 spin_unlock(&controller->lock); 90 91 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; 92 } 93 94 static int zevio_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 95 { 96 struct zevio_gpio *controller = gpiochip_get_data(chip); 97 u32 val; 98 99 spin_lock(&controller->lock); 100 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 101 if (value) 102 val |= BIT(ZEVIO_GPIO_BIT(pin)); 103 else 104 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 105 106 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); 107 spin_unlock(&controller->lock); 108 109 return 0; 110 } 111 112 static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 113 { 114 struct zevio_gpio *controller = gpiochip_get_data(chip); 115 u32 val; 116 117 spin_lock(&controller->lock); 118 119 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 120 val |= BIT(ZEVIO_GPIO_BIT(pin)); 121 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); 122 123 spin_unlock(&controller->lock); 124 125 return 0; 126 } 127 128 static int zevio_gpio_direction_output(struct gpio_chip *chip, 129 unsigned pin, int value) 130 { 131 struct zevio_gpio *controller = gpiochip_get_data(chip); 132 u32 val; 133 134 spin_lock(&controller->lock); 135 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); 136 if (value) 137 val |= BIT(ZEVIO_GPIO_BIT(pin)); 138 else 139 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 140 141 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); 142 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); 143 val &= ~BIT(ZEVIO_GPIO_BIT(pin)); 144 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); 145 146 spin_unlock(&controller->lock); 147 148 return 0; 149 } 150 151 static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 152 { 153 /* 154 * TODO: Implement IRQs. 155 * Not implemented yet due to weird lockups 156 */ 157 158 return -ENXIO; 159 } 160 161 static const struct gpio_chip zevio_gpio_chip = { 162 .direction_input = zevio_gpio_direction_input, 163 .direction_output = zevio_gpio_direction_output, 164 .set = zevio_gpio_set, 165 .get = zevio_gpio_get, 166 .to_irq = zevio_gpio_to_irq, 167 .base = 0, 168 .owner = THIS_MODULE, 169 .ngpio = 32, 170 }; 171 172 /* Initialization */ 173 static int zevio_gpio_probe(struct platform_device *pdev) 174 { 175 struct device *dev = &pdev->dev; 176 struct zevio_gpio *controller; 177 int status, i; 178 179 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL); 180 if (!controller) 181 return -ENOMEM; 182 183 /* Copy our reference */ 184 controller->chip = zevio_gpio_chip; 185 controller->chip.parent = &pdev->dev; 186 187 controller->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev)); 188 if (!controller->chip.label) 189 return -ENOMEM; 190 191 controller->regs = devm_platform_ioremap_resource(pdev, 0); 192 if (IS_ERR(controller->regs)) 193 return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs), 194 "failed to ioremap memory resource\n"); 195 196 status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller); 197 if (status) { 198 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status); 199 return status; 200 } 201 202 spin_lock_init(&controller->lock); 203 204 /* Disable interrupts, they only cause errors */ 205 for (i = 0; i < controller->chip.ngpio; i += 8) 206 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF); 207 208 dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n"); 209 210 return 0; 211 } 212 213 static const struct of_device_id zevio_gpio_of_match[] = { 214 { .compatible = "lsi,zevio-gpio", }, 215 { }, 216 }; 217 218 static struct platform_driver zevio_gpio_driver = { 219 .driver = { 220 .name = "gpio-zevio", 221 .of_match_table = zevio_gpio_of_match, 222 .suppress_bind_attrs = true, 223 }, 224 .probe = zevio_gpio_probe, 225 }; 226 builtin_platform_driver(zevio_gpio_driver); 227