1130a990bSLinus Walleij // SPDX-License-Identifier: GPL-2.0 2ff718800SKamlakant Patel /* 3ff718800SKamlakant Patel * Copyright (C) 2003-2015 Broadcom Corporation 4ff718800SKamlakant Patel * All Rights Reserved 5ff718800SKamlakant Patel */ 6ff718800SKamlakant Patel 7121111d7SLinus Walleij #include <linux/gpio/driver.h> 8ff718800SKamlakant Patel #include <linux/platform_device.h> 9ff718800SKamlakant Patel #include <linux/module.h> 10ff718800SKamlakant Patel #include <linux/irq.h> 11ff718800SKamlakant Patel #include <linux/interrupt.h> 1283ea24fdSKamlakant Patel #include <linux/irqchip/chained_irq.h> 13baa1b920SKamlakant Patel #include <linux/acpi.h> 14ff718800SKamlakant Patel 15ff718800SKamlakant Patel /* 16ff718800SKamlakant Patel * XLP GPIO has multiple 32 bit registers for each feature where each register 17ff718800SKamlakant Patel * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 18ff718800SKamlakant Patel * require 3 32-bit registers for each feature. 19ff718800SKamlakant Patel * Here we only define offset of the first register for each feature. Offset of 20ff718800SKamlakant Patel * the registers for pins greater than 32 can be calculated as following(Use 21ff718800SKamlakant Patel * GPIO_INT_STAT as example): 22ff718800SKamlakant Patel * 23ff718800SKamlakant Patel * offset = (gpio / XLP_GPIO_REGSZ) * 4; 24ff718800SKamlakant Patel * reg_addr = addr + offset; 25ff718800SKamlakant Patel * 26ff718800SKamlakant Patel * where addr is base address of the that feature register and gpio is the pin. 27ff718800SKamlakant Patel */ 28ff718800SKamlakant Patel #define GPIO_9XX_BYTESWAP 0X00 29ff718800SKamlakant Patel #define GPIO_9XX_CTRL 0X04 30ff718800SKamlakant Patel #define GPIO_9XX_OUTPUT_EN 0x14 31ff718800SKamlakant Patel #define GPIO_9XX_PADDRV 0x24 32ff718800SKamlakant Patel /* 33ff718800SKamlakant Patel * Only for 4 interrupt enable reg are defined for now, 34ff718800SKamlakant Patel * total reg available are 12. 35ff718800SKamlakant Patel */ 36ff718800SKamlakant Patel #define GPIO_9XX_INT_EN00 0x44 37ff718800SKamlakant Patel #define GPIO_9XX_INT_EN10 0x54 38ff718800SKamlakant Patel #define GPIO_9XX_INT_EN20 0x64 39ff718800SKamlakant Patel #define GPIO_9XX_INT_EN30 0x74 40ff718800SKamlakant Patel #define GPIO_9XX_INT_POL 0x104 41ff718800SKamlakant Patel #define GPIO_9XX_INT_TYPE 0x114 42ff718800SKamlakant Patel #define GPIO_9XX_INT_STAT 0x124 43ff718800SKamlakant Patel 44ff718800SKamlakant Patel /* Interrupt type register mask */ 45ff718800SKamlakant Patel #define XLP_GPIO_IRQ_TYPE_LVL 0x0 46ff718800SKamlakant Patel #define XLP_GPIO_IRQ_TYPE_EDGE 0x1 47ff718800SKamlakant Patel 48ff718800SKamlakant Patel /* Interrupt polarity register mask */ 49ff718800SKamlakant Patel #define XLP_GPIO_IRQ_POL_HIGH 0x0 50ff718800SKamlakant Patel #define XLP_GPIO_IRQ_POL_LOW 0x1 51ff718800SKamlakant Patel 52ff718800SKamlakant Patel #define XLP_GPIO_REGSZ 32 53ff718800SKamlakant Patel #define XLP_GPIO_IRQ_BASE 768 54ff718800SKamlakant Patel #define XLP_MAX_NR_GPIO 96 55ff718800SKamlakant Patel 56ff718800SKamlakant Patel struct xlp_gpio_priv { 57ff718800SKamlakant Patel struct gpio_chip chip; 58ff718800SKamlakant Patel DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); 59ff718800SKamlakant Patel void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ 60ff718800SKamlakant Patel void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ 61ff718800SKamlakant Patel void __iomem *gpio_intr_type; /* pointer to first intr type reg */ 62ff718800SKamlakant Patel void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ 63ff718800SKamlakant Patel void __iomem *gpio_out_en; /* pointer to first output enable reg */ 64ff718800SKamlakant Patel void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ 65ff718800SKamlakant Patel spinlock_t lock; 66ff718800SKamlakant Patel }; 67ff718800SKamlakant Patel 68ff718800SKamlakant Patel static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) 69ff718800SKamlakant Patel { 70ff718800SKamlakant Patel u32 pos, regset; 71ff718800SKamlakant Patel 72ff718800SKamlakant Patel pos = gpio % XLP_GPIO_REGSZ; 73ff718800SKamlakant Patel regset = (gpio / XLP_GPIO_REGSZ) * 4; 74ff718800SKamlakant Patel return !!(readl(addr + regset) & BIT(pos)); 75ff718800SKamlakant Patel } 76ff718800SKamlakant Patel 77ff718800SKamlakant Patel static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) 78ff718800SKamlakant Patel { 79ff718800SKamlakant Patel u32 value, pos, regset; 80ff718800SKamlakant Patel 81ff718800SKamlakant Patel pos = gpio % XLP_GPIO_REGSZ; 82ff718800SKamlakant Patel regset = (gpio / XLP_GPIO_REGSZ) * 4; 83ff718800SKamlakant Patel value = readl(addr + regset); 84ff718800SKamlakant Patel 85ff718800SKamlakant Patel if (state) 86ff718800SKamlakant Patel value |= BIT(pos); 87ff718800SKamlakant Patel else 88ff718800SKamlakant Patel value &= ~BIT(pos); 89ff718800SKamlakant Patel 90ff718800SKamlakant Patel writel(value, addr + regset); 91ff718800SKamlakant Patel } 92ff718800SKamlakant Patel 93*2093bcd8SLinus Walleij static void xlp_gpio_irq_enable(struct irq_data *d) 94*2093bcd8SLinus Walleij { 95*2093bcd8SLinus Walleij struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 96*2093bcd8SLinus Walleij 97*2093bcd8SLinus Walleij gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 98*2093bcd8SLinus Walleij } 99*2093bcd8SLinus Walleij 100ff718800SKamlakant Patel static void xlp_gpio_irq_disable(struct irq_data *d) 101ff718800SKamlakant Patel { 102ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 103e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 104ff718800SKamlakant Patel unsigned long flags; 105ff718800SKamlakant Patel 106ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 107ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 108ff718800SKamlakant Patel __clear_bit(d->hwirq, priv->gpio_enabled_mask); 109ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 110*2093bcd8SLinus Walleij gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 111ff718800SKamlakant Patel } 112ff718800SKamlakant Patel 113ff718800SKamlakant Patel static void xlp_gpio_irq_mask_ack(struct irq_data *d) 114ff718800SKamlakant Patel { 115ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 116e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 117ff718800SKamlakant Patel unsigned long flags; 118ff718800SKamlakant Patel 119ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 120ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); 121ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); 122ff718800SKamlakant Patel __clear_bit(d->hwirq, priv->gpio_enabled_mask); 123ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 124ff718800SKamlakant Patel } 125ff718800SKamlakant Patel 126ff718800SKamlakant Patel static void xlp_gpio_irq_unmask(struct irq_data *d) 127ff718800SKamlakant Patel { 128ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 129e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 130ff718800SKamlakant Patel unsigned long flags; 131ff718800SKamlakant Patel 132ff718800SKamlakant Patel spin_lock_irqsave(&priv->lock, flags); 133ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); 134ff718800SKamlakant Patel __set_bit(d->hwirq, priv->gpio_enabled_mask); 135ff718800SKamlakant Patel spin_unlock_irqrestore(&priv->lock, flags); 136ff718800SKamlakant Patel } 137ff718800SKamlakant Patel 138ff718800SKamlakant Patel static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) 139ff718800SKamlakant Patel { 140ff718800SKamlakant Patel struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 141e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 142ff718800SKamlakant Patel int pol, irq_type; 143ff718800SKamlakant Patel 144ff718800SKamlakant Patel switch (type) { 145ff718800SKamlakant Patel case IRQ_TYPE_EDGE_RISING: 146ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 147ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_HIGH; 148ff718800SKamlakant Patel break; 149ff718800SKamlakant Patel case IRQ_TYPE_EDGE_FALLING: 150ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_EDGE; 151ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_LOW; 152ff718800SKamlakant Patel break; 153ff718800SKamlakant Patel case IRQ_TYPE_LEVEL_HIGH: 154ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_LVL; 155ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_HIGH; 156ff718800SKamlakant Patel break; 157ff718800SKamlakant Patel case IRQ_TYPE_LEVEL_LOW: 158ff718800SKamlakant Patel irq_type = XLP_GPIO_IRQ_TYPE_LVL; 159ff718800SKamlakant Patel pol = XLP_GPIO_IRQ_POL_LOW; 160ff718800SKamlakant Patel break; 161ff718800SKamlakant Patel default: 162ff718800SKamlakant Patel return -EINVAL; 163ff718800SKamlakant Patel } 164ff718800SKamlakant Patel 165ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); 166ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); 167ff718800SKamlakant Patel 168ff718800SKamlakant Patel return 0; 169ff718800SKamlakant Patel } 170ff718800SKamlakant Patel 171ff718800SKamlakant Patel static struct irq_chip xlp_gpio_irq_chip = { 172ff718800SKamlakant Patel .name = "XLP-GPIO", 173ff718800SKamlakant Patel .irq_mask_ack = xlp_gpio_irq_mask_ack, 174*2093bcd8SLinus Walleij .irq_enable = xlp_gpio_irq_enable, 175ff718800SKamlakant Patel .irq_disable = xlp_gpio_irq_disable, 176ff718800SKamlakant Patel .irq_set_type = xlp_gpio_set_irq_type, 177ff718800SKamlakant Patel .irq_unmask = xlp_gpio_irq_unmask, 178*2093bcd8SLinus Walleij .flags = IRQCHIP_ONESHOT_SAFE | IRQCHIP_IMMUTABLE, 179*2093bcd8SLinus Walleij GPIOCHIP_IRQ_RESOURCE_HELPERS, 180ff718800SKamlakant Patel }; 181ff718800SKamlakant Patel 18283ea24fdSKamlakant Patel static void xlp_gpio_generic_handler(struct irq_desc *desc) 183ff718800SKamlakant Patel { 18483ea24fdSKamlakant Patel struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); 18583ea24fdSKamlakant Patel struct irq_chip *irqchip = irq_desc_get_chip(desc); 186ff718800SKamlakant Patel int gpio, regoff; 187ff718800SKamlakant Patel u32 gpio_stat; 188ff718800SKamlakant Patel 189ff718800SKamlakant Patel regoff = -1; 190ff718800SKamlakant Patel gpio_stat = 0; 19183ea24fdSKamlakant Patel 19283ea24fdSKamlakant Patel chained_irq_enter(irqchip, desc); 193ff718800SKamlakant Patel for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { 194ff718800SKamlakant Patel if (regoff != gpio / XLP_GPIO_REGSZ) { 195ff718800SKamlakant Patel regoff = gpio / XLP_GPIO_REGSZ; 196ff718800SKamlakant Patel gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); 197ff718800SKamlakant Patel } 19883ea24fdSKamlakant Patel 199ff718800SKamlakant Patel if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) 200dbd1c54fSMarc Zyngier generic_handle_domain_irq(priv->chip.irq.domain, gpio); 201ff718800SKamlakant Patel } 20283ea24fdSKamlakant Patel chained_irq_exit(irqchip, desc); 203ff718800SKamlakant Patel } 204ff718800SKamlakant Patel 205ff718800SKamlakant Patel static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) 206ff718800SKamlakant Patel { 207e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 208ff718800SKamlakant Patel 209ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 210ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); 211ff718800SKamlakant Patel 212ff718800SKamlakant Patel return 0; 213ff718800SKamlakant Patel } 214ff718800SKamlakant Patel 215ff718800SKamlakant Patel static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) 216ff718800SKamlakant Patel { 217e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 218ff718800SKamlakant Patel 219ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 220ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); 221ff718800SKamlakant Patel 222ff718800SKamlakant Patel return 0; 223ff718800SKamlakant Patel } 224ff718800SKamlakant Patel 225ff718800SKamlakant Patel static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) 226ff718800SKamlakant Patel { 227e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 228ff718800SKamlakant Patel 229ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 230ff718800SKamlakant Patel return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); 231ff718800SKamlakant Patel } 232ff718800SKamlakant Patel 233ff718800SKamlakant Patel static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) 234ff718800SKamlakant Patel { 235e730a595SLinus Walleij struct xlp_gpio_priv *priv = gpiochip_get_data(gc); 236ff718800SKamlakant Patel 237ff718800SKamlakant Patel BUG_ON(gpio >= gc->ngpio); 238ff718800SKamlakant Patel xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); 239ff718800SKamlakant Patel } 240ff718800SKamlakant Patel 241ff718800SKamlakant Patel static int xlp_gpio_probe(struct platform_device *pdev) 242ff718800SKamlakant Patel { 243ff718800SKamlakant Patel struct gpio_chip *gc; 244c7e66e48SLinus Walleij struct gpio_irq_chip *girq; 245ff718800SKamlakant Patel struct xlp_gpio_priv *priv; 246ff718800SKamlakant Patel void __iomem *gpio_base; 247ea708ac5SRob Herring int irq, err; 248ff718800SKamlakant Patel 249ff718800SKamlakant Patel priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 250ff718800SKamlakant Patel if (!priv) 251ff718800SKamlakant Patel return -ENOMEM; 252ff718800SKamlakant Patel 2533883de02SEnrico Weigelt, metux IT consult gpio_base = devm_platform_ioremap_resource(pdev, 0); 254ff718800SKamlakant Patel if (IS_ERR(gpio_base)) 255ff718800SKamlakant Patel return PTR_ERR(gpio_base); 256ff718800SKamlakant Patel 257ff718800SKamlakant Patel irq = platform_get_irq(pdev, 0); 258ff718800SKamlakant Patel if (irq < 0) 259ff718800SKamlakant Patel return irq; 260ff718800SKamlakant Patel 261ff718800SKamlakant Patel priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; 262ff718800SKamlakant Patel priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; 263ff718800SKamlakant Patel priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; 264ff718800SKamlakant Patel priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; 265ff718800SKamlakant Patel priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; 266ff718800SKamlakant Patel priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; 267ff718800SKamlakant Patel 268ff718800SKamlakant Patel bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); 269ff718800SKamlakant Patel 270ff718800SKamlakant Patel gc = &priv->chip; 271ff718800SKamlakant Patel 272b8a3f52eSAxel Lin gc->owner = THIS_MODULE; 273b8a3f52eSAxel Lin gc->label = dev_name(&pdev->dev); 274ff718800SKamlakant Patel gc->base = 0; 27558383c78SLinus Walleij gc->parent = &pdev->dev; 276ea708ac5SRob Herring gc->ngpio = 70; 277ff718800SKamlakant Patel gc->direction_output = xlp_gpio_dir_output; 278ff718800SKamlakant Patel gc->direction_input = xlp_gpio_dir_input; 279ff718800SKamlakant Patel gc->set = xlp_gpio_set; 280ff718800SKamlakant Patel gc->get = xlp_gpio_get; 281ff718800SKamlakant Patel 282ff718800SKamlakant Patel spin_lock_init(&priv->lock); 2831630a062SKamlakant Patel 284c7e66e48SLinus Walleij girq = &gc->irq; 285*2093bcd8SLinus Walleij gpio_irq_chip_set_chip(girq, &xlp_gpio_irq_chip); 286c7e66e48SLinus Walleij girq->parent_handler = xlp_gpio_generic_handler; 287c7e66e48SLinus Walleij girq->num_parents = 1; 288c7e66e48SLinus Walleij girq->parents = devm_kcalloc(&pdev->dev, 1, 289c7e66e48SLinus Walleij sizeof(*girq->parents), 290c7e66e48SLinus Walleij GFP_KERNEL); 291c7e66e48SLinus Walleij if (!girq->parents) 292c7e66e48SLinus Walleij return -ENOMEM; 293c7e66e48SLinus Walleij girq->parents[0] = irq; 294ea708ac5SRob Herring girq->first = 0; 295c7e66e48SLinus Walleij girq->default_type = IRQ_TYPE_NONE; 296c7e66e48SLinus Walleij girq->handler = handle_level_irq; 297c7e66e48SLinus Walleij 298e730a595SLinus Walleij err = gpiochip_add_data(gc, priv); 299ff718800SKamlakant Patel if (err < 0) 30031bd86d9SBartosz Golaszewski return err; 301ff718800SKamlakant Patel 302ff718800SKamlakant Patel dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); 303ff718800SKamlakant Patel 304ff718800SKamlakant Patel return 0; 305ff718800SKamlakant Patel } 306ff718800SKamlakant Patel 307baa1b920SKamlakant Patel #ifdef CONFIG_ACPI 308baa1b920SKamlakant Patel static const struct acpi_device_id xlp_gpio_acpi_match[] = { 309e320d9c2SRob Herring { "BRCM9006" }, 310e320d9c2SRob Herring { "CAV9006" }, 311baa1b920SKamlakant Patel {}, 312baa1b920SKamlakant Patel }; 313baa1b920SKamlakant Patel MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); 314baa1b920SKamlakant Patel #endif 315baa1b920SKamlakant Patel 316ff718800SKamlakant Patel static struct platform_driver xlp_gpio_driver = { 317ff718800SKamlakant Patel .driver = { 318ff718800SKamlakant Patel .name = "xlp-gpio", 319baa1b920SKamlakant Patel .acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match), 320ff718800SKamlakant Patel }, 321ff718800SKamlakant Patel .probe = xlp_gpio_probe, 322ff718800SKamlakant Patel }; 323ff718800SKamlakant Patel module_platform_driver(xlp_gpio_driver); 324ff718800SKamlakant Patel 325ff718800SKamlakant Patel MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>"); 326ff718800SKamlakant Patel MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>"); 327ff718800SKamlakant Patel MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); 328ff718800SKamlakant Patel MODULE_LICENSE("GPL v2"); 329