1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx gpio driver for xps/axi_gpio IP. 4 * 5 * Copyright 2008 - 2013 Xilinx, Inc. 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/errno.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 23 /* Register Offset Definitions */ 24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */ 25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ 26 27 #define XGPIO_CHANNEL0_OFFSET 0x0 28 #define XGPIO_CHANNEL1_OFFSET 0x8 29 30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ 31 #define XGPIO_GIER_IE BIT(31) 32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ 33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ 34 35 /* Read/Write access to the GPIO registers */ 36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) 37 # define xgpio_readreg(offset) readl(offset) 38 # define xgpio_writereg(offset, val) writel(val, offset) 39 #else 40 # define xgpio_readreg(offset) __raw_readl(offset) 41 # define xgpio_writereg(offset, val) __raw_writel(val, offset) 42 #endif 43 44 /** 45 * struct xgpio_instance - Stores information about GPIO device 46 * @gc: GPIO chip 47 * @regs: register block 48 * @map: GPIO pin mapping on hardware side 49 * @state: GPIO write state shadow register 50 * @last_irq_read: GPIO read state register from last interrupt 51 * @dir: GPIO direction shadow register 52 * @gpio_lock: Lock used for synchronization 53 * @irq: IRQ used by GPIO device 54 * @enable: GPIO IRQ enable/disable bitfield 55 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield 56 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield 57 * @clk: clock resource for this driver 58 */ 59 struct xgpio_instance { 60 struct gpio_chip gc; 61 void __iomem *regs; 62 DECLARE_BITMAP(map, 64); 63 DECLARE_BITMAP(state, 64); 64 DECLARE_BITMAP(last_irq_read, 64); 65 DECLARE_BITMAP(dir, 64); 66 raw_spinlock_t gpio_lock; /* For serializing operations */ 67 int irq; 68 DECLARE_BITMAP(enable, 64); 69 DECLARE_BITMAP(rising_edge, 64); 70 DECLARE_BITMAP(falling_edge, 64); 71 struct clk *clk; 72 }; 73 74 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) 75 { 76 switch (ch) { 77 case 0: 78 return XGPIO_CHANNEL0_OFFSET; 79 case 1: 80 return XGPIO_CHANNEL1_OFFSET; 81 default: 82 return -EINVAL; 83 } 84 } 85 86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 87 { 88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 89 unsigned long value = xgpio_readreg(addr); 90 91 bitmap_write(a, value, round_down(bit, 32), 32); 92 } 93 94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 95 { 96 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 97 unsigned long value = bitmap_read(a, round_down(bit, 32), 32); 98 99 xgpio_writereg(addr, value); 100 } 101 102 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 103 { 104 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 105 int bit; 106 107 for (bit = 0; bit <= lastbit ; bit += 32) 108 xgpio_read_ch(chip, reg, bit, a); 109 } 110 111 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 112 { 113 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 114 int bit; 115 116 for (bit = 0; bit <= lastbit ; bit += 32) 117 xgpio_write_ch(chip, reg, bit, a); 118 } 119 120 /** 121 * xgpio_get - Read the specified signal of the GPIO device. 122 * @gc: Pointer to gpio_chip device structure. 123 * @gpio: GPIO signal number. 124 * 125 * This function reads the specified signal of the GPIO device. 126 * 127 * Return: 128 * 0 if direction of GPIO signals is set as input otherwise it 129 * returns negative error value. 130 */ 131 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 132 { 133 struct xgpio_instance *chip = gpiochip_get_data(gc); 134 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 135 DECLARE_BITMAP(state, 64); 136 137 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); 138 139 return test_bit(bit, state); 140 } 141 142 /** 143 * xgpio_set - Write the specified signal of the GPIO device. 144 * @gc: Pointer to gpio_chip device structure. 145 * @gpio: GPIO signal number. 146 * @val: Value to be written to specified signal. 147 * 148 * This function writes the specified value in to the specified signal of the 149 * GPIO device. 150 */ 151 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 152 { 153 unsigned long flags; 154 struct xgpio_instance *chip = gpiochip_get_data(gc); 155 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 156 157 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 158 159 /* Write to GPIO signal and set its direction to output */ 160 __assign_bit(bit, chip->state, val); 161 162 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 163 164 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 165 } 166 167 /** 168 * xgpio_set_multiple - Write the specified signals of the GPIO device. 169 * @gc: Pointer to gpio_chip device structure. 170 * @mask: Mask of the GPIOS to modify. 171 * @bits: Value to be wrote on each GPIO 172 * 173 * This function writes the specified values into the specified signals of the 174 * GPIO devices. 175 */ 176 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 177 unsigned long *bits) 178 { 179 DECLARE_BITMAP(hw_mask, 64); 180 DECLARE_BITMAP(hw_bits, 64); 181 DECLARE_BITMAP(state, 64); 182 unsigned long flags; 183 struct xgpio_instance *chip = gpiochip_get_data(gc); 184 185 bitmap_scatter(hw_mask, mask, chip->map, 64); 186 bitmap_scatter(hw_bits, bits, chip->map, 64); 187 188 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 189 190 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); 191 192 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); 193 194 bitmap_copy(chip->state, state, 64); 195 196 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 197 } 198 199 /** 200 * xgpio_dir_in - Set the direction of the specified GPIO signal as input. 201 * @gc: Pointer to gpio_chip device structure. 202 * @gpio: GPIO signal number. 203 * 204 * Return: 205 * 0 - if direction of GPIO signals is set as input 206 * otherwise it returns negative error value. 207 */ 208 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 209 { 210 unsigned long flags; 211 struct xgpio_instance *chip = gpiochip_get_data(gc); 212 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 213 214 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 215 216 /* Set the GPIO bit in shadow register and set direction as input */ 217 __set_bit(bit, chip->dir); 218 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 219 220 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 221 222 return 0; 223 } 224 225 /** 226 * xgpio_dir_out - Set the direction of the specified GPIO signal as output. 227 * @gc: Pointer to gpio_chip device structure. 228 * @gpio: GPIO signal number. 229 * @val: Value to be written to specified signal. 230 * 231 * This function sets the direction of specified GPIO signal as output. 232 * 233 * Return: 234 * If all GPIO signals of GPIO chip is configured as input then it returns 235 * error otherwise it returns 0. 236 */ 237 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 238 { 239 unsigned long flags; 240 struct xgpio_instance *chip = gpiochip_get_data(gc); 241 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 242 243 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 244 245 /* Write state of GPIO signal */ 246 __assign_bit(bit, chip->state, val); 247 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 248 249 /* Clear the GPIO bit in shadow register and set direction as output */ 250 __clear_bit(bit, chip->dir); 251 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 252 253 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 254 255 return 0; 256 } 257 258 /** 259 * xgpio_save_regs - Set initial values of GPIO pins 260 * @chip: Pointer to GPIO instance 261 */ 262 static void xgpio_save_regs(struct xgpio_instance *chip) 263 { 264 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); 265 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); 266 } 267 268 static int xgpio_request(struct gpio_chip *chip, unsigned int offset) 269 { 270 int ret; 271 272 ret = pm_runtime_get_sync(chip->parent); 273 /* 274 * If the device is already active pm_runtime_get() will return 1 on 275 * success, but gpio_request still needs to return 0. 276 */ 277 return ret < 0 ? ret : 0; 278 } 279 280 static void xgpio_free(struct gpio_chip *chip, unsigned int offset) 281 { 282 pm_runtime_put(chip->parent); 283 } 284 285 static int __maybe_unused xgpio_suspend(struct device *dev) 286 { 287 struct xgpio_instance *gpio = dev_get_drvdata(dev); 288 struct irq_data *data = irq_get_irq_data(gpio->irq); 289 290 if (!data) { 291 dev_dbg(dev, "IRQ not connected\n"); 292 return pm_runtime_force_suspend(dev); 293 } 294 295 if (!irqd_is_wakeup_set(data)) 296 return pm_runtime_force_suspend(dev); 297 298 return 0; 299 } 300 301 /** 302 * xgpio_remove - Remove method for the GPIO device. 303 * @pdev: pointer to the platform device 304 * 305 * This function remove gpiochips and frees all the allocated resources. 306 * 307 * Return: 0 always 308 */ 309 static void xgpio_remove(struct platform_device *pdev) 310 { 311 pm_runtime_get_sync(&pdev->dev); 312 pm_runtime_put_noidle(&pdev->dev); 313 pm_runtime_disable(&pdev->dev); 314 } 315 316 /** 317 * xgpio_irq_ack - Acknowledge a child GPIO interrupt. 318 * @irq_data: per IRQ and chip data passed down to chip functions 319 * This currently does nothing, but irq_ack is unconditionally called by 320 * handle_edge_irq and therefore must be defined. 321 */ 322 static void xgpio_irq_ack(struct irq_data *irq_data) 323 { 324 } 325 326 static int __maybe_unused xgpio_resume(struct device *dev) 327 { 328 struct xgpio_instance *gpio = dev_get_drvdata(dev); 329 struct irq_data *data = irq_get_irq_data(gpio->irq); 330 331 if (!data) { 332 dev_dbg(dev, "IRQ not connected\n"); 333 return pm_runtime_force_resume(dev); 334 } 335 336 if (!irqd_is_wakeup_set(data)) 337 return pm_runtime_force_resume(dev); 338 339 return 0; 340 } 341 342 static int __maybe_unused xgpio_runtime_suspend(struct device *dev) 343 { 344 struct xgpio_instance *gpio = dev_get_drvdata(dev); 345 346 clk_disable(gpio->clk); 347 348 return 0; 349 } 350 351 static int __maybe_unused xgpio_runtime_resume(struct device *dev) 352 { 353 struct xgpio_instance *gpio = dev_get_drvdata(dev); 354 355 return clk_enable(gpio->clk); 356 } 357 358 static const struct dev_pm_ops xgpio_dev_pm_ops = { 359 SET_SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) 360 SET_RUNTIME_PM_OPS(xgpio_runtime_suspend, 361 xgpio_runtime_resume, NULL) 362 }; 363 364 /** 365 * xgpio_irq_mask - Write the specified signal of the GPIO device. 366 * @irq_data: per IRQ and chip data passed down to chip functions 367 */ 368 static void xgpio_irq_mask(struct irq_data *irq_data) 369 { 370 unsigned long flags; 371 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 372 int irq_offset = irqd_to_hwirq(irq_data); 373 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 374 u32 mask = BIT(bit / 32), temp; 375 376 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 377 378 __clear_bit(bit, chip->enable); 379 380 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 381 if (enable == 0) { 382 /* Disable per channel interrupt */ 383 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 384 temp &= ~mask; 385 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); 386 } 387 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 388 389 gpiochip_disable_irq(&chip->gc, irq_offset); 390 } 391 392 /** 393 * xgpio_irq_unmask - Write the specified signal of the GPIO device. 394 * @irq_data: per IRQ and chip data passed down to chip functions 395 */ 396 static void xgpio_irq_unmask(struct irq_data *irq_data) 397 { 398 unsigned long flags; 399 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 400 int irq_offset = irqd_to_hwirq(irq_data); 401 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 402 u32 mask = BIT(bit / 32), val; 403 404 gpiochip_enable_irq(&chip->gc, irq_offset); 405 406 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 407 408 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 409 if (enable == 0) { 410 /* Clear any existing per-channel interrupts */ 411 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 412 val &= mask; 413 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); 414 415 /* Update GPIO IRQ read data before enabling interrupt*/ 416 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); 417 418 /* Enable per channel interrupt */ 419 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 420 val |= mask; 421 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 422 } 423 424 __set_bit(bit, chip->enable); 425 426 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 427 } 428 429 /** 430 * xgpio_set_irq_type - Write the specified signal of the GPIO device. 431 * @irq_data: Per IRQ and chip data passed down to chip functions 432 * @type: Interrupt type that is to be set for the gpio pin 433 * 434 * Return: 435 * 0 if interrupt type is supported otherwise -EINVAL 436 */ 437 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 438 { 439 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 440 int irq_offset = irqd_to_hwirq(irq_data); 441 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset); 442 443 /* 444 * The Xilinx GPIO hardware provides a single interrupt status 445 * indication for any state change in a given GPIO channel (bank). 446 * Therefore, only rising edge or falling edge triggers are 447 * supported. 448 */ 449 switch (type & IRQ_TYPE_SENSE_MASK) { 450 case IRQ_TYPE_EDGE_BOTH: 451 __set_bit(bit, chip->rising_edge); 452 __set_bit(bit, chip->falling_edge); 453 break; 454 case IRQ_TYPE_EDGE_RISING: 455 __set_bit(bit, chip->rising_edge); 456 __clear_bit(bit, chip->falling_edge); 457 break; 458 case IRQ_TYPE_EDGE_FALLING: 459 __clear_bit(bit, chip->rising_edge); 460 __set_bit(bit, chip->falling_edge); 461 break; 462 default: 463 return -EINVAL; 464 } 465 466 irq_set_handler_locked(irq_data, handle_edge_irq); 467 return 0; 468 } 469 470 /** 471 * xgpio_irqhandler - Gpio interrupt service routine 472 * @desc: Pointer to interrupt description 473 */ 474 static void xgpio_irqhandler(struct irq_desc *desc) 475 { 476 struct xgpio_instance *chip = irq_desc_get_handler_data(desc); 477 struct gpio_chip *gc = &chip->gc; 478 struct irq_chip *irqchip = irq_desc_get_chip(desc); 479 DECLARE_BITMAP(rising, 64); 480 DECLARE_BITMAP(falling, 64); 481 DECLARE_BITMAP(hw, 64); 482 DECLARE_BITMAP(sw, 64); 483 int irq_offset; 484 u32 status; 485 486 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 487 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); 488 489 chained_irq_enter(irqchip, desc); 490 491 raw_spin_lock(&chip->gpio_lock); 492 493 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw); 494 495 bitmap_complement(rising, chip->last_irq_read, 64); 496 bitmap_and(rising, rising, hw, 64); 497 bitmap_and(rising, rising, chip->enable, 64); 498 bitmap_and(rising, rising, chip->rising_edge, 64); 499 500 bitmap_complement(falling, hw, 64); 501 bitmap_and(falling, falling, chip->last_irq_read, 64); 502 bitmap_and(falling, falling, chip->enable, 64); 503 bitmap_and(falling, falling, chip->falling_edge, 64); 504 505 bitmap_copy(chip->last_irq_read, hw, 64); 506 bitmap_or(hw, rising, falling, 64); 507 508 raw_spin_unlock(&chip->gpio_lock); 509 510 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); 511 512 bitmap_gather(sw, hw, chip->map, 64); 513 for_each_set_bit(irq_offset, sw, 64) 514 generic_handle_domain_irq(gc->irq.domain, irq_offset); 515 516 chained_irq_exit(irqchip, desc); 517 } 518 519 static const struct irq_chip xgpio_irq_chip = { 520 .name = "gpio-xilinx", 521 .irq_ack = xgpio_irq_ack, 522 .irq_mask = xgpio_irq_mask, 523 .irq_unmask = xgpio_irq_unmask, 524 .irq_set_type = xgpio_set_irq_type, 525 .flags = IRQCHIP_IMMUTABLE, 526 GPIOCHIP_IRQ_RESOURCE_HELPERS, 527 }; 528 529 /** 530 * xgpio_probe - Probe method for the GPIO device. 531 * @pdev: pointer to the platform device 532 * 533 * Return: 534 * It returns 0, if the driver is bound to the GPIO device, or 535 * a negative value if there is an error. 536 */ 537 static int xgpio_probe(struct platform_device *pdev) 538 { 539 struct device *dev = &pdev->dev; 540 struct xgpio_instance *chip; 541 int status = 0; 542 u32 is_dual = 0; 543 u32 width[2]; 544 u32 state[2]; 545 u32 dir[2]; 546 struct gpio_irq_chip *girq; 547 u32 temp; 548 549 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 550 if (!chip) 551 return -ENOMEM; 552 553 platform_set_drvdata(pdev, chip); 554 555 /* First, check if the device is dual-channel */ 556 device_property_read_u32(dev, "xlnx,is-dual", &is_dual); 557 558 /* Setup defaults */ 559 memset32(width, 0, ARRAY_SIZE(width)); 560 memset32(state, 0, ARRAY_SIZE(state)); 561 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); 562 563 /* Update GPIO state shadow register with default value */ 564 device_property_read_u32(dev, "xlnx,dout-default", &state[0]); 565 device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]); 566 567 bitmap_from_arr32(chip->state, state, 64); 568 569 /* Update GPIO direction shadow register with default value */ 570 device_property_read_u32(dev, "xlnx,tri-default", &dir[0]); 571 device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]); 572 573 bitmap_from_arr32(chip->dir, dir, 64); 574 575 /* 576 * Check device node and parent device node for device width 577 * and assume default width of 32 578 */ 579 if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0])) 580 width[0] = 32; 581 582 if (width[0] > 32) 583 return -EINVAL; 584 585 if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1])) 586 width[1] = 32; 587 588 if (width[1] > 32) 589 return -EINVAL; 590 591 /* Setup hardware pin mapping */ 592 bitmap_set(chip->map, 0, width[0]); 593 bitmap_set(chip->map, 32, width[1]); 594 595 raw_spin_lock_init(&chip->gpio_lock); 596 597 chip->gc.base = -1; 598 chip->gc.ngpio = bitmap_weight(chip->map, 64); 599 chip->gc.parent = dev; 600 chip->gc.direction_input = xgpio_dir_in; 601 chip->gc.direction_output = xgpio_dir_out; 602 chip->gc.get = xgpio_get; 603 chip->gc.set = xgpio_set; 604 chip->gc.request = xgpio_request; 605 chip->gc.free = xgpio_free; 606 chip->gc.set_multiple = xgpio_set_multiple; 607 608 chip->gc.label = dev_name(dev); 609 610 chip->regs = devm_platform_ioremap_resource(pdev, 0); 611 if (IS_ERR(chip->regs)) { 612 dev_err(dev, "failed to ioremap memory resource\n"); 613 return PTR_ERR(chip->regs); 614 } 615 616 chip->clk = devm_clk_get_optional_enabled(dev, NULL); 617 if (IS_ERR(chip->clk)) 618 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n"); 619 620 pm_runtime_get_noresume(dev); 621 pm_runtime_set_active(dev); 622 pm_runtime_enable(dev); 623 624 xgpio_save_regs(chip); 625 626 chip->irq = platform_get_irq_optional(pdev, 0); 627 if (chip->irq <= 0) 628 goto skip_irq; 629 630 /* Disable per-channel interrupts */ 631 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); 632 /* Clear any existing per-channel interrupts */ 633 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 634 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); 635 /* Enable global interrupts */ 636 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); 637 638 girq = &chip->gc.irq; 639 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip); 640 girq->parent_handler = xgpio_irqhandler; 641 girq->num_parents = 1; 642 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 643 GFP_KERNEL); 644 if (!girq->parents) { 645 status = -ENOMEM; 646 goto err_pm_put; 647 } 648 girq->parents[0] = chip->irq; 649 girq->default_type = IRQ_TYPE_NONE; 650 girq->handler = handle_bad_irq; 651 652 skip_irq: 653 status = devm_gpiochip_add_data(dev, &chip->gc, chip); 654 if (status) { 655 dev_err(dev, "failed to add GPIO chip\n"); 656 goto err_pm_put; 657 } 658 659 pm_runtime_put(dev); 660 return 0; 661 662 err_pm_put: 663 pm_runtime_disable(dev); 664 pm_runtime_put_noidle(dev); 665 return status; 666 } 667 668 static const struct of_device_id xgpio_of_match[] = { 669 { .compatible = "xlnx,xps-gpio-1.00.a", }, 670 { /* end of list */ }, 671 }; 672 673 MODULE_DEVICE_TABLE(of, xgpio_of_match); 674 675 static struct platform_driver xgpio_plat_driver = { 676 .probe = xgpio_probe, 677 .remove = xgpio_remove, 678 .driver = { 679 .name = "gpio-xilinx", 680 .of_match_table = xgpio_of_match, 681 .pm = &xgpio_dev_pm_ops, 682 }, 683 }; 684 685 static int __init xgpio_init(void) 686 { 687 return platform_driver_register(&xgpio_plat_driver); 688 } 689 690 subsys_initcall(xgpio_init); 691 692 static void __exit xgpio_exit(void) 693 { 694 platform_driver_unregister(&xgpio_plat_driver); 695 } 696 module_exit(xgpio_exit); 697 698 MODULE_AUTHOR("Xilinx, Inc."); 699 MODULE_DESCRIPTION("Xilinx GPIO driver"); 700 MODULE_LICENSE("GPL"); 701