1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx gpio driver for xps/axi_gpio IP. 4 * 5 * Copyright 2008 - 2013 Xilinx, Inc. 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/errno.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 23 /* Register Offset Definitions */ 24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */ 25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ 26 27 #define XGPIO_CHANNEL0_OFFSET 0x0 28 #define XGPIO_CHANNEL1_OFFSET 0x8 29 30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ 31 #define XGPIO_GIER_IE BIT(31) 32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ 33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ 34 35 /* Read/Write access to the GPIO registers */ 36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) 37 # define xgpio_readreg(offset) readl(offset) 38 # define xgpio_writereg(offset, val) writel(val, offset) 39 #else 40 # define xgpio_readreg(offset) __raw_readl(offset) 41 # define xgpio_writereg(offset, val) __raw_writel(val, offset) 42 #endif 43 44 /** 45 * struct xgpio_instance - Stores information about GPIO device 46 * @gc: GPIO chip 47 * @regs: register block 48 * @map: GPIO pin mapping on hardware side 49 * @state: GPIO write state shadow register 50 * @last_irq_read: GPIO read state register from last interrupt 51 * @dir: GPIO direction shadow register 52 * @gpio_lock: Lock used for synchronization 53 * @irq: IRQ used by GPIO device 54 * @enable: GPIO IRQ enable/disable bitfield 55 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield 56 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield 57 * @clk: clock resource for this driver 58 */ 59 struct xgpio_instance { 60 struct gpio_chip gc; 61 void __iomem *regs; 62 DECLARE_BITMAP(map, 64); 63 DECLARE_BITMAP(state, 64); 64 DECLARE_BITMAP(last_irq_read, 64); 65 DECLARE_BITMAP(dir, 64); 66 raw_spinlock_t gpio_lock; /* For serializing operations */ 67 int irq; 68 DECLARE_BITMAP(enable, 64); 69 DECLARE_BITMAP(rising_edge, 64); 70 DECLARE_BITMAP(falling_edge, 64); 71 struct clk *clk; 72 }; 73 74 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) 75 { 76 switch (ch) { 77 case 0: 78 return XGPIO_CHANNEL0_OFFSET; 79 case 1: 80 return XGPIO_CHANNEL1_OFFSET; 81 default: 82 return -EINVAL; 83 } 84 } 85 86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 87 { 88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 89 unsigned long value = xgpio_readreg(addr); 90 91 bitmap_write(a, value, round_down(bit, 32), 32); 92 } 93 94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 95 { 96 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 97 unsigned long value = bitmap_read(a, round_down(bit, 32), 32); 98 99 xgpio_writereg(addr, value); 100 } 101 102 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 103 { 104 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 105 int bit; 106 107 for (bit = 0; bit <= lastbit ; bit += 32) 108 xgpio_read_ch(chip, reg, bit, a); 109 } 110 111 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 112 { 113 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 114 int bit; 115 116 for (bit = 0; bit <= lastbit ; bit += 32) 117 xgpio_write_ch(chip, reg, bit, a); 118 } 119 120 /** 121 * xgpio_get - Read the specified signal of the GPIO device. 122 * @gc: Pointer to gpio_chip device structure. 123 * @gpio: GPIO signal number. 124 * 125 * This function reads the specified signal of the GPIO device. 126 * 127 * Return: 128 * 0 if direction of GPIO signals is set as input otherwise it 129 * returns negative error value. 130 */ 131 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 132 { 133 struct xgpio_instance *chip = gpiochip_get_data(gc); 134 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 135 DECLARE_BITMAP(state, 64); 136 137 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); 138 139 return test_bit(bit, state); 140 } 141 142 /** 143 * xgpio_set - Write the specified signal of the GPIO device. 144 * @gc: Pointer to gpio_chip device structure. 145 * @gpio: GPIO signal number. 146 * @val: Value to be written to specified signal. 147 * 148 * This function writes the specified value in to the specified signal of the 149 * GPIO device. 150 */ 151 static int xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 152 { 153 unsigned long flags; 154 struct xgpio_instance *chip = gpiochip_get_data(gc); 155 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 156 157 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 158 159 /* Write to GPIO signal and set its direction to output */ 160 __assign_bit(bit, chip->state, val); 161 162 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 163 164 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 165 166 return 0; 167 } 168 169 /** 170 * xgpio_set_multiple - Write the specified signals of the GPIO device. 171 * @gc: Pointer to gpio_chip device structure. 172 * @mask: Mask of the GPIOS to modify. 173 * @bits: Value to be wrote on each GPIO 174 * 175 * This function writes the specified values into the specified signals of the 176 * GPIO devices. 177 */ 178 static int xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 179 unsigned long *bits) 180 { 181 DECLARE_BITMAP(hw_mask, 64); 182 DECLARE_BITMAP(hw_bits, 64); 183 DECLARE_BITMAP(state, 64); 184 unsigned long flags; 185 struct xgpio_instance *chip = gpiochip_get_data(gc); 186 187 bitmap_scatter(hw_mask, mask, chip->map, 64); 188 bitmap_scatter(hw_bits, bits, chip->map, 64); 189 190 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 191 192 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); 193 194 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); 195 196 bitmap_copy(chip->state, state, 64); 197 198 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 199 200 return 0; 201 } 202 203 /** 204 * xgpio_dir_in - Set the direction of the specified GPIO signal as input. 205 * @gc: Pointer to gpio_chip device structure. 206 * @gpio: GPIO signal number. 207 * 208 * Return: 209 * 0 - if direction of GPIO signals is set as input 210 * otherwise it returns negative error value. 211 */ 212 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 213 { 214 unsigned long flags; 215 struct xgpio_instance *chip = gpiochip_get_data(gc); 216 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 217 218 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 219 220 /* Set the GPIO bit in shadow register and set direction as input */ 221 __set_bit(bit, chip->dir); 222 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 223 224 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 225 226 return 0; 227 } 228 229 /** 230 * xgpio_dir_out - Set the direction of the specified GPIO signal as output. 231 * @gc: Pointer to gpio_chip device structure. 232 * @gpio: GPIO signal number. 233 * @val: Value to be written to specified signal. 234 * 235 * This function sets the direction of specified GPIO signal as output. 236 * 237 * Return: 238 * If all GPIO signals of GPIO chip is configured as input then it returns 239 * error otherwise it returns 0. 240 */ 241 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 242 { 243 unsigned long flags; 244 struct xgpio_instance *chip = gpiochip_get_data(gc); 245 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 246 247 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 248 249 /* Write state of GPIO signal */ 250 __assign_bit(bit, chip->state, val); 251 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 252 253 /* Clear the GPIO bit in shadow register and set direction as output */ 254 __clear_bit(bit, chip->dir); 255 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 256 257 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 258 259 return 0; 260 } 261 262 /** 263 * xgpio_save_regs - Set initial values of GPIO pins 264 * @chip: Pointer to GPIO instance 265 */ 266 static void xgpio_save_regs(struct xgpio_instance *chip) 267 { 268 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); 269 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); 270 } 271 272 static int xgpio_request(struct gpio_chip *chip, unsigned int offset) 273 { 274 int ret; 275 276 ret = pm_runtime_get_sync(chip->parent); 277 /* 278 * If the device is already active pm_runtime_get() will return 1 on 279 * success, but gpio_request still needs to return 0. 280 */ 281 return ret < 0 ? ret : 0; 282 } 283 284 static void xgpio_free(struct gpio_chip *chip, unsigned int offset) 285 { 286 pm_runtime_put(chip->parent); 287 } 288 289 static int xgpio_suspend(struct device *dev) 290 { 291 struct xgpio_instance *gpio = dev_get_drvdata(dev); 292 struct irq_data *data = irq_get_irq_data(gpio->irq); 293 294 if (!data) { 295 dev_dbg(dev, "IRQ not connected\n"); 296 return pm_runtime_force_suspend(dev); 297 } 298 299 if (!irqd_is_wakeup_set(data)) 300 return pm_runtime_force_suspend(dev); 301 302 return 0; 303 } 304 305 /** 306 * xgpio_remove - Remove method for the GPIO device. 307 * @pdev: pointer to the platform device 308 * 309 * This function remove gpiochips and frees all the allocated resources. 310 * 311 * Return: 0 always 312 */ 313 static void xgpio_remove(struct platform_device *pdev) 314 { 315 pm_runtime_get_sync(&pdev->dev); 316 pm_runtime_put_noidle(&pdev->dev); 317 pm_runtime_disable(&pdev->dev); 318 } 319 320 /** 321 * xgpio_irq_ack - Acknowledge a child GPIO interrupt. 322 * @irq_data: per IRQ and chip data passed down to chip functions 323 * This currently does nothing, but irq_ack is unconditionally called by 324 * handle_edge_irq and therefore must be defined. 325 */ 326 static void xgpio_irq_ack(struct irq_data *irq_data) 327 { 328 } 329 330 static int xgpio_resume(struct device *dev) 331 { 332 struct xgpio_instance *gpio = dev_get_drvdata(dev); 333 struct irq_data *data = irq_get_irq_data(gpio->irq); 334 335 if (!data) { 336 dev_dbg(dev, "IRQ not connected\n"); 337 return pm_runtime_force_resume(dev); 338 } 339 340 if (!irqd_is_wakeup_set(data)) 341 return pm_runtime_force_resume(dev); 342 343 return 0; 344 } 345 346 static int xgpio_runtime_suspend(struct device *dev) 347 { 348 struct xgpio_instance *gpio = dev_get_drvdata(dev); 349 350 clk_disable(gpio->clk); 351 352 return 0; 353 } 354 355 static int xgpio_runtime_resume(struct device *dev) 356 { 357 struct xgpio_instance *gpio = dev_get_drvdata(dev); 358 359 return clk_enable(gpio->clk); 360 } 361 362 static const struct dev_pm_ops xgpio_dev_pm_ops = { 363 SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) 364 RUNTIME_PM_OPS(xgpio_runtime_suspend, xgpio_runtime_resume, NULL) 365 }; 366 367 /** 368 * xgpio_irq_mask - Write the specified signal of the GPIO device. 369 * @irq_data: per IRQ and chip data passed down to chip functions 370 */ 371 static void xgpio_irq_mask(struct irq_data *irq_data) 372 { 373 unsigned long flags; 374 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 375 int irq_offset = irqd_to_hwirq(irq_data); 376 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 377 u32 mask = BIT(bit / 32), temp; 378 379 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 380 381 __clear_bit(bit, chip->enable); 382 383 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 384 if (enable == 0) { 385 /* Disable per channel interrupt */ 386 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 387 temp &= ~mask; 388 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); 389 } 390 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 391 392 gpiochip_disable_irq(&chip->gc, irq_offset); 393 } 394 395 /** 396 * xgpio_irq_unmask - Write the specified signal of the GPIO device. 397 * @irq_data: per IRQ and chip data passed down to chip functions 398 */ 399 static void xgpio_irq_unmask(struct irq_data *irq_data) 400 { 401 unsigned long flags; 402 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 403 int irq_offset = irqd_to_hwirq(irq_data); 404 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 405 u32 mask = BIT(bit / 32), val; 406 407 gpiochip_enable_irq(&chip->gc, irq_offset); 408 409 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 410 411 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 412 if (enable == 0) { 413 /* Clear any existing per-channel interrupts */ 414 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 415 val &= mask; 416 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); 417 418 /* Update GPIO IRQ read data before enabling interrupt*/ 419 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); 420 421 /* Enable per channel interrupt */ 422 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 423 val |= mask; 424 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 425 } 426 427 __set_bit(bit, chip->enable); 428 429 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 430 } 431 432 /** 433 * xgpio_set_irq_type - Write the specified signal of the GPIO device. 434 * @irq_data: Per IRQ and chip data passed down to chip functions 435 * @type: Interrupt type that is to be set for the gpio pin 436 * 437 * Return: 438 * 0 if interrupt type is supported otherwise -EINVAL 439 */ 440 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 441 { 442 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 443 int irq_offset = irqd_to_hwirq(irq_data); 444 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset); 445 446 /* 447 * The Xilinx GPIO hardware provides a single interrupt status 448 * indication for any state change in a given GPIO channel (bank). 449 * Therefore, only rising edge or falling edge triggers are 450 * supported. 451 */ 452 switch (type & IRQ_TYPE_SENSE_MASK) { 453 case IRQ_TYPE_EDGE_BOTH: 454 __set_bit(bit, chip->rising_edge); 455 __set_bit(bit, chip->falling_edge); 456 break; 457 case IRQ_TYPE_EDGE_RISING: 458 __set_bit(bit, chip->rising_edge); 459 __clear_bit(bit, chip->falling_edge); 460 break; 461 case IRQ_TYPE_EDGE_FALLING: 462 __clear_bit(bit, chip->rising_edge); 463 __set_bit(bit, chip->falling_edge); 464 break; 465 default: 466 return -EINVAL; 467 } 468 469 irq_set_handler_locked(irq_data, handle_edge_irq); 470 return 0; 471 } 472 473 /** 474 * xgpio_irqhandler - Gpio interrupt service routine 475 * @desc: Pointer to interrupt description 476 */ 477 static void xgpio_irqhandler(struct irq_desc *desc) 478 { 479 struct xgpio_instance *chip = irq_desc_get_handler_data(desc); 480 struct gpio_chip *gc = &chip->gc; 481 struct irq_chip *irqchip = irq_desc_get_chip(desc); 482 DECLARE_BITMAP(rising, 64); 483 DECLARE_BITMAP(falling, 64); 484 DECLARE_BITMAP(hw, 64); 485 DECLARE_BITMAP(sw, 64); 486 int irq_offset; 487 u32 status; 488 489 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 490 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); 491 492 chained_irq_enter(irqchip, desc); 493 494 raw_spin_lock(&chip->gpio_lock); 495 496 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw); 497 498 bitmap_complement(rising, chip->last_irq_read, 64); 499 bitmap_and(rising, rising, hw, 64); 500 bitmap_and(rising, rising, chip->enable, 64); 501 bitmap_and(rising, rising, chip->rising_edge, 64); 502 503 bitmap_complement(falling, hw, 64); 504 bitmap_and(falling, falling, chip->last_irq_read, 64); 505 bitmap_and(falling, falling, chip->enable, 64); 506 bitmap_and(falling, falling, chip->falling_edge, 64); 507 508 bitmap_copy(chip->last_irq_read, hw, 64); 509 bitmap_or(hw, rising, falling, 64); 510 511 raw_spin_unlock(&chip->gpio_lock); 512 513 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); 514 515 bitmap_gather(sw, hw, chip->map, 64); 516 for_each_set_bit(irq_offset, sw, 64) 517 generic_handle_domain_irq(gc->irq.domain, irq_offset); 518 519 chained_irq_exit(irqchip, desc); 520 } 521 522 static const struct irq_chip xgpio_irq_chip = { 523 .name = "gpio-xilinx", 524 .irq_ack = xgpio_irq_ack, 525 .irq_mask = xgpio_irq_mask, 526 .irq_unmask = xgpio_irq_unmask, 527 .irq_set_type = xgpio_set_irq_type, 528 .flags = IRQCHIP_IMMUTABLE, 529 GPIOCHIP_IRQ_RESOURCE_HELPERS, 530 }; 531 532 /** 533 * xgpio_probe - Probe method for the GPIO device. 534 * @pdev: pointer to the platform device 535 * 536 * Return: 537 * It returns 0, if the driver is bound to the GPIO device, or 538 * a negative value if there is an error. 539 */ 540 static int xgpio_probe(struct platform_device *pdev) 541 { 542 struct device *dev = &pdev->dev; 543 struct xgpio_instance *chip; 544 int status = 0; 545 u32 is_dual = 0; 546 u32 width[2]; 547 u32 state[2]; 548 u32 dir[2]; 549 struct gpio_irq_chip *girq; 550 u32 temp; 551 552 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 553 if (!chip) 554 return -ENOMEM; 555 556 platform_set_drvdata(pdev, chip); 557 558 /* First, check if the device is dual-channel */ 559 device_property_read_u32(dev, "xlnx,is-dual", &is_dual); 560 561 /* Setup defaults */ 562 memset32(width, 0, ARRAY_SIZE(width)); 563 memset32(state, 0, ARRAY_SIZE(state)); 564 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); 565 566 /* Update GPIO state shadow register with default value */ 567 device_property_read_u32(dev, "xlnx,dout-default", &state[0]); 568 device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]); 569 570 bitmap_from_arr32(chip->state, state, 64); 571 572 /* Update GPIO direction shadow register with default value */ 573 device_property_read_u32(dev, "xlnx,tri-default", &dir[0]); 574 device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]); 575 576 bitmap_from_arr32(chip->dir, dir, 64); 577 578 /* 579 * Check device node and parent device node for device width 580 * and assume default width of 32 581 */ 582 if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0])) 583 width[0] = 32; 584 585 if (width[0] > 32) 586 return -EINVAL; 587 588 if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1])) 589 width[1] = 32; 590 591 if (width[1] > 32) 592 return -EINVAL; 593 594 /* Setup hardware pin mapping */ 595 bitmap_set(chip->map, 0, width[0]); 596 bitmap_set(chip->map, 32, width[1]); 597 598 raw_spin_lock_init(&chip->gpio_lock); 599 600 chip->gc.base = -1; 601 chip->gc.ngpio = bitmap_weight(chip->map, 64); 602 chip->gc.parent = dev; 603 chip->gc.direction_input = xgpio_dir_in; 604 chip->gc.direction_output = xgpio_dir_out; 605 chip->gc.get = xgpio_get; 606 chip->gc.set = xgpio_set; 607 chip->gc.request = xgpio_request; 608 chip->gc.free = xgpio_free; 609 chip->gc.set_multiple = xgpio_set_multiple; 610 611 chip->gc.label = dev_name(dev); 612 613 chip->regs = devm_platform_ioremap_resource(pdev, 0); 614 if (IS_ERR(chip->regs)) { 615 dev_err(dev, "failed to ioremap memory resource\n"); 616 return PTR_ERR(chip->regs); 617 } 618 619 chip->clk = devm_clk_get_optional_enabled(dev, NULL); 620 if (IS_ERR(chip->clk)) 621 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n"); 622 623 pm_runtime_get_noresume(dev); 624 pm_runtime_set_active(dev); 625 pm_runtime_enable(dev); 626 627 xgpio_save_regs(chip); 628 629 chip->irq = platform_get_irq_optional(pdev, 0); 630 if (chip->irq <= 0) 631 goto skip_irq; 632 633 /* Disable per-channel interrupts */ 634 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); 635 /* Clear any existing per-channel interrupts */ 636 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 637 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); 638 /* Enable global interrupts */ 639 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); 640 641 girq = &chip->gc.irq; 642 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip); 643 girq->parent_handler = xgpio_irqhandler; 644 girq->num_parents = 1; 645 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 646 GFP_KERNEL); 647 if (!girq->parents) { 648 status = -ENOMEM; 649 goto err_pm_put; 650 } 651 girq->parents[0] = chip->irq; 652 girq->default_type = IRQ_TYPE_NONE; 653 girq->handler = handle_bad_irq; 654 655 skip_irq: 656 status = devm_gpiochip_add_data(dev, &chip->gc, chip); 657 if (status) { 658 dev_err(dev, "failed to add GPIO chip\n"); 659 goto err_pm_put; 660 } 661 662 pm_runtime_put(dev); 663 return 0; 664 665 err_pm_put: 666 pm_runtime_disable(dev); 667 pm_runtime_put_noidle(dev); 668 return status; 669 } 670 671 static const struct of_device_id xgpio_of_match[] = { 672 { .compatible = "xlnx,xps-gpio-1.00.a", }, 673 { /* end of list */ }, 674 }; 675 676 MODULE_DEVICE_TABLE(of, xgpio_of_match); 677 678 static struct platform_driver xgpio_plat_driver = { 679 .probe = xgpio_probe, 680 .remove = xgpio_remove, 681 .driver = { 682 .name = "gpio-xilinx", 683 .of_match_table = xgpio_of_match, 684 .pm = pm_ptr(&xgpio_dev_pm_ops), 685 }, 686 }; 687 688 static int __init xgpio_init(void) 689 { 690 return platform_driver_register(&xgpio_plat_driver); 691 } 692 693 subsys_initcall(xgpio_init); 694 695 static void __exit xgpio_exit(void) 696 { 697 platform_driver_unregister(&xgpio_plat_driver); 698 } 699 module_exit(xgpio_exit); 700 701 MODULE_AUTHOR("Xilinx, Inc."); 702 MODULE_DESCRIPTION("Xilinx GPIO driver"); 703 MODULE_LICENSE("GPL"); 704