1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx gpio driver for xps/axi_gpio IP. 4 * 5 * Copyright 2008 - 2013 Xilinx, Inc. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/of_platform.h> 19 #include <linux/slab.h> 20 21 /* Register Offset Definitions */ 22 #define XGPIO_DATA_OFFSET (0x0) /* Data register */ 23 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ 24 25 #define XGPIO_CHANNEL_OFFSET 0x8 26 27 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ 28 #define XGPIO_GIER_IE BIT(31) 29 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ 30 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ 31 32 /* Read/Write access to the GPIO registers */ 33 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) 34 # define xgpio_readreg(offset) readl(offset) 35 # define xgpio_writereg(offset, val) writel(val, offset) 36 #else 37 # define xgpio_readreg(offset) __raw_readl(offset) 38 # define xgpio_writereg(offset, val) __raw_writel(val, offset) 39 #endif 40 41 /** 42 * struct xgpio_instance - Stores information about GPIO device 43 * @gc: GPIO chip 44 * @regs: register block 45 * @gpio_width: GPIO width for every channel 46 * @gpio_state: GPIO write state shadow register 47 * @gpio_last_irq_read: GPIO read state register from last interrupt 48 * @gpio_dir: GPIO direction shadow register 49 * @gpio_lock: Lock used for synchronization 50 * @irq: IRQ used by GPIO device 51 * @irqchip: IRQ chip 52 * @irq_enable: GPIO IRQ enable/disable bitfield 53 * @irq_rising_edge: GPIO IRQ rising edge enable/disable bitfield 54 * @irq_falling_edge: GPIO IRQ falling edge enable/disable bitfield 55 * @clk: clock resource for this driver 56 */ 57 struct xgpio_instance { 58 struct gpio_chip gc; 59 void __iomem *regs; 60 unsigned int gpio_width[2]; 61 u32 gpio_state[2]; 62 u32 gpio_last_irq_read[2]; 63 u32 gpio_dir[2]; 64 spinlock_t gpio_lock; /* For serializing operations */ 65 int irq; 66 struct irq_chip irqchip; 67 u32 irq_enable[2]; 68 u32 irq_rising_edge[2]; 69 u32 irq_falling_edge[2]; 70 struct clk *clk; 71 }; 72 73 static inline int xgpio_index(struct xgpio_instance *chip, int gpio) 74 { 75 if (gpio >= chip->gpio_width[0]) 76 return 1; 77 78 return 0; 79 } 80 81 static inline int xgpio_regoffset(struct xgpio_instance *chip, int gpio) 82 { 83 if (xgpio_index(chip, gpio)) 84 return XGPIO_CHANNEL_OFFSET; 85 86 return 0; 87 } 88 89 static inline int xgpio_offset(struct xgpio_instance *chip, int gpio) 90 { 91 if (xgpio_index(chip, gpio)) 92 return gpio - chip->gpio_width[0]; 93 94 return gpio; 95 } 96 97 /** 98 * xgpio_get - Read the specified signal of the GPIO device. 99 * @gc: Pointer to gpio_chip device structure. 100 * @gpio: GPIO signal number. 101 * 102 * This function reads the specified signal of the GPIO device. 103 * 104 * Return: 105 * 0 if direction of GPIO signals is set as input otherwise it 106 * returns negative error value. 107 */ 108 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 109 { 110 struct xgpio_instance *chip = gpiochip_get_data(gc); 111 u32 val; 112 113 val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 114 xgpio_regoffset(chip, gpio)); 115 116 return !!(val & BIT(xgpio_offset(chip, gpio))); 117 } 118 119 /** 120 * xgpio_set - Write the specified signal of the GPIO device. 121 * @gc: Pointer to gpio_chip device structure. 122 * @gpio: GPIO signal number. 123 * @val: Value to be written to specified signal. 124 * 125 * This function writes the specified value in to the specified signal of the 126 * GPIO device. 127 */ 128 static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 129 { 130 unsigned long flags; 131 struct xgpio_instance *chip = gpiochip_get_data(gc); 132 int index = xgpio_index(chip, gpio); 133 int offset = xgpio_offset(chip, gpio); 134 135 spin_lock_irqsave(&chip->gpio_lock, flags); 136 137 /* Write to GPIO signal and set its direction to output */ 138 if (val) 139 chip->gpio_state[index] |= BIT(offset); 140 else 141 chip->gpio_state[index] &= ~BIT(offset); 142 143 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 144 xgpio_regoffset(chip, gpio), chip->gpio_state[index]); 145 146 spin_unlock_irqrestore(&chip->gpio_lock, flags); 147 } 148 149 /** 150 * xgpio_set_multiple - Write the specified signals of the GPIO device. 151 * @gc: Pointer to gpio_chip device structure. 152 * @mask: Mask of the GPIOS to modify. 153 * @bits: Value to be wrote on each GPIO 154 * 155 * This function writes the specified values into the specified signals of the 156 * GPIO devices. 157 */ 158 static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 159 unsigned long *bits) 160 { 161 unsigned long flags; 162 struct xgpio_instance *chip = gpiochip_get_data(gc); 163 int index = xgpio_index(chip, 0); 164 int offset, i; 165 166 spin_lock_irqsave(&chip->gpio_lock, flags); 167 168 /* Write to GPIO signals */ 169 for (i = 0; i < gc->ngpio; i++) { 170 if (*mask == 0) 171 break; 172 /* Once finished with an index write it out to the register */ 173 if (index != xgpio_index(chip, i)) { 174 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 175 index * XGPIO_CHANNEL_OFFSET, 176 chip->gpio_state[index]); 177 spin_unlock_irqrestore(&chip->gpio_lock, flags); 178 index = xgpio_index(chip, i); 179 spin_lock_irqsave(&chip->gpio_lock, flags); 180 } 181 if (__test_and_clear_bit(i, mask)) { 182 offset = xgpio_offset(chip, i); 183 if (test_bit(i, bits)) 184 chip->gpio_state[index] |= BIT(offset); 185 else 186 chip->gpio_state[index] &= ~BIT(offset); 187 } 188 } 189 190 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 191 index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); 192 193 spin_unlock_irqrestore(&chip->gpio_lock, flags); 194 } 195 196 /** 197 * xgpio_dir_in - Set the direction of the specified GPIO signal as input. 198 * @gc: Pointer to gpio_chip device structure. 199 * @gpio: GPIO signal number. 200 * 201 * Return: 202 * 0 - if direction of GPIO signals is set as input 203 * otherwise it returns negative error value. 204 */ 205 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 206 { 207 unsigned long flags; 208 struct xgpio_instance *chip = gpiochip_get_data(gc); 209 int index = xgpio_index(chip, gpio); 210 int offset = xgpio_offset(chip, gpio); 211 212 spin_lock_irqsave(&chip->gpio_lock, flags); 213 214 /* Set the GPIO bit in shadow register and set direction as input */ 215 chip->gpio_dir[index] |= BIT(offset); 216 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + 217 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); 218 219 spin_unlock_irqrestore(&chip->gpio_lock, flags); 220 221 return 0; 222 } 223 224 /** 225 * xgpio_dir_out - Set the direction of the specified GPIO signal as output. 226 * @gc: Pointer to gpio_chip device structure. 227 * @gpio: GPIO signal number. 228 * @val: Value to be written to specified signal. 229 * 230 * This function sets the direction of specified GPIO signal as output. 231 * 232 * Return: 233 * If all GPIO signals of GPIO chip is configured as input then it returns 234 * error otherwise it returns 0. 235 */ 236 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 237 { 238 unsigned long flags; 239 struct xgpio_instance *chip = gpiochip_get_data(gc); 240 int index = xgpio_index(chip, gpio); 241 int offset = xgpio_offset(chip, gpio); 242 243 spin_lock_irqsave(&chip->gpio_lock, flags); 244 245 /* Write state of GPIO signal */ 246 if (val) 247 chip->gpio_state[index] |= BIT(offset); 248 else 249 chip->gpio_state[index] &= ~BIT(offset); 250 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + 251 xgpio_regoffset(chip, gpio), chip->gpio_state[index]); 252 253 /* Clear the GPIO bit in shadow register and set direction as output */ 254 chip->gpio_dir[index] &= ~BIT(offset); 255 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + 256 xgpio_regoffset(chip, gpio), chip->gpio_dir[index]); 257 258 spin_unlock_irqrestore(&chip->gpio_lock, flags); 259 260 return 0; 261 } 262 263 /** 264 * xgpio_save_regs - Set initial values of GPIO pins 265 * @chip: Pointer to GPIO instance 266 */ 267 static void xgpio_save_regs(struct xgpio_instance *chip) 268 { 269 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, chip->gpio_state[0]); 270 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET, chip->gpio_dir[0]); 271 272 if (!chip->gpio_width[1]) 273 return; 274 275 xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + XGPIO_CHANNEL_OFFSET, 276 chip->gpio_state[1]); 277 xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET + XGPIO_CHANNEL_OFFSET, 278 chip->gpio_dir[1]); 279 } 280 281 /** 282 * xgpio_remove - Remove method for the GPIO device. 283 * @pdev: pointer to the platform device 284 * 285 * This function remove gpiochips and frees all the allocated resources. 286 * 287 * Return: 0 always 288 */ 289 static int xgpio_remove(struct platform_device *pdev) 290 { 291 struct xgpio_instance *gpio = platform_get_drvdata(pdev); 292 293 clk_disable_unprepare(gpio->clk); 294 295 return 0; 296 } 297 298 /** 299 * xgpio_irq_ack - Acknowledge a child GPIO interrupt. 300 * @irq_data: per IRQ and chip data passed down to chip functions 301 * This currently does nothing, but irq_ack is unconditionally called by 302 * handle_edge_irq and therefore must be defined. 303 */ 304 static void xgpio_irq_ack(struct irq_data *irq_data) 305 { 306 } 307 308 /** 309 * xgpio_irq_mask - Write the specified signal of the GPIO device. 310 * @irq_data: per IRQ and chip data passed down to chip functions 311 */ 312 static void xgpio_irq_mask(struct irq_data *irq_data) 313 { 314 unsigned long flags; 315 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 316 int irq_offset = irqd_to_hwirq(irq_data); 317 int index = xgpio_index(chip, irq_offset); 318 int offset = xgpio_offset(chip, irq_offset); 319 320 spin_lock_irqsave(&chip->gpio_lock, flags); 321 322 chip->irq_enable[index] &= ~BIT(offset); 323 324 if (!chip->irq_enable[index]) { 325 /* Disable per channel interrupt */ 326 u32 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 327 328 temp &= ~BIT(index); 329 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); 330 } 331 spin_unlock_irqrestore(&chip->gpio_lock, flags); 332 } 333 334 /** 335 * xgpio_irq_unmask - Write the specified signal of the GPIO device. 336 * @irq_data: per IRQ and chip data passed down to chip functions 337 */ 338 static void xgpio_irq_unmask(struct irq_data *irq_data) 339 { 340 unsigned long flags; 341 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 342 int irq_offset = irqd_to_hwirq(irq_data); 343 int index = xgpio_index(chip, irq_offset); 344 int offset = xgpio_offset(chip, irq_offset); 345 u32 old_enable = chip->irq_enable[index]; 346 347 spin_lock_irqsave(&chip->gpio_lock, flags); 348 349 chip->irq_enable[index] |= BIT(offset); 350 351 if (!old_enable) { 352 /* Clear any existing per-channel interrupts */ 353 u32 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET) & 354 BIT(index); 355 356 if (val) 357 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); 358 359 /* Update GPIO IRQ read data before enabling interrupt*/ 360 val = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 361 index * XGPIO_CHANNEL_OFFSET); 362 chip->gpio_last_irq_read[index] = val; 363 364 /* Enable per channel interrupt */ 365 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 366 val |= BIT(index); 367 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 368 } 369 370 spin_unlock_irqrestore(&chip->gpio_lock, flags); 371 } 372 373 /** 374 * xgpio_set_irq_type - Write the specified signal of the GPIO device. 375 * @irq_data: Per IRQ and chip data passed down to chip functions 376 * @type: Interrupt type that is to be set for the gpio pin 377 * 378 * Return: 379 * 0 if interrupt type is supported otherwise -EINVAL 380 */ 381 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 382 { 383 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 384 int irq_offset = irqd_to_hwirq(irq_data); 385 int index = xgpio_index(chip, irq_offset); 386 int offset = xgpio_offset(chip, irq_offset); 387 388 /* 389 * The Xilinx GPIO hardware provides a single interrupt status 390 * indication for any state change in a given GPIO channel (bank). 391 * Therefore, only rising edge or falling edge triggers are 392 * supported. 393 */ 394 switch (type & IRQ_TYPE_SENSE_MASK) { 395 case IRQ_TYPE_EDGE_BOTH: 396 chip->irq_rising_edge[index] |= BIT(offset); 397 chip->irq_falling_edge[index] |= BIT(offset); 398 break; 399 case IRQ_TYPE_EDGE_RISING: 400 chip->irq_rising_edge[index] |= BIT(offset); 401 chip->irq_falling_edge[index] &= ~BIT(offset); 402 break; 403 case IRQ_TYPE_EDGE_FALLING: 404 chip->irq_rising_edge[index] &= ~BIT(offset); 405 chip->irq_falling_edge[index] |= BIT(offset); 406 break; 407 default: 408 return -EINVAL; 409 } 410 411 irq_set_handler_locked(irq_data, handle_edge_irq); 412 return 0; 413 } 414 415 /** 416 * xgpio_irqhandler - Gpio interrupt service routine 417 * @desc: Pointer to interrupt description 418 */ 419 static void xgpio_irqhandler(struct irq_desc *desc) 420 { 421 struct xgpio_instance *chip = irq_desc_get_handler_data(desc); 422 struct irq_chip *irqchip = irq_desc_get_chip(desc); 423 u32 num_channels = chip->gpio_width[1] ? 2 : 1; 424 u32 offset = 0, index; 425 u32 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 426 427 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); 428 429 chained_irq_enter(irqchip, desc); 430 for (index = 0; index < num_channels; index++) { 431 if ((status & BIT(index))) { 432 unsigned long rising_events, falling_events, all_events; 433 unsigned long flags; 434 u32 data, bit; 435 unsigned int irq; 436 437 spin_lock_irqsave(&chip->gpio_lock, flags); 438 data = xgpio_readreg(chip->regs + XGPIO_DATA_OFFSET + 439 index * XGPIO_CHANNEL_OFFSET); 440 rising_events = data & 441 ~chip->gpio_last_irq_read[index] & 442 chip->irq_enable[index] & 443 chip->irq_rising_edge[index]; 444 falling_events = ~data & 445 chip->gpio_last_irq_read[index] & 446 chip->irq_enable[index] & 447 chip->irq_falling_edge[index]; 448 dev_dbg(chip->gc.parent, 449 "IRQ chan %u rising 0x%lx falling 0x%lx\n", 450 index, rising_events, falling_events); 451 all_events = rising_events | falling_events; 452 chip->gpio_last_irq_read[index] = data; 453 spin_unlock_irqrestore(&chip->gpio_lock, flags); 454 455 for_each_set_bit(bit, &all_events, 32) { 456 irq = irq_find_mapping(chip->gc.irq.domain, 457 offset + bit); 458 generic_handle_irq(irq); 459 } 460 } 461 offset += chip->gpio_width[index]; 462 } 463 464 chained_irq_exit(irqchip, desc); 465 } 466 467 /** 468 * xgpio_of_probe - Probe method for the GPIO device. 469 * @pdev: pointer to the platform device 470 * 471 * Return: 472 * It returns 0, if the driver is bound to the GPIO device, or 473 * a negative value if there is an error. 474 */ 475 static int xgpio_probe(struct platform_device *pdev) 476 { 477 struct xgpio_instance *chip; 478 int status = 0; 479 struct device_node *np = pdev->dev.of_node; 480 u32 is_dual = 0; 481 u32 cells = 2; 482 struct gpio_irq_chip *girq; 483 u32 temp; 484 485 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 486 if (!chip) 487 return -ENOMEM; 488 489 platform_set_drvdata(pdev, chip); 490 491 /* Update GPIO state shadow register with default value */ 492 if (of_property_read_u32(np, "xlnx,dout-default", &chip->gpio_state[0])) 493 chip->gpio_state[0] = 0x0; 494 495 /* Update GPIO direction shadow register with default value */ 496 if (of_property_read_u32(np, "xlnx,tri-default", &chip->gpio_dir[0])) 497 chip->gpio_dir[0] = 0xFFFFFFFF; 498 499 /* Update cells with gpio-cells value */ 500 if (of_property_read_u32(np, "#gpio-cells", &cells)) 501 dev_dbg(&pdev->dev, "Missing gpio-cells property\n"); 502 503 if (cells != 2) { 504 dev_err(&pdev->dev, "#gpio-cells mismatch\n"); 505 return -EINVAL; 506 } 507 508 /* 509 * Check device node and parent device node for device width 510 * and assume default width of 32 511 */ 512 if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0])) 513 chip->gpio_width[0] = 32; 514 515 spin_lock_init(&chip->gpio_lock); 516 517 if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) 518 is_dual = 0; 519 520 if (is_dual) { 521 /* Update GPIO state shadow register with default value */ 522 if (of_property_read_u32(np, "xlnx,dout-default-2", 523 &chip->gpio_state[1])) 524 chip->gpio_state[1] = 0x0; 525 526 /* Update GPIO direction shadow register with default value */ 527 if (of_property_read_u32(np, "xlnx,tri-default-2", 528 &chip->gpio_dir[1])) 529 chip->gpio_dir[1] = 0xFFFFFFFF; 530 531 /* 532 * Check device node and parent device node for device width 533 * and assume default width of 32 534 */ 535 if (of_property_read_u32(np, "xlnx,gpio2-width", 536 &chip->gpio_width[1])) 537 chip->gpio_width[1] = 32; 538 539 } 540 541 chip->gc.base = -1; 542 chip->gc.ngpio = chip->gpio_width[0] + chip->gpio_width[1]; 543 chip->gc.parent = &pdev->dev; 544 chip->gc.direction_input = xgpio_dir_in; 545 chip->gc.direction_output = xgpio_dir_out; 546 chip->gc.of_gpio_n_cells = cells; 547 chip->gc.get = xgpio_get; 548 chip->gc.set = xgpio_set; 549 chip->gc.set_multiple = xgpio_set_multiple; 550 551 chip->gc.label = dev_name(&pdev->dev); 552 553 chip->regs = devm_platform_ioremap_resource(pdev, 0); 554 if (IS_ERR(chip->regs)) { 555 dev_err(&pdev->dev, "failed to ioremap memory resource\n"); 556 return PTR_ERR(chip->regs); 557 } 558 559 chip->clk = devm_clk_get_optional(&pdev->dev, NULL); 560 if (IS_ERR(chip->clk)) 561 return dev_err_probe(&pdev->dev, PTR_ERR(chip->clk), "input clock not found.\n"); 562 563 status = clk_prepare_enable(chip->clk); 564 if (status < 0) { 565 dev_err(&pdev->dev, "Failed to prepare clk\n"); 566 return status; 567 } 568 569 xgpio_save_regs(chip); 570 571 chip->irq = platform_get_irq_optional(pdev, 0); 572 if (chip->irq <= 0) 573 goto skip_irq; 574 575 chip->irqchip.name = "gpio-xilinx"; 576 chip->irqchip.irq_ack = xgpio_irq_ack; 577 chip->irqchip.irq_mask = xgpio_irq_mask; 578 chip->irqchip.irq_unmask = xgpio_irq_unmask; 579 chip->irqchip.irq_set_type = xgpio_set_irq_type; 580 581 /* Disable per-channel interrupts */ 582 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); 583 /* Clear any existing per-channel interrupts */ 584 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 585 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); 586 /* Enable global interrupts */ 587 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); 588 589 girq = &chip->gc.irq; 590 girq->chip = &chip->irqchip; 591 girq->parent_handler = xgpio_irqhandler; 592 girq->num_parents = 1; 593 girq->parents = devm_kcalloc(&pdev->dev, 1, 594 sizeof(*girq->parents), 595 GFP_KERNEL); 596 if (!girq->parents) { 597 status = -ENOMEM; 598 goto err_unprepare_clk; 599 } 600 girq->parents[0] = chip->irq; 601 girq->default_type = IRQ_TYPE_NONE; 602 girq->handler = handle_bad_irq; 603 604 skip_irq: 605 status = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); 606 if (status) { 607 dev_err(&pdev->dev, "failed to add GPIO chip\n"); 608 goto err_unprepare_clk; 609 } 610 611 return 0; 612 613 err_unprepare_clk: 614 clk_disable_unprepare(chip->clk); 615 return status; 616 } 617 618 static const struct of_device_id xgpio_of_match[] = { 619 { .compatible = "xlnx,xps-gpio-1.00.a", }, 620 { /* end of list */ }, 621 }; 622 623 MODULE_DEVICE_TABLE(of, xgpio_of_match); 624 625 static struct platform_driver xgpio_plat_driver = { 626 .probe = xgpio_probe, 627 .remove = xgpio_remove, 628 .driver = { 629 .name = "gpio-xilinx", 630 .of_match_table = xgpio_of_match, 631 }, 632 }; 633 634 static int __init xgpio_init(void) 635 { 636 return platform_driver_register(&xgpio_plat_driver); 637 } 638 639 subsys_initcall(xgpio_init); 640 641 static void __exit xgpio_exit(void) 642 { 643 platform_driver_unregister(&xgpio_plat_driver); 644 } 645 module_exit(xgpio_exit); 646 647 MODULE_AUTHOR("Xilinx, Inc."); 648 MODULE_DESCRIPTION("Xilinx GPIO driver"); 649 MODULE_LICENSE("GPL"); 650