1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Xilinx gpio driver for xps/axi_gpio IP. 4 * 5 * Copyright 2008 - 2013 Xilinx, Inc. 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/errno.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 23 /* Register Offset Definitions */ 24 #define XGPIO_DATA_OFFSET (0x0) /* Data register */ 25 #define XGPIO_TRI_OFFSET (0x4) /* I/O direction register */ 26 27 #define XGPIO_CHANNEL0_OFFSET 0x0 28 #define XGPIO_CHANNEL1_OFFSET 0x8 29 30 #define XGPIO_GIER_OFFSET 0x11c /* Global Interrupt Enable */ 31 #define XGPIO_GIER_IE BIT(31) 32 #define XGPIO_IPISR_OFFSET 0x120 /* IP Interrupt Status */ 33 #define XGPIO_IPIER_OFFSET 0x128 /* IP Interrupt Enable */ 34 35 /* Read/Write access to the GPIO registers */ 36 #if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_X86) 37 # define xgpio_readreg(offset) readl(offset) 38 # define xgpio_writereg(offset, val) writel(val, offset) 39 #else 40 # define xgpio_readreg(offset) __raw_readl(offset) 41 # define xgpio_writereg(offset, val) __raw_writel(val, offset) 42 #endif 43 44 /** 45 * struct xgpio_instance - Stores information about GPIO device 46 * @gc: GPIO chip 47 * @regs: register block 48 * @map: GPIO pin mapping on hardware side 49 * @state: GPIO write state shadow register 50 * @last_irq_read: GPIO read state register from last interrupt 51 * @dir: GPIO direction shadow register 52 * @gpio_lock: Lock used for synchronization 53 * @irq: IRQ used by GPIO device 54 * @enable: GPIO IRQ enable/disable bitfield 55 * @rising_edge: GPIO IRQ rising edge enable/disable bitfield 56 * @falling_edge: GPIO IRQ falling edge enable/disable bitfield 57 * @clk: clock resource for this driver 58 */ 59 struct xgpio_instance { 60 struct gpio_chip gc; 61 void __iomem *regs; 62 DECLARE_BITMAP(map, 64); 63 DECLARE_BITMAP(state, 64); 64 DECLARE_BITMAP(last_irq_read, 64); 65 DECLARE_BITMAP(dir, 64); 66 raw_spinlock_t gpio_lock; /* For serializing operations */ 67 int irq; 68 DECLARE_BITMAP(enable, 64); 69 DECLARE_BITMAP(rising_edge, 64); 70 DECLARE_BITMAP(falling_edge, 64); 71 struct clk *clk; 72 }; 73 74 static inline int xgpio_regoffset(struct xgpio_instance *chip, int ch) 75 { 76 switch (ch) { 77 case 0: 78 return XGPIO_CHANNEL0_OFFSET; 79 case 1: 80 return XGPIO_CHANNEL1_OFFSET; 81 default: 82 return -EINVAL; 83 } 84 } 85 86 static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 87 { 88 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 89 unsigned long value = xgpio_readreg(addr); 90 91 bitmap_write(a, value, round_down(bit, 32), 32); 92 } 93 94 static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a) 95 { 96 void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32); 97 unsigned long value = bitmap_read(a, round_down(bit, 32), 32); 98 99 xgpio_writereg(addr, value); 100 } 101 102 static void xgpio_read_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 103 { 104 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 105 int bit; 106 107 for (bit = 0; bit <= lastbit ; bit += 32) 108 xgpio_read_ch(chip, reg, bit, a); 109 } 110 111 static void xgpio_write_ch_all(struct xgpio_instance *chip, int reg, unsigned long *a) 112 { 113 unsigned long lastbit = find_nth_bit(chip->map, 64, chip->gc.ngpio - 1); 114 int bit; 115 116 for (bit = 0; bit <= lastbit ; bit += 32) 117 xgpio_write_ch(chip, reg, bit, a); 118 } 119 120 /** 121 * xgpio_get - Read the specified signal of the GPIO device. 122 * @gc: Pointer to gpio_chip device structure. 123 * @gpio: GPIO signal number. 124 * 125 * This function reads the specified signal of the GPIO device. 126 * 127 * Return: 128 * 0 if direction of GPIO signals is set as input otherwise it 129 * returns negative error value. 130 */ 131 static int xgpio_get(struct gpio_chip *gc, unsigned int gpio) 132 { 133 struct xgpio_instance *chip = gpiochip_get_data(gc); 134 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 135 DECLARE_BITMAP(state, 64); 136 137 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, state); 138 139 return test_bit(bit, state); 140 } 141 142 /** 143 * xgpio_set - Write the specified signal of the GPIO device. 144 * @gc: Pointer to gpio_chip device structure. 145 * @gpio: GPIO signal number. 146 * @val: Value to be written to specified signal. 147 * 148 * This function writes the specified value in to the specified signal of the 149 * GPIO device. 150 */ 151 static int xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 152 { 153 unsigned long flags; 154 struct xgpio_instance *chip = gpiochip_get_data(gc); 155 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 156 157 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 158 159 /* Write to GPIO signal and set its direction to output */ 160 __assign_bit(bit, chip->state, val); 161 162 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 163 164 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 165 166 return 0; 167 } 168 169 /** 170 * xgpio_set_multiple - Write the specified signals of the GPIO device. 171 * @gc: Pointer to gpio_chip device structure. 172 * @mask: Mask of the GPIOS to modify. 173 * @bits: Value to be wrote on each GPIO 174 * 175 * This function writes the specified values into the specified signals of the 176 * GPIO devices. 177 */ 178 static int xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 179 unsigned long *bits) 180 { 181 DECLARE_BITMAP(hw_mask, 64); 182 DECLARE_BITMAP(hw_bits, 64); 183 DECLARE_BITMAP(state, 64); 184 unsigned long flags; 185 struct xgpio_instance *chip = gpiochip_get_data(gc); 186 187 bitmap_scatter(hw_mask, mask, chip->map, 64); 188 bitmap_scatter(hw_bits, bits, chip->map, 64); 189 190 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 191 192 bitmap_replace(state, chip->state, hw_bits, hw_mask, 64); 193 194 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, state); 195 196 bitmap_copy(chip->state, state, 64); 197 198 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 199 200 return 0; 201 } 202 203 /** 204 * xgpio_dir_in - Set the direction of the specified GPIO signal as input. 205 * @gc: Pointer to gpio_chip device structure. 206 * @gpio: GPIO signal number. 207 * 208 * Return: 209 * 0 - if direction of GPIO signals is set as input 210 * otherwise it returns negative error value. 211 */ 212 static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 213 { 214 unsigned long flags; 215 struct xgpio_instance *chip = gpiochip_get_data(gc); 216 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 217 218 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 219 220 /* Set the GPIO bit in shadow register and set direction as input */ 221 __set_bit(bit, chip->dir); 222 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 223 224 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 225 226 return 0; 227 } 228 229 /** 230 * xgpio_dir_out - Set the direction of the specified GPIO signal as output. 231 * @gc: Pointer to gpio_chip device structure. 232 * @gpio: GPIO signal number. 233 * @val: Value to be written to specified signal. 234 * 235 * This function sets the direction of specified GPIO signal as output. 236 * 237 * Return: 238 * If all GPIO signals of GPIO chip is configured as input then it returns 239 * error otherwise it returns 0. 240 */ 241 static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 242 { 243 unsigned long flags; 244 struct xgpio_instance *chip = gpiochip_get_data(gc); 245 unsigned long bit = find_nth_bit(chip->map, 64, gpio); 246 247 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 248 249 /* Write state of GPIO signal */ 250 __assign_bit(bit, chip->state, val); 251 xgpio_write_ch(chip, XGPIO_DATA_OFFSET, bit, chip->state); 252 253 /* Clear the GPIO bit in shadow register and set direction as output */ 254 __clear_bit(bit, chip->dir); 255 xgpio_write_ch(chip, XGPIO_TRI_OFFSET, bit, chip->dir); 256 257 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 258 259 return 0; 260 } 261 262 /** 263 * xgpio_save_regs - Set initial values of GPIO pins 264 * @chip: Pointer to GPIO instance 265 */ 266 static void xgpio_save_regs(struct xgpio_instance *chip) 267 { 268 xgpio_write_ch_all(chip, XGPIO_DATA_OFFSET, chip->state); 269 xgpio_write_ch_all(chip, XGPIO_TRI_OFFSET, chip->dir); 270 } 271 272 static int xgpio_request(struct gpio_chip *chip, unsigned int offset) 273 { 274 return pm_runtime_resume_and_get(chip->parent); 275 } 276 277 static void xgpio_free(struct gpio_chip *chip, unsigned int offset) 278 { 279 pm_runtime_put(chip->parent); 280 } 281 282 static int xgpio_suspend(struct device *dev) 283 { 284 struct xgpio_instance *gpio = dev_get_drvdata(dev); 285 struct irq_data *data = irq_get_irq_data(gpio->irq); 286 287 if (!data) { 288 dev_dbg(dev, "IRQ not connected\n"); 289 return pm_runtime_force_suspend(dev); 290 } 291 292 if (!irqd_is_wakeup_set(data)) 293 return pm_runtime_force_suspend(dev); 294 295 return 0; 296 } 297 298 /** 299 * xgpio_remove - Remove method for the GPIO device. 300 * @pdev: pointer to the platform device 301 * 302 * This function remove gpiochips and frees all the allocated resources. 303 * 304 * Return: 0 always 305 */ 306 static void xgpio_remove(struct platform_device *pdev) 307 { 308 pm_runtime_get_sync(&pdev->dev); 309 pm_runtime_put_noidle(&pdev->dev); 310 pm_runtime_disable(&pdev->dev); 311 } 312 313 /** 314 * xgpio_irq_ack - Acknowledge a child GPIO interrupt. 315 * @irq_data: per IRQ and chip data passed down to chip functions 316 * This currently does nothing, but irq_ack is unconditionally called by 317 * handle_edge_irq and therefore must be defined. 318 */ 319 static void xgpio_irq_ack(struct irq_data *irq_data) 320 { 321 } 322 323 static int xgpio_resume(struct device *dev) 324 { 325 struct xgpio_instance *gpio = dev_get_drvdata(dev); 326 struct irq_data *data = irq_get_irq_data(gpio->irq); 327 328 if (!data) { 329 dev_dbg(dev, "IRQ not connected\n"); 330 return pm_runtime_force_resume(dev); 331 } 332 333 if (!irqd_is_wakeup_set(data)) 334 return pm_runtime_force_resume(dev); 335 336 return 0; 337 } 338 339 static int xgpio_runtime_suspend(struct device *dev) 340 { 341 struct xgpio_instance *gpio = dev_get_drvdata(dev); 342 343 clk_disable(gpio->clk); 344 345 return 0; 346 } 347 348 static int xgpio_runtime_resume(struct device *dev) 349 { 350 struct xgpio_instance *gpio = dev_get_drvdata(dev); 351 352 return clk_enable(gpio->clk); 353 } 354 355 static const struct dev_pm_ops xgpio_dev_pm_ops = { 356 SYSTEM_SLEEP_PM_OPS(xgpio_suspend, xgpio_resume) 357 RUNTIME_PM_OPS(xgpio_runtime_suspend, xgpio_runtime_resume, NULL) 358 }; 359 360 /** 361 * xgpio_irq_mask - Write the specified signal of the GPIO device. 362 * @irq_data: per IRQ and chip data passed down to chip functions 363 */ 364 static void xgpio_irq_mask(struct irq_data *irq_data) 365 { 366 unsigned long flags; 367 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 368 int irq_offset = irqd_to_hwirq(irq_data); 369 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 370 u32 mask = BIT(bit / 32), temp; 371 372 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 373 374 __clear_bit(bit, chip->enable); 375 376 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 377 if (enable == 0) { 378 /* Disable per channel interrupt */ 379 temp = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 380 temp &= ~mask; 381 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, temp); 382 } 383 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 384 385 gpiochip_disable_irq(&chip->gc, irq_offset); 386 } 387 388 /** 389 * xgpio_irq_unmask - Write the specified signal of the GPIO device. 390 * @irq_data: per IRQ and chip data passed down to chip functions 391 */ 392 static void xgpio_irq_unmask(struct irq_data *irq_data) 393 { 394 unsigned long flags; 395 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 396 int irq_offset = irqd_to_hwirq(irq_data); 397 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset), enable; 398 u32 mask = BIT(bit / 32), val; 399 400 gpiochip_enable_irq(&chip->gc, irq_offset); 401 402 raw_spin_lock_irqsave(&chip->gpio_lock, flags); 403 404 enable = bitmap_read(chip->enable, round_down(bit, 32), 32); 405 if (enable == 0) { 406 /* Clear any existing per-channel interrupts */ 407 val = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 408 val &= mask; 409 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, val); 410 411 /* Update GPIO IRQ read data before enabling interrupt*/ 412 xgpio_read_ch(chip, XGPIO_DATA_OFFSET, bit, chip->last_irq_read); 413 414 /* Enable per channel interrupt */ 415 val = xgpio_readreg(chip->regs + XGPIO_IPIER_OFFSET); 416 val |= mask; 417 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, val); 418 } 419 420 __set_bit(bit, chip->enable); 421 422 raw_spin_unlock_irqrestore(&chip->gpio_lock, flags); 423 } 424 425 /** 426 * xgpio_set_irq_type - Write the specified signal of the GPIO device. 427 * @irq_data: Per IRQ and chip data passed down to chip functions 428 * @type: Interrupt type that is to be set for the gpio pin 429 * 430 * Return: 431 * 0 if interrupt type is supported otherwise -EINVAL 432 */ 433 static int xgpio_set_irq_type(struct irq_data *irq_data, unsigned int type) 434 { 435 struct xgpio_instance *chip = irq_data_get_irq_chip_data(irq_data); 436 int irq_offset = irqd_to_hwirq(irq_data); 437 unsigned long bit = find_nth_bit(chip->map, 64, irq_offset); 438 439 /* 440 * The Xilinx GPIO hardware provides a single interrupt status 441 * indication for any state change in a given GPIO channel (bank). 442 * Therefore, only rising edge or falling edge triggers are 443 * supported. 444 */ 445 switch (type & IRQ_TYPE_SENSE_MASK) { 446 case IRQ_TYPE_EDGE_BOTH: 447 __set_bit(bit, chip->rising_edge); 448 __set_bit(bit, chip->falling_edge); 449 break; 450 case IRQ_TYPE_EDGE_RISING: 451 __set_bit(bit, chip->rising_edge); 452 __clear_bit(bit, chip->falling_edge); 453 break; 454 case IRQ_TYPE_EDGE_FALLING: 455 __clear_bit(bit, chip->rising_edge); 456 __set_bit(bit, chip->falling_edge); 457 break; 458 default: 459 return -EINVAL; 460 } 461 462 irq_set_handler_locked(irq_data, handle_edge_irq); 463 return 0; 464 } 465 466 /** 467 * xgpio_irqhandler - Gpio interrupt service routine 468 * @desc: Pointer to interrupt description 469 */ 470 static void xgpio_irqhandler(struct irq_desc *desc) 471 { 472 struct xgpio_instance *chip = irq_desc_get_handler_data(desc); 473 struct gpio_chip *gc = &chip->gc; 474 struct irq_chip *irqchip = irq_desc_get_chip(desc); 475 DECLARE_BITMAP(rising, 64); 476 DECLARE_BITMAP(falling, 64); 477 DECLARE_BITMAP(hw, 64); 478 DECLARE_BITMAP(sw, 64); 479 int irq_offset; 480 u32 status; 481 482 status = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 483 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, status); 484 485 chained_irq_enter(irqchip, desc); 486 487 raw_spin_lock(&chip->gpio_lock); 488 489 xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw); 490 491 bitmap_andnot(rising, hw, chip->last_irq_read, 64); 492 bitmap_and(rising, rising, chip->enable, 64); 493 bitmap_and(rising, rising, chip->rising_edge, 64); 494 495 bitmap_andnot(falling, chip->last_irq_read, hw, 64); 496 bitmap_and(falling, falling, chip->enable, 64); 497 bitmap_and(falling, falling, chip->falling_edge, 64); 498 499 bitmap_copy(chip->last_irq_read, hw, 64); 500 bitmap_or(hw, rising, falling, 64); 501 502 raw_spin_unlock(&chip->gpio_lock); 503 504 dev_dbg(gc->parent, "IRQ rising %*pb falling %*pb\n", 64, rising, 64, falling); 505 506 bitmap_gather(sw, hw, chip->map, 64); 507 for_each_set_bit(irq_offset, sw, 64) 508 generic_handle_domain_irq(gc->irq.domain, irq_offset); 509 510 chained_irq_exit(irqchip, desc); 511 } 512 513 static const struct irq_chip xgpio_irq_chip = { 514 .name = "gpio-xilinx", 515 .irq_ack = xgpio_irq_ack, 516 .irq_mask = xgpio_irq_mask, 517 .irq_unmask = xgpio_irq_unmask, 518 .irq_set_type = xgpio_set_irq_type, 519 .flags = IRQCHIP_IMMUTABLE, 520 GPIOCHIP_IRQ_RESOURCE_HELPERS, 521 }; 522 523 /** 524 * xgpio_probe - Probe method for the GPIO device. 525 * @pdev: pointer to the platform device 526 * 527 * Return: 528 * It returns 0, if the driver is bound to the GPIO device, or 529 * a negative value if there is an error. 530 */ 531 static int xgpio_probe(struct platform_device *pdev) 532 { 533 struct device *dev = &pdev->dev; 534 struct xgpio_instance *chip; 535 int status = 0; 536 u32 is_dual = 0; 537 u32 width[2]; 538 u32 state[2]; 539 u32 dir[2]; 540 struct gpio_irq_chip *girq; 541 u32 temp; 542 543 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 544 if (!chip) 545 return -ENOMEM; 546 547 platform_set_drvdata(pdev, chip); 548 549 /* First, check if the device is dual-channel */ 550 device_property_read_u32(dev, "xlnx,is-dual", &is_dual); 551 552 /* Setup defaults */ 553 memset32(width, 0, ARRAY_SIZE(width)); 554 memset32(state, 0, ARRAY_SIZE(state)); 555 memset32(dir, 0xFFFFFFFF, ARRAY_SIZE(dir)); 556 557 /* Update GPIO state shadow register with default value */ 558 device_property_read_u32(dev, "xlnx,dout-default", &state[0]); 559 device_property_read_u32(dev, "xlnx,dout-default-2", &state[1]); 560 561 bitmap_from_arr32(chip->state, state, 64); 562 563 /* Update GPIO direction shadow register with default value */ 564 device_property_read_u32(dev, "xlnx,tri-default", &dir[0]); 565 device_property_read_u32(dev, "xlnx,tri-default-2", &dir[1]); 566 567 bitmap_from_arr32(chip->dir, dir, 64); 568 569 /* 570 * Check device node and parent device node for device width 571 * and assume default width of 32 572 */ 573 if (device_property_read_u32(dev, "xlnx,gpio-width", &width[0])) 574 width[0] = 32; 575 576 if (width[0] > 32) 577 return -EINVAL; 578 579 if (is_dual && device_property_read_u32(dev, "xlnx,gpio2-width", &width[1])) 580 width[1] = 32; 581 582 if (width[1] > 32) 583 return -EINVAL; 584 585 /* Setup hardware pin mapping */ 586 bitmap_set(chip->map, 0, width[0]); 587 bitmap_set(chip->map, 32, width[1]); 588 589 raw_spin_lock_init(&chip->gpio_lock); 590 591 chip->gc.base = -1; 592 chip->gc.ngpio = bitmap_weight(chip->map, 64); 593 chip->gc.parent = dev; 594 chip->gc.direction_input = xgpio_dir_in; 595 chip->gc.direction_output = xgpio_dir_out; 596 chip->gc.get = xgpio_get; 597 chip->gc.set = xgpio_set; 598 chip->gc.request = xgpio_request; 599 chip->gc.free = xgpio_free; 600 chip->gc.set_multiple = xgpio_set_multiple; 601 602 chip->gc.label = dev_name(dev); 603 604 chip->regs = devm_platform_ioremap_resource(pdev, 0); 605 if (IS_ERR(chip->regs)) { 606 dev_err(dev, "failed to ioremap memory resource\n"); 607 return PTR_ERR(chip->regs); 608 } 609 610 chip->clk = devm_clk_get_optional_enabled(dev, NULL); 611 if (IS_ERR(chip->clk)) 612 return dev_err_probe(dev, PTR_ERR(chip->clk), "input clock not found.\n"); 613 614 pm_runtime_get_noresume(dev); 615 pm_runtime_set_active(dev); 616 pm_runtime_enable(dev); 617 618 xgpio_save_regs(chip); 619 620 chip->irq = platform_get_irq_optional(pdev, 0); 621 if (chip->irq <= 0) 622 goto skip_irq; 623 624 /* Disable per-channel interrupts */ 625 xgpio_writereg(chip->regs + XGPIO_IPIER_OFFSET, 0); 626 /* Clear any existing per-channel interrupts */ 627 temp = xgpio_readreg(chip->regs + XGPIO_IPISR_OFFSET); 628 xgpio_writereg(chip->regs + XGPIO_IPISR_OFFSET, temp); 629 /* Enable global interrupts */ 630 xgpio_writereg(chip->regs + XGPIO_GIER_OFFSET, XGPIO_GIER_IE); 631 632 girq = &chip->gc.irq; 633 gpio_irq_chip_set_chip(girq, &xgpio_irq_chip); 634 girq->parent_handler = xgpio_irqhandler; 635 girq->num_parents = 1; 636 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 637 GFP_KERNEL); 638 if (!girq->parents) { 639 status = -ENOMEM; 640 goto err_pm_put; 641 } 642 girq->parents[0] = chip->irq; 643 girq->default_type = IRQ_TYPE_NONE; 644 girq->handler = handle_bad_irq; 645 646 skip_irq: 647 status = devm_gpiochip_add_data(dev, &chip->gc, chip); 648 if (status) { 649 dev_err(dev, "failed to add GPIO chip\n"); 650 goto err_pm_put; 651 } 652 653 pm_runtime_put(dev); 654 return 0; 655 656 err_pm_put: 657 pm_runtime_disable(dev); 658 pm_runtime_put_noidle(dev); 659 return status; 660 } 661 662 static const struct of_device_id xgpio_of_match[] = { 663 { .compatible = "xlnx,xps-gpio-1.00.a", }, 664 { /* end of list */ }, 665 }; 666 667 MODULE_DEVICE_TABLE(of, xgpio_of_match); 668 669 static struct platform_driver xgpio_plat_driver = { 670 .probe = xgpio_probe, 671 .remove = xgpio_remove, 672 .driver = { 673 .name = "gpio-xilinx", 674 .of_match_table = xgpio_of_match, 675 .pm = pm_ptr(&xgpio_dev_pm_ops), 676 }, 677 }; 678 679 static int __init xgpio_init(void) 680 { 681 return platform_driver_register(&xgpio_plat_driver); 682 } 683 684 subsys_initcall(xgpio_init); 685 686 static void __exit xgpio_exit(void) 687 { 688 platform_driver_unregister(&xgpio_plat_driver); 689 } 690 module_exit(xgpio_exit); 691 692 MODULE_AUTHOR("Xilinx, Inc."); 693 MODULE_DESCRIPTION("Xilinx GPIO driver"); 694 MODULE_LICENSE("GPL"); 695