1 /* 2 * AppliedMicro X-Gene SoC GPIO Driver 3 * 4 * Copyright (c) 2014, Applied Micro Circuits Corporation 5 * Author: Feng Kan <fkan@apm.com>. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include <linux/acpi.h> 21 #include <linux/kernel.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/spinlock.h> 25 #include <linux/platform_device.h> 26 #include <linux/gpio/driver.h> 27 #include <linux/types.h> 28 #include <linux/bitops.h> 29 30 #define GPIO_SET_DR_OFFSET 0x0C 31 #define GPIO_DATA_OFFSET 0x14 32 #define GPIO_BANK_STRIDE 0x0C 33 34 #define XGENE_GPIOS_PER_BANK 16 35 #define XGENE_MAX_GPIO_BANKS 3 36 #define XGENE_MAX_GPIOS (XGENE_GPIOS_PER_BANK * XGENE_MAX_GPIO_BANKS) 37 38 #define GPIO_BIT_OFFSET(x) (x % XGENE_GPIOS_PER_BANK) 39 #define GPIO_BANK_OFFSET(x) ((x / XGENE_GPIOS_PER_BANK) * GPIO_BANK_STRIDE) 40 41 struct xgene_gpio { 42 struct gpio_chip chip; 43 void __iomem *base; 44 spinlock_t lock; 45 #ifdef CONFIG_PM 46 u32 set_dr_val[XGENE_MAX_GPIO_BANKS]; 47 #endif 48 }; 49 50 static int xgene_gpio_get(struct gpio_chip *gc, unsigned int offset) 51 { 52 struct xgene_gpio *chip = gpiochip_get_data(gc); 53 unsigned long bank_offset; 54 u32 bit_offset; 55 56 bank_offset = GPIO_DATA_OFFSET + GPIO_BANK_OFFSET(offset); 57 bit_offset = GPIO_BIT_OFFSET(offset); 58 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); 59 } 60 61 static void __xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 62 { 63 struct xgene_gpio *chip = gpiochip_get_data(gc); 64 unsigned long bank_offset; 65 u32 setval, bit_offset; 66 67 bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset); 68 bit_offset = GPIO_BIT_OFFSET(offset) + XGENE_GPIOS_PER_BANK; 69 70 setval = ioread32(chip->base + bank_offset); 71 if (val) 72 setval |= BIT(bit_offset); 73 else 74 setval &= ~BIT(bit_offset); 75 iowrite32(setval, chip->base + bank_offset); 76 } 77 78 static void xgene_gpio_set(struct gpio_chip *gc, unsigned int offset, int val) 79 { 80 struct xgene_gpio *chip = gpiochip_get_data(gc); 81 unsigned long flags; 82 83 spin_lock_irqsave(&chip->lock, flags); 84 __xgene_gpio_set(gc, offset, val); 85 spin_unlock_irqrestore(&chip->lock, flags); 86 } 87 88 static int xgene_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 89 { 90 struct xgene_gpio *chip = gpiochip_get_data(gc); 91 unsigned long bank_offset, bit_offset; 92 93 bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset); 94 bit_offset = GPIO_BIT_OFFSET(offset); 95 96 return !!(ioread32(chip->base + bank_offset) & BIT(bit_offset)); 97 } 98 99 static int xgene_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 100 { 101 struct xgene_gpio *chip = gpiochip_get_data(gc); 102 unsigned long flags, bank_offset; 103 u32 dirval, bit_offset; 104 105 bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset); 106 bit_offset = GPIO_BIT_OFFSET(offset); 107 108 spin_lock_irqsave(&chip->lock, flags); 109 110 dirval = ioread32(chip->base + bank_offset); 111 dirval |= BIT(bit_offset); 112 iowrite32(dirval, chip->base + bank_offset); 113 114 spin_unlock_irqrestore(&chip->lock, flags); 115 116 return 0; 117 } 118 119 static int xgene_gpio_dir_out(struct gpio_chip *gc, 120 unsigned int offset, int val) 121 { 122 struct xgene_gpio *chip = gpiochip_get_data(gc); 123 unsigned long flags, bank_offset; 124 u32 dirval, bit_offset; 125 126 bank_offset = GPIO_SET_DR_OFFSET + GPIO_BANK_OFFSET(offset); 127 bit_offset = GPIO_BIT_OFFSET(offset); 128 129 spin_lock_irqsave(&chip->lock, flags); 130 131 dirval = ioread32(chip->base + bank_offset); 132 dirval &= ~BIT(bit_offset); 133 iowrite32(dirval, chip->base + bank_offset); 134 __xgene_gpio_set(gc, offset, val); 135 136 spin_unlock_irqrestore(&chip->lock, flags); 137 138 return 0; 139 } 140 141 #ifdef CONFIG_PM 142 static int xgene_gpio_suspend(struct device *dev) 143 { 144 struct xgene_gpio *gpio = dev_get_drvdata(dev); 145 unsigned long bank_offset; 146 unsigned int bank; 147 148 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) { 149 bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE; 150 gpio->set_dr_val[bank] = ioread32(gpio->base + bank_offset); 151 } 152 return 0; 153 } 154 155 static int xgene_gpio_resume(struct device *dev) 156 { 157 struct xgene_gpio *gpio = dev_get_drvdata(dev); 158 unsigned long bank_offset; 159 unsigned int bank; 160 161 for (bank = 0; bank < XGENE_MAX_GPIO_BANKS; bank++) { 162 bank_offset = GPIO_SET_DR_OFFSET + bank * GPIO_BANK_STRIDE; 163 iowrite32(gpio->set_dr_val[bank], gpio->base + bank_offset); 164 } 165 return 0; 166 } 167 168 static SIMPLE_DEV_PM_OPS(xgene_gpio_pm, xgene_gpio_suspend, xgene_gpio_resume); 169 #define XGENE_GPIO_PM_OPS (&xgene_gpio_pm) 170 #else 171 #define XGENE_GPIO_PM_OPS NULL 172 #endif 173 174 static int xgene_gpio_probe(struct platform_device *pdev) 175 { 176 struct resource *res; 177 struct xgene_gpio *gpio; 178 int err = 0; 179 180 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 181 if (!gpio) { 182 err = -ENOMEM; 183 goto err; 184 } 185 186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 187 if (!res) { 188 err = -EINVAL; 189 goto err; 190 } 191 192 gpio->base = devm_ioremap_nocache(&pdev->dev, res->start, 193 resource_size(res)); 194 if (!gpio->base) { 195 err = -ENOMEM; 196 goto err; 197 } 198 199 gpio->chip.ngpio = XGENE_MAX_GPIOS; 200 201 spin_lock_init(&gpio->lock); 202 gpio->chip.parent = &pdev->dev; 203 gpio->chip.get_direction = xgene_gpio_get_direction; 204 gpio->chip.direction_input = xgene_gpio_dir_in; 205 gpio->chip.direction_output = xgene_gpio_dir_out; 206 gpio->chip.get = xgene_gpio_get; 207 gpio->chip.set = xgene_gpio_set; 208 gpio->chip.label = dev_name(&pdev->dev); 209 gpio->chip.base = -1; 210 211 platform_set_drvdata(pdev, gpio); 212 213 err = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 214 if (err) { 215 dev_err(&pdev->dev, 216 "failed to register gpiochip.\n"); 217 goto err; 218 } 219 220 dev_info(&pdev->dev, "X-Gene GPIO driver registered.\n"); 221 return 0; 222 err: 223 dev_err(&pdev->dev, "X-Gene GPIO driver registration failed.\n"); 224 return err; 225 } 226 227 static const struct of_device_id xgene_gpio_of_match[] = { 228 { .compatible = "apm,xgene-gpio", }, 229 {}, 230 }; 231 232 #ifdef CONFIG_ACPI 233 static const struct acpi_device_id xgene_gpio_acpi_match[] = { 234 { "APMC0D14", 0 }, 235 { }, 236 }; 237 #endif 238 239 static struct platform_driver xgene_gpio_driver = { 240 .driver = { 241 .name = "xgene-gpio", 242 .of_match_table = xgene_gpio_of_match, 243 .acpi_match_table = ACPI_PTR(xgene_gpio_acpi_match), 244 .pm = XGENE_GPIO_PM_OPS, 245 }, 246 .probe = xgene_gpio_probe, 247 }; 248 builtin_platform_driver(xgene_gpio_driver); 249