1 /* 2 * AppliedMicro X-Gene SoC GPIO-Standby Driver 3 * 4 * Copyright (c) 2014, Applied Micro Circuits Corporation 5 * Author: Tin Huynh <tnhuynh@apm.com>. 6 * Y Vo <yvo@apm.com>. 7 * Quan Nguyen <qnguyen@apm.com>. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/io.h> 25 #include <linux/platform_device.h> 26 #include <linux/of_gpio.h> 27 #include <linux/gpio/driver.h> 28 #include <linux/acpi.h> 29 30 #include "gpiolib.h" 31 32 /* Common property names */ 33 #define XGENE_NIRQ_PROPERTY "apm,nr-irqs" 34 #define XGENE_NGPIO_PROPERTY "apm,nr-gpios" 35 #define XGENE_IRQ_START_PROPERTY "apm,irq-start" 36 37 #define XGENE_DFLT_MAX_NGPIO 22 38 #define XGENE_DFLT_MAX_NIRQ 6 39 #define XGENE_DFLT_IRQ_START_PIN 8 40 #define GPIO_MASK(x) (1U << ((x) % 32)) 41 42 #define MPA_GPIO_INT_LVL 0x0290 43 #define MPA_GPIO_OE_ADDR 0x029c 44 #define MPA_GPIO_OUT_ADDR 0x02a0 45 #define MPA_GPIO_IN_ADDR 0x02a4 46 #define MPA_GPIO_SEL_LO 0x0294 47 48 #define GPIO_INT_LEVEL_H 0x000001 49 #define GPIO_INT_LEVEL_L 0x000000 50 51 /** 52 * struct xgene_gpio_sb - GPIO-Standby private data structure. 53 * @gc: memory-mapped GPIO controllers. 54 * @regs: GPIO register base offset 55 * @irq_domain: GPIO interrupt domain 56 * @irq_start: GPIO pin that start support interrupt 57 * @nirq: Number of GPIO pins that supports interrupt 58 * @parent_irq_base: Start parent HWIRQ 59 */ 60 struct xgene_gpio_sb { 61 struct gpio_chip gc; 62 void __iomem *regs; 63 struct irq_domain *irq_domain; 64 u16 irq_start; 65 u16 nirq; 66 u16 parent_irq_base; 67 }; 68 69 #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start) 70 #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start) 71 72 static void xgene_gpio_set_bit(struct gpio_chip *gc, 73 void __iomem *reg, u32 gpio, int val) 74 { 75 u32 data; 76 77 data = gc->read_reg(reg); 78 if (val) 79 data |= GPIO_MASK(gpio); 80 else 81 data &= ~GPIO_MASK(gpio); 82 gc->write_reg(reg, data); 83 } 84 85 static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type) 86 { 87 struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d); 88 int gpio = HWIRQ_TO_GPIO(priv, d->hwirq); 89 int lvl_type = GPIO_INT_LEVEL_H; 90 91 switch (type & IRQ_TYPE_SENSE_MASK) { 92 case IRQ_TYPE_EDGE_RISING: 93 case IRQ_TYPE_LEVEL_HIGH: 94 lvl_type = GPIO_INT_LEVEL_H; 95 break; 96 case IRQ_TYPE_EDGE_FALLING: 97 case IRQ_TYPE_LEVEL_LOW: 98 lvl_type = GPIO_INT_LEVEL_L; 99 break; 100 default: 101 break; 102 } 103 104 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 105 gpio * 2, 1); 106 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL, 107 d->hwirq, lvl_type); 108 109 /* Propagate IRQ type setting to parent */ 110 if (type & IRQ_TYPE_EDGE_BOTH) 111 return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING); 112 else 113 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 114 } 115 116 static struct irq_chip xgene_gpio_sb_irq_chip = { 117 .name = "sbgpio", 118 .irq_eoi = irq_chip_eoi_parent, 119 .irq_mask = irq_chip_mask_parent, 120 .irq_unmask = irq_chip_unmask_parent, 121 .irq_set_type = xgene_gpio_sb_irq_set_type, 122 }; 123 124 static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio) 125 { 126 struct xgene_gpio_sb *priv = gpiochip_get_data(gc); 127 struct irq_fwspec fwspec; 128 129 if ((gpio < priv->irq_start) || 130 (gpio > HWIRQ_TO_GPIO(priv, priv->nirq))) 131 return -ENXIO; 132 133 if (gc->parent->of_node) 134 fwspec.fwnode = of_node_to_fwnode(gc->parent->of_node); 135 else 136 fwspec.fwnode = gc->parent->fwnode; 137 fwspec.param_count = 2; 138 fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio); 139 fwspec.param[1] = IRQ_TYPE_NONE; 140 return irq_create_fwspec_mapping(&fwspec); 141 } 142 143 static void xgene_gpio_sb_domain_activate(struct irq_domain *d, 144 struct irq_data *irq_data) 145 { 146 struct xgene_gpio_sb *priv = d->host_data; 147 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); 148 149 if (gpiochip_lock_as_irq(&priv->gc, gpio)) { 150 dev_err(priv->gc.parent, 151 "Unable to configure XGene GPIO standby pin %d as IRQ\n", 152 gpio); 153 return; 154 } 155 156 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 157 gpio * 2, 1); 158 } 159 160 static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d, 161 struct irq_data *irq_data) 162 { 163 struct xgene_gpio_sb *priv = d->host_data; 164 u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq); 165 166 gpiochip_unlock_as_irq(&priv->gc, gpio); 167 xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO, 168 gpio * 2, 0); 169 } 170 171 static int xgene_gpio_sb_domain_translate(struct irq_domain *d, 172 struct irq_fwspec *fwspec, 173 unsigned long *hwirq, 174 unsigned int *type) 175 { 176 struct xgene_gpio_sb *priv = d->host_data; 177 178 if ((fwspec->param_count != 2) || 179 (fwspec->param[0] >= priv->nirq)) 180 return -EINVAL; 181 *hwirq = fwspec->param[0]; 182 *type = fwspec->param[1]; 183 return 0; 184 } 185 186 static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain, 187 unsigned int virq, 188 unsigned int nr_irqs, void *data) 189 { 190 struct irq_fwspec *fwspec = data; 191 struct irq_fwspec parent_fwspec; 192 struct xgene_gpio_sb *priv = domain->host_data; 193 irq_hw_number_t hwirq; 194 unsigned int i; 195 196 hwirq = fwspec->param[0]; 197 for (i = 0; i < nr_irqs; i++) 198 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 199 &xgene_gpio_sb_irq_chip, priv); 200 201 parent_fwspec.fwnode = domain->parent->fwnode; 202 if (is_of_node(parent_fwspec.fwnode)) { 203 parent_fwspec.param_count = 3; 204 parent_fwspec.param[0] = 0;/* SPI */ 205 /* Skip SGIs and PPIs*/ 206 parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32; 207 parent_fwspec.param[2] = fwspec->param[1]; 208 } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) { 209 parent_fwspec.param_count = 2; 210 parent_fwspec.param[0] = hwirq + priv->parent_irq_base; 211 parent_fwspec.param[1] = fwspec->param[1]; 212 } else 213 return -EINVAL; 214 215 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 216 &parent_fwspec); 217 } 218 219 static void xgene_gpio_sb_domain_free(struct irq_domain *domain, 220 unsigned int virq, 221 unsigned int nr_irqs) 222 { 223 struct irq_data *d; 224 unsigned int i; 225 226 for (i = 0; i < nr_irqs; i++) { 227 d = irq_domain_get_irq_data(domain, virq + i); 228 irq_domain_reset_irq_data(d); 229 } 230 } 231 232 static const struct irq_domain_ops xgene_gpio_sb_domain_ops = { 233 .translate = xgene_gpio_sb_domain_translate, 234 .alloc = xgene_gpio_sb_domain_alloc, 235 .free = xgene_gpio_sb_domain_free, 236 .activate = xgene_gpio_sb_domain_activate, 237 .deactivate = xgene_gpio_sb_domain_deactivate, 238 }; 239 240 static int xgene_gpio_sb_probe(struct platform_device *pdev) 241 { 242 struct xgene_gpio_sb *priv; 243 int ret; 244 struct resource *res; 245 void __iomem *regs; 246 struct irq_domain *parent_domain = NULL; 247 struct fwnode_handle *fwnode; 248 u32 val32; 249 250 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 251 if (!priv) 252 return -ENOMEM; 253 254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 255 regs = devm_ioremap_resource(&pdev->dev, res); 256 if (IS_ERR(regs)) 257 return PTR_ERR(regs); 258 259 priv->regs = regs; 260 261 ret = platform_get_irq(pdev, 0); 262 if (ret > 0) { 263 priv->parent_irq_base = irq_get_irq_data(ret)->hwirq; 264 parent_domain = irq_get_irq_data(ret)->domain; 265 } 266 if (!parent_domain) { 267 dev_err(&pdev->dev, "unable to obtain parent domain\n"); 268 return -ENODEV; 269 } 270 271 ret = bgpio_init(&priv->gc, &pdev->dev, 4, 272 regs + MPA_GPIO_IN_ADDR, 273 regs + MPA_GPIO_OUT_ADDR, NULL, 274 regs + MPA_GPIO_OE_ADDR, NULL, 0); 275 if (ret) 276 return ret; 277 278 priv->gc.to_irq = xgene_gpio_sb_to_irq; 279 280 /* Retrieve start irq pin, use default if property not found */ 281 priv->irq_start = XGENE_DFLT_IRQ_START_PIN; 282 if (!device_property_read_u32(&pdev->dev, 283 XGENE_IRQ_START_PROPERTY, &val32)) 284 priv->irq_start = val32; 285 286 /* Retrieve number irqs, use default if property not found */ 287 priv->nirq = XGENE_DFLT_MAX_NIRQ; 288 if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32)) 289 priv->nirq = val32; 290 291 /* Retrieve number gpio, use default if property not found */ 292 priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO; 293 if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32)) 294 priv->gc.ngpio = val32; 295 296 dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n", 297 priv->gc.ngpio, priv->nirq, priv->irq_start); 298 299 platform_set_drvdata(pdev, priv); 300 301 if (pdev->dev.of_node) 302 fwnode = of_node_to_fwnode(pdev->dev.of_node); 303 else 304 fwnode = pdev->dev.fwnode; 305 306 priv->irq_domain = irq_domain_create_hierarchy(parent_domain, 307 0, priv->nirq, fwnode, 308 &xgene_gpio_sb_domain_ops, priv); 309 if (!priv->irq_domain) 310 return -ENODEV; 311 312 priv->gc.irqdomain = priv->irq_domain; 313 314 ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); 315 if (ret) { 316 dev_err(&pdev->dev, 317 "failed to register X-Gene GPIO Standby driver\n"); 318 irq_domain_remove(priv->irq_domain); 319 return ret; 320 } 321 322 dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n"); 323 324 if (priv->nirq > 0) { 325 /* Register interrupt handlers for gpio signaled acpi events */ 326 acpi_gpiochip_request_interrupts(&priv->gc); 327 } 328 329 return ret; 330 } 331 332 static int xgene_gpio_sb_remove(struct platform_device *pdev) 333 { 334 struct xgene_gpio_sb *priv = platform_get_drvdata(pdev); 335 336 if (priv->nirq > 0) { 337 acpi_gpiochip_free_interrupts(&priv->gc); 338 } 339 340 irq_domain_remove(priv->irq_domain); 341 342 return 0; 343 } 344 345 static const struct of_device_id xgene_gpio_sb_of_match[] = { 346 {.compatible = "apm,xgene-gpio-sb", }, 347 {}, 348 }; 349 MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match); 350 351 #ifdef CONFIG_ACPI 352 static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = { 353 {"APMC0D15", 0}, 354 {}, 355 }; 356 MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match); 357 #endif 358 359 static struct platform_driver xgene_gpio_sb_driver = { 360 .driver = { 361 .name = "xgene-gpio-sb", 362 .of_match_table = xgene_gpio_sb_of_match, 363 .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match), 364 }, 365 .probe = xgene_gpio_sb_probe, 366 .remove = xgene_gpio_sb_remove, 367 }; 368 module_platform_driver(xgene_gpio_sb_driver); 369 370 MODULE_AUTHOR("AppliedMicro"); 371 MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver"); 372 MODULE_LICENSE("GPL"); 373