1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Whiskey Cove PMIC GPIO Driver 4 * 5 * This driver is written based on gpio-crystalcove.c 6 * 7 * Copyright (C) 2016 Intel Corporation. All rights reserved. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/intel_soc_pmic.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/seq_file.h> 18 #include <linux/string_choices.h> 19 20 /* 21 * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks: 22 * Bank 0: Pin 0 - 6 23 * Bank 1: Pin 7 - 10 24 * Bank 2: Pin 11 - 12 25 * Each pin has one output control register and one input control register. 26 */ 27 #define BANK0_NR_PINS 7 28 #define BANK1_NR_PINS 4 29 #define BANK2_NR_PINS 2 30 #define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS) 31 #define WCOVE_VGPIO_NUM 94 32 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */ 33 #define GPIO_OUT_CTRL_BASE 0x4e44 34 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */ 35 #define GPIO_IN_CTRL_BASE 0x4e51 36 37 /* 38 * GPIO interrupts are organized in two groups: 39 * Group 0: Bank 0 pins (Pin 0 - 6) 40 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12) 41 * Each group has two registers (one bit per pin): status and mask. 42 */ 43 #define GROUP0_NR_IRQS 7 44 #define GROUP1_NR_IRQS 6 45 #define IRQ_MASK_BASE 0x4e19 46 #define IRQ_STATUS_BASE 0x4e0b 47 #define GPIO_IRQ0_MASK GENMASK(6, 0) 48 #define GPIO_IRQ1_MASK GENMASK(5, 0) 49 #define UPDATE_IRQ_TYPE BIT(0) 50 #define UPDATE_IRQ_MASK BIT(1) 51 52 #define CTLI_INTCNT_DIS (0 << 1) 53 #define CTLI_INTCNT_NE (1 << 1) 54 #define CTLI_INTCNT_PE (2 << 1) 55 #define CTLI_INTCNT_BE (3 << 1) 56 57 #define CTLO_DIR_IN (0 << 5) 58 #define CTLO_DIR_OUT (1 << 5) 59 60 #define CTLO_DRV_MASK (1 << 4) 61 #define CTLO_DRV_OD (0 << 4) 62 #define CTLO_DRV_CMOS (1 << 4) 63 64 #define CTLO_DRV_REN (1 << 3) 65 66 #define CTLO_RVAL_2KDOWN (0 << 1) 67 #define CTLO_RVAL_2KUP (1 << 1) 68 #define CTLO_RVAL_50KDOWN (2 << 1) 69 #define CTLO_RVAL_50KUP (3 << 1) 70 71 #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) 72 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) 73 74 enum ctrl_register { 75 CTRL_IN, 76 CTRL_OUT, 77 IRQ_STATUS, 78 IRQ_MASK, 79 }; 80 81 /* 82 * struct wcove_gpio - Whiskey Cove GPIO controller 83 * @buslock: for bus lock/sync and unlock. 84 * @chip: the abstract gpio_chip structure. 85 * @dev: the gpio device 86 * @regmap: the regmap from the parent device. 87 * @regmap_irq_chip: the regmap of the gpio irq chip. 88 * @update: pending IRQ setting update, to be written to the chip upon unlock. 89 * @intcnt: the Interrupt Detect value to be written. 90 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear. 91 */ 92 struct wcove_gpio { 93 struct mutex buslock; 94 struct gpio_chip chip; 95 struct device *dev; 96 struct regmap *regmap; 97 struct regmap_irq_chip_data *regmap_irq_chip; 98 int update; 99 int intcnt; 100 bool set_irq_mask; 101 }; 102 103 static inline int to_reg(int gpio, enum ctrl_register type) 104 { 105 unsigned int reg = type == CTRL_IN ? GPIO_IN_CTRL_BASE : GPIO_OUT_CTRL_BASE; 106 107 if (gpio >= WCOVE_GPIO_NUM) 108 return -ENOTSUPP; 109 110 return reg + gpio; 111 } 112 113 static inline int to_ireg(int gpio, enum ctrl_register type, unsigned int *mask) 114 { 115 unsigned int reg = type == IRQ_STATUS ? IRQ_STATUS_BASE : IRQ_MASK_BASE; 116 117 if (gpio < GROUP0_NR_IRQS) { 118 reg += 0; 119 *mask = BIT(gpio); 120 } else { 121 reg += 1; 122 *mask = BIT(gpio - GROUP0_NR_IRQS); 123 } 124 125 return reg; 126 } 127 128 static void wcove_update_irq_mask(struct wcove_gpio *wg, irq_hw_number_t gpio) 129 { 130 unsigned int mask, reg = to_ireg(gpio, IRQ_MASK, &mask); 131 132 if (wg->set_irq_mask) 133 regmap_set_bits(wg->regmap, reg, mask); 134 else 135 regmap_clear_bits(wg->regmap, reg, mask); 136 } 137 138 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, irq_hw_number_t gpio) 139 { 140 int reg = to_reg(gpio, CTRL_IN); 141 142 regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); 143 } 144 145 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) 146 { 147 struct wcove_gpio *wg = gpiochip_get_data(chip); 148 int reg = to_reg(gpio, CTRL_OUT); 149 150 if (reg < 0) 151 return 0; 152 153 return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); 154 } 155 156 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, 157 int value) 158 { 159 struct wcove_gpio *wg = gpiochip_get_data(chip); 160 int reg = to_reg(gpio, CTRL_OUT); 161 162 if (reg < 0) 163 return 0; 164 165 return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); 166 } 167 168 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) 169 { 170 struct wcove_gpio *wg = gpiochip_get_data(chip); 171 unsigned int val; 172 int ret, reg = to_reg(gpio, CTRL_OUT); 173 174 if (reg < 0) 175 return GPIO_LINE_DIRECTION_OUT; 176 177 ret = regmap_read(wg->regmap, reg, &val); 178 if (ret) 179 return ret; 180 181 if (val & CTLO_DIR_OUT) 182 return GPIO_LINE_DIRECTION_OUT; 183 184 return GPIO_LINE_DIRECTION_IN; 185 } 186 187 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) 188 { 189 struct wcove_gpio *wg = gpiochip_get_data(chip); 190 unsigned int val; 191 int ret, reg = to_reg(gpio, CTRL_IN); 192 193 if (reg < 0) 194 return 0; 195 196 ret = regmap_read(wg->regmap, reg, &val); 197 if (ret) 198 return ret; 199 200 return val & 0x1; 201 } 202 203 static void wcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) 204 { 205 struct wcove_gpio *wg = gpiochip_get_data(chip); 206 int reg = to_reg(gpio, CTRL_OUT); 207 208 if (reg < 0) 209 return; 210 211 if (value) 212 regmap_set_bits(wg->regmap, reg, 1); 213 else 214 regmap_clear_bits(wg->regmap, reg, 1); 215 } 216 217 static int wcove_gpio_set_config(struct gpio_chip *chip, unsigned int gpio, 218 unsigned long config) 219 { 220 struct wcove_gpio *wg = gpiochip_get_data(chip); 221 int reg = to_reg(gpio, CTRL_OUT); 222 223 if (reg < 0) 224 return 0; 225 226 switch (pinconf_to_config_param(config)) { 227 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 228 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 229 CTLO_DRV_OD); 230 case PIN_CONFIG_DRIVE_PUSH_PULL: 231 return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, 232 CTLO_DRV_CMOS); 233 default: 234 break; 235 } 236 237 return -ENOTSUPP; 238 } 239 240 static int wcove_irq_type(struct irq_data *data, unsigned int type) 241 { 242 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 243 struct wcove_gpio *wg = gpiochip_get_data(chip); 244 irq_hw_number_t gpio = irqd_to_hwirq(data); 245 246 if (gpio >= WCOVE_GPIO_NUM) 247 return 0; 248 249 switch (type) { 250 case IRQ_TYPE_NONE: 251 wg->intcnt = CTLI_INTCNT_DIS; 252 break; 253 case IRQ_TYPE_EDGE_BOTH: 254 wg->intcnt = CTLI_INTCNT_BE; 255 break; 256 case IRQ_TYPE_EDGE_RISING: 257 wg->intcnt = CTLI_INTCNT_PE; 258 break; 259 case IRQ_TYPE_EDGE_FALLING: 260 wg->intcnt = CTLI_INTCNT_NE; 261 break; 262 default: 263 return -EINVAL; 264 } 265 266 wg->update |= UPDATE_IRQ_TYPE; 267 268 return 0; 269 } 270 271 static void wcove_bus_lock(struct irq_data *data) 272 { 273 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 274 struct wcove_gpio *wg = gpiochip_get_data(chip); 275 276 mutex_lock(&wg->buslock); 277 } 278 279 static void wcove_bus_sync_unlock(struct irq_data *data) 280 { 281 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 282 struct wcove_gpio *wg = gpiochip_get_data(chip); 283 irq_hw_number_t gpio = irqd_to_hwirq(data); 284 285 if (wg->update & UPDATE_IRQ_TYPE) 286 wcove_update_irq_ctrl(wg, gpio); 287 if (wg->update & UPDATE_IRQ_MASK) 288 wcove_update_irq_mask(wg, gpio); 289 wg->update = 0; 290 291 mutex_unlock(&wg->buslock); 292 } 293 294 static void wcove_irq_unmask(struct irq_data *data) 295 { 296 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 297 struct wcove_gpio *wg = gpiochip_get_data(chip); 298 irq_hw_number_t gpio = irqd_to_hwirq(data); 299 300 if (gpio >= WCOVE_GPIO_NUM) 301 return; 302 303 gpiochip_enable_irq(chip, gpio); 304 305 wg->set_irq_mask = false; 306 wg->update |= UPDATE_IRQ_MASK; 307 } 308 309 static void wcove_irq_mask(struct irq_data *data) 310 { 311 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 312 struct wcove_gpio *wg = gpiochip_get_data(chip); 313 irq_hw_number_t gpio = irqd_to_hwirq(data); 314 315 if (gpio >= WCOVE_GPIO_NUM) 316 return; 317 318 wg->set_irq_mask = true; 319 wg->update |= UPDATE_IRQ_MASK; 320 321 gpiochip_disable_irq(chip, gpio); 322 } 323 324 static const struct irq_chip wcove_irqchip = { 325 .name = "Whiskey Cove", 326 .irq_mask = wcove_irq_mask, 327 .irq_unmask = wcove_irq_unmask, 328 .irq_set_type = wcove_irq_type, 329 .irq_bus_lock = wcove_bus_lock, 330 .irq_bus_sync_unlock = wcove_bus_sync_unlock, 331 .flags = IRQCHIP_IMMUTABLE, 332 GPIOCHIP_IRQ_RESOURCE_HELPERS, 333 }; 334 335 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data) 336 { 337 struct wcove_gpio *wg = (struct wcove_gpio *)data; 338 unsigned int virq, gpio; 339 unsigned long pending; 340 u8 p[2]; 341 342 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 343 dev_err(wg->dev, "Failed to read irq status register\n"); 344 return IRQ_NONE; 345 } 346 347 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 348 if (!pending) 349 return IRQ_NONE; 350 351 /* Iterate until no interrupt is pending */ 352 while (pending) { 353 /* One iteration is for all pending bits */ 354 for_each_set_bit(gpio, &pending, WCOVE_GPIO_NUM) { 355 unsigned int mask, reg = to_ireg(gpio, IRQ_STATUS, &mask); 356 357 virq = irq_find_mapping(wg->chip.irq.domain, gpio); 358 handle_nested_irq(virq); 359 regmap_set_bits(wg->regmap, reg, mask); 360 } 361 362 /* Next iteration */ 363 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { 364 dev_err(wg->dev, "Failed to read irq status\n"); 365 break; 366 } 367 368 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7); 369 } 370 371 return IRQ_HANDLED; 372 } 373 374 static void wcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 375 { 376 unsigned int ctlo, ctli, irq_mask, irq_status; 377 struct wcove_gpio *wg = gpiochip_get_data(chip); 378 int gpio, mask, ret = 0; 379 380 for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) { 381 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); 382 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); 383 if (ret) { 384 dev_err(wg->dev, "Failed to read registers: CTRL out/in\n"); 385 break; 386 } 387 388 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_MASK, &mask), &irq_mask); 389 ret += regmap_read(wg->regmap, to_ireg(gpio, IRQ_STATUS, &mask), &irq_status); 390 if (ret) { 391 dev_err(wg->dev, "Failed to read registers: IRQ status/mask\n"); 392 break; 393 } 394 395 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n", 396 gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", 397 str_hi_lo(ctli & 0x1), 398 ctli & CTLI_INTCNT_NE ? "fall" : " ", 399 ctli & CTLI_INTCNT_PE ? "rise" : " ", 400 ctlo, 401 irq_mask & mask ? "mask " : "unmask", 402 irq_status & mask ? "pending" : " "); 403 } 404 } 405 406 static int wcove_gpio_probe(struct platform_device *pdev) 407 { 408 struct intel_soc_pmic *pmic; 409 struct wcove_gpio *wg; 410 int virq, ret, irq; 411 struct device *dev; 412 struct gpio_irq_chip *girq; 413 414 /* 415 * This gpio platform device is created by a mfd device (see 416 * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information 417 * shared by all sub-devices created by the mfd device, the regmap 418 * pointer for instance, is stored as driver data of the mfd device 419 * driver. 420 */ 421 pmic = dev_get_drvdata(pdev->dev.parent); 422 if (!pmic) 423 return -ENODEV; 424 425 irq = platform_get_irq(pdev, 0); 426 if (irq < 0) 427 return irq; 428 429 dev = &pdev->dev; 430 431 wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); 432 if (!wg) 433 return -ENOMEM; 434 435 wg->regmap_irq_chip = pmic->irq_chip_data; 436 437 platform_set_drvdata(pdev, wg); 438 439 mutex_init(&wg->buslock); 440 wg->chip.label = KBUILD_MODNAME; 441 wg->chip.direction_input = wcove_gpio_dir_in; 442 wg->chip.direction_output = wcove_gpio_dir_out; 443 wg->chip.get_direction = wcove_gpio_get_direction; 444 wg->chip.get = wcove_gpio_get; 445 wg->chip.set = wcove_gpio_set; 446 wg->chip.set_config = wcove_gpio_set_config; 447 wg->chip.base = -1; 448 wg->chip.ngpio = WCOVE_VGPIO_NUM; 449 wg->chip.can_sleep = true; 450 wg->chip.parent = pdev->dev.parent; 451 wg->chip.dbg_show = wcove_gpio_dbg_show; 452 wg->dev = dev; 453 wg->regmap = pmic->regmap; 454 455 virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); 456 if (virq < 0) { 457 dev_err(dev, "Failed to get virq by irq %d\n", irq); 458 return virq; 459 } 460 461 girq = &wg->chip.irq; 462 gpio_irq_chip_set_chip(girq, &wcove_irqchip); 463 /* This will let us handle the parent IRQ in the driver */ 464 girq->parent_handler = NULL; 465 girq->num_parents = 0; 466 girq->parents = NULL; 467 girq->default_type = IRQ_TYPE_NONE; 468 girq->handler = handle_simple_irq; 469 girq->threaded = true; 470 471 ret = devm_request_threaded_irq(dev, virq, NULL, wcove_gpio_irq_handler, 472 IRQF_ONESHOT, pdev->name, wg); 473 if (ret) { 474 dev_err(dev, "Failed to request irq %d\n", virq); 475 return ret; 476 } 477 478 ret = devm_gpiochip_add_data(dev, &wg->chip, wg); 479 if (ret) { 480 dev_err(dev, "Failed to add gpiochip: %d\n", ret); 481 return ret; 482 } 483 484 /* Enable GPIO0 interrupts */ 485 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 0, GPIO_IRQ0_MASK); 486 if (ret) 487 return ret; 488 489 /* Enable GPIO1 interrupts */ 490 ret = regmap_clear_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK); 491 if (ret) 492 return ret; 493 494 return 0; 495 } 496 497 /* 498 * Whiskey Cove PMIC itself is a analog device(but with digital control 499 * interface) providing power management support for other devices in 500 * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver. 501 */ 502 static struct platform_driver wcove_gpio_driver = { 503 .driver = { 504 .name = "bxt_wcove_gpio", 505 }, 506 .probe = wcove_gpio_probe, 507 }; 508 509 module_platform_driver(wcove_gpio_driver); 510 511 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>"); 512 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>"); 513 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver"); 514 MODULE_LICENSE("GPL v2"); 515 MODULE_ALIAS("platform:bxt_wcove_gpio"); 516