1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale vf610 GPIO support through PORT and GPIO 4 * 5 * Copyright (c) 2014 Toradex AG. 6 * 7 * Author: Stefan Agner <stefan@agner.ch>. 8 */ 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/gpio/generic.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/irq.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/property.h> 22 23 #define VF610_GPIO_PER_PORT 32 24 25 struct fsl_gpio_soc_data { 26 /* SoCs has a Port Data Direction Register (PDDR) */ 27 bool have_paddr; 28 bool have_dual_base; 29 }; 30 31 struct vf610_gpio_port { 32 struct gpio_generic_chip chip; 33 void __iomem *base; 34 void __iomem *gpio_base; 35 const struct fsl_gpio_soc_data *sdata; 36 u8 irqc[VF610_GPIO_PER_PORT]; 37 struct clk *clk_port; 38 struct clk *clk_gpio; 39 int irq; 40 }; 41 42 #define GPIO_PDOR 0x00 43 #define GPIO_PSOR 0x04 44 #define GPIO_PCOR 0x08 45 #define GPIO_PTOR 0x0c 46 #define GPIO_PDIR 0x10 47 #define GPIO_PDDR 0x14 48 49 #define PORT_PCR(n) ((n) * 0x4) 50 #define PORT_PCR_IRQC_OFFSET 16 51 52 #define PORT_ISFR 0xa0 53 #define PORT_DFER 0xc0 54 #define PORT_DFCR 0xc4 55 #define PORT_DFWR 0xc8 56 57 #define PORT_INT_OFF 0x0 58 #define PORT_INT_LOGIC_ZERO 0x8 59 #define PORT_INT_RISING_EDGE 0x9 60 #define PORT_INT_FALLING_EDGE 0xa 61 #define PORT_INT_EITHER_EDGE 0xb 62 #define PORT_INT_LOGIC_ONE 0xc 63 64 #define IMX8ULP_GPIO_BASE_OFF 0x40 65 #define IMX8ULP_BASE_OFF 0x80 66 67 static const struct fsl_gpio_soc_data vf610_data = { 68 .have_dual_base = true, 69 }; 70 71 static const struct fsl_gpio_soc_data imx_data = { 72 .have_paddr = true, 73 .have_dual_base = true, 74 }; 75 76 static const struct fsl_gpio_soc_data imx8ulp_data = { 77 .have_paddr = true, 78 }; 79 80 static const struct of_device_id vf610_gpio_dt_ids[] = { 81 { .compatible = "fsl,vf610-gpio", .data = &vf610_data }, 82 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 83 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, }, 84 { /* sentinel */ } 85 }; 86 MODULE_DEVICE_TABLE(of, vf610_gpio_dt_ids); 87 88 static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 89 { 90 writel_relaxed(val, reg); 91 } 92 93 static inline u32 vf610_gpio_readl(void __iomem *reg) 94 { 95 return readl_relaxed(reg); 96 } 97 98 static void vf610_gpio_irq_handler(struct irq_desc *desc) 99 { 100 struct vf610_gpio_port *port = 101 gpiochip_get_data(irq_desc_get_handler_data(desc)); 102 struct irq_chip *chip = irq_desc_get_chip(desc); 103 int pin; 104 unsigned long irq_isfr; 105 106 chained_irq_enter(chip, desc); 107 108 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 109 110 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 111 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 112 113 generic_handle_domain_irq(port->chip.gc.irq.domain, pin); 114 } 115 116 chained_irq_exit(chip, desc); 117 } 118 119 static void vf610_gpio_irq_ack(struct irq_data *d) 120 { 121 struct vf610_gpio_port *port = 122 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 123 int gpio = d->hwirq; 124 125 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 126 } 127 128 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 129 { 130 struct vf610_gpio_port *port = 131 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 132 u8 irqc; 133 134 switch (type) { 135 case IRQ_TYPE_EDGE_RISING: 136 irqc = PORT_INT_RISING_EDGE; 137 break; 138 case IRQ_TYPE_EDGE_FALLING: 139 irqc = PORT_INT_FALLING_EDGE; 140 break; 141 case IRQ_TYPE_EDGE_BOTH: 142 irqc = PORT_INT_EITHER_EDGE; 143 break; 144 case IRQ_TYPE_LEVEL_LOW: 145 irqc = PORT_INT_LOGIC_ZERO; 146 break; 147 case IRQ_TYPE_LEVEL_HIGH: 148 irqc = PORT_INT_LOGIC_ONE; 149 break; 150 default: 151 return -EINVAL; 152 } 153 154 port->irqc[d->hwirq] = irqc; 155 156 if (type & IRQ_TYPE_LEVEL_MASK) 157 irq_set_handler_locked(d, handle_level_irq); 158 else 159 irq_set_handler_locked(d, handle_edge_irq); 160 161 return 0; 162 } 163 164 static void vf610_gpio_irq_mask(struct irq_data *d) 165 { 166 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 167 struct vf610_gpio_port *port = gpiochip_get_data(gc); 168 irq_hw_number_t gpio_num = irqd_to_hwirq(d); 169 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 170 171 vf610_gpio_writel(0, pcr_base); 172 gpiochip_disable_irq(gc, gpio_num); 173 } 174 175 static void vf610_gpio_irq_unmask(struct irq_data *d) 176 { 177 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 178 struct vf610_gpio_port *port = gpiochip_get_data(gc); 179 irq_hw_number_t gpio_num = irqd_to_hwirq(d); 180 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 181 182 gpiochip_enable_irq(gc, gpio_num); 183 vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET, 184 pcr_base); 185 } 186 187 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 188 { 189 struct vf610_gpio_port *port = 190 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 191 192 if (enable) 193 enable_irq_wake(port->irq); 194 else 195 disable_irq_wake(port->irq); 196 197 return 0; 198 } 199 200 static const struct irq_chip vf610_irqchip = { 201 .name = "gpio-vf610", 202 .irq_ack = vf610_gpio_irq_ack, 203 .irq_mask = vf610_gpio_irq_mask, 204 .irq_unmask = vf610_gpio_irq_unmask, 205 .irq_set_type = vf610_gpio_irq_set_type, 206 .irq_set_wake = vf610_gpio_irq_set_wake, 207 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND 208 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 209 GPIOCHIP_IRQ_RESOURCE_HELPERS, 210 }; 211 212 static void vf610_gpio_disable_clk(void *data) 213 { 214 clk_disable_unprepare(data); 215 } 216 217 static int vf610_gpio_probe(struct platform_device *pdev) 218 { 219 struct gpio_generic_chip_config config; 220 struct device *dev = &pdev->dev; 221 struct vf610_gpio_port *port; 222 struct gpio_chip *gc; 223 struct gpio_irq_chip *girq; 224 unsigned long flags; 225 int i; 226 int ret; 227 bool dual_base; 228 229 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 230 if (!port) 231 return -ENOMEM; 232 233 port->sdata = device_get_match_data(dev); 234 235 dual_base = port->sdata->have_dual_base; 236 237 /* 238 * Handle legacy compatible combinations which used two reg values 239 * for the i.MX8ULP and i.MX93. 240 */ 241 if (device_is_compatible(dev, "fsl,imx7ulp-gpio") && 242 (device_is_compatible(dev, "fsl,imx93-gpio") || 243 (device_is_compatible(dev, "fsl,imx8ulp-gpio")))) 244 dual_base = true; 245 246 if (dual_base) { 247 port->base = devm_platform_ioremap_resource(pdev, 0); 248 if (IS_ERR(port->base)) 249 return PTR_ERR(port->base); 250 251 port->gpio_base = devm_platform_ioremap_resource(pdev, 1); 252 if (IS_ERR(port->gpio_base)) 253 return PTR_ERR(port->gpio_base); 254 } else { 255 port->base = devm_platform_ioremap_resource(pdev, 0); 256 if (IS_ERR(port->base)) 257 return PTR_ERR(port->base); 258 259 port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF; 260 port->base = port->base + IMX8ULP_BASE_OFF; 261 } 262 263 port->irq = platform_get_irq(pdev, 0); 264 if (port->irq < 0) 265 return port->irq; 266 267 port->clk_port = devm_clk_get(dev, "port"); 268 ret = PTR_ERR_OR_ZERO(port->clk_port); 269 if (!ret) { 270 ret = clk_prepare_enable(port->clk_port); 271 if (ret) 272 return ret; 273 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 274 port->clk_port); 275 if (ret) 276 return ret; 277 } else if (ret == -EPROBE_DEFER) { 278 /* 279 * Percolate deferrals, for anything else, 280 * just live without the clocking. 281 */ 282 return ret; 283 } 284 285 port->clk_gpio = devm_clk_get(dev, "gpio"); 286 ret = PTR_ERR_OR_ZERO(port->clk_gpio); 287 if (!ret) { 288 ret = clk_prepare_enable(port->clk_gpio); 289 if (ret) 290 return ret; 291 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 292 port->clk_gpio); 293 if (ret) 294 return ret; 295 } else if (ret == -EPROBE_DEFER) { 296 return ret; 297 } 298 299 gc = &port->chip.gc; 300 flags = GPIO_GENERIC_PINCTRL_BACKEND; 301 /* 302 * We only read the output register for current value on output 303 * lines if the direction register is available so we can switch 304 * direction. 305 */ 306 if (port->sdata->have_paddr) 307 flags |= GPIO_GENERIC_READ_OUTPUT_REG_SET; 308 309 config = (struct gpio_generic_chip_config) { 310 .dev = dev, 311 .sz = 4, 312 .dat = port->gpio_base + GPIO_PDIR, 313 .set = port->gpio_base + GPIO_PDOR, 314 .dirout = port->sdata->have_paddr ? 315 port->gpio_base + GPIO_PDDR : NULL, 316 .flags = flags, 317 }; 318 319 ret = gpio_generic_chip_init(&port->chip, &config); 320 if (ret) 321 return dev_err_probe(dev, ret, "unable to init generic GPIO\n"); 322 gc->label = dev_name(dev); 323 gc->base = -1; 324 325 /* Mask all GPIO interrupts */ 326 for (i = 0; i < gc->ngpio; i++) 327 vf610_gpio_writel(0, port->base + PORT_PCR(i)); 328 329 /* Clear the interrupt status register for all GPIO's */ 330 vf610_gpio_writel(~0, port->base + PORT_ISFR); 331 332 girq = &gc->irq; 333 gpio_irq_chip_set_chip(girq, &vf610_irqchip); 334 girq->parent_handler = vf610_gpio_irq_handler; 335 girq->num_parents = 1; 336 girq->parents = devm_kcalloc(&pdev->dev, 1, 337 sizeof(*girq->parents), 338 GFP_KERNEL); 339 if (!girq->parents) 340 return -ENOMEM; 341 girq->parents[0] = port->irq; 342 girq->default_type = IRQ_TYPE_NONE; 343 girq->handler = handle_edge_irq; 344 345 return devm_gpiochip_add_data(dev, gc, port); 346 } 347 348 static struct platform_driver vf610_gpio_driver = { 349 .driver = { 350 .name = "gpio-vf610", 351 .of_match_table = vf610_gpio_dt_ids, 352 }, 353 .probe = vf610_gpio_probe, 354 }; 355 356 module_platform_driver(vf610_gpio_driver); 357 MODULE_DESCRIPTION("VF610 GPIO driver"); 358 MODULE_LICENSE("GPL"); 359