1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale vf610 GPIO support through PORT and GPIO 4 * 5 * Copyright (c) 2014 Toradex AG. 6 * 7 * Author: Stefan Agner <stefan@agner.ch>. 8 */ 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 23 #define VF610_GPIO_PER_PORT 32 24 25 struct fsl_gpio_soc_data { 26 /* SoCs has a Port Data Direction Register (PDDR) */ 27 bool have_paddr; 28 }; 29 30 struct vf610_gpio_port { 31 struct gpio_chip gc; 32 struct irq_chip ic; 33 void __iomem *base; 34 void __iomem *gpio_base; 35 const struct fsl_gpio_soc_data *sdata; 36 u8 irqc[VF610_GPIO_PER_PORT]; 37 struct clk *clk_port; 38 struct clk *clk_gpio; 39 int irq; 40 }; 41 42 #define GPIO_PDOR 0x00 43 #define GPIO_PSOR 0x04 44 #define GPIO_PCOR 0x08 45 #define GPIO_PTOR 0x0c 46 #define GPIO_PDIR 0x10 47 #define GPIO_PDDR 0x14 48 49 #define PORT_PCR(n) ((n) * 0x4) 50 #define PORT_PCR_IRQC_OFFSET 16 51 52 #define PORT_ISFR 0xa0 53 #define PORT_DFER 0xc0 54 #define PORT_DFCR 0xc4 55 #define PORT_DFWR 0xc8 56 57 #define PORT_INT_OFF 0x0 58 #define PORT_INT_LOGIC_ZERO 0x8 59 #define PORT_INT_RISING_EDGE 0x9 60 #define PORT_INT_FALLING_EDGE 0xa 61 #define PORT_INT_EITHER_EDGE 0xb 62 #define PORT_INT_LOGIC_ONE 0xc 63 64 static const struct fsl_gpio_soc_data imx_data = { 65 .have_paddr = true, 66 }; 67 68 static const struct of_device_id vf610_gpio_dt_ids[] = { 69 { .compatible = "fsl,vf610-gpio", .data = NULL, }, 70 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 71 { /* sentinel */ } 72 }; 73 74 static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 75 { 76 writel_relaxed(val, reg); 77 } 78 79 static inline u32 vf610_gpio_readl(void __iomem *reg) 80 { 81 return readl_relaxed(reg); 82 } 83 84 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 85 { 86 struct vf610_gpio_port *port = gpiochip_get_data(gc); 87 unsigned long mask = BIT(gpio); 88 unsigned long offset = GPIO_PDIR; 89 90 if (port->sdata && port->sdata->have_paddr) { 91 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 92 if (mask) 93 offset = GPIO_PDOR; 94 } 95 96 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); 97 } 98 99 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 100 { 101 struct vf610_gpio_port *port = gpiochip_get_data(gc); 102 unsigned long mask = BIT(gpio); 103 unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; 104 105 vf610_gpio_writel(mask, port->gpio_base + offset); 106 } 107 108 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 109 { 110 struct vf610_gpio_port *port = gpiochip_get_data(chip); 111 unsigned long mask = BIT(gpio); 112 u32 val; 113 114 if (port->sdata && port->sdata->have_paddr) { 115 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 116 val &= ~mask; 117 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 118 } 119 120 return pinctrl_gpio_direction_input(chip->base + gpio); 121 } 122 123 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, 124 int value) 125 { 126 struct vf610_gpio_port *port = gpiochip_get_data(chip); 127 unsigned long mask = BIT(gpio); 128 u32 val; 129 130 if (port->sdata && port->sdata->have_paddr) { 131 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 132 val |= mask; 133 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 134 } 135 136 vf610_gpio_set(chip, gpio, value); 137 138 return pinctrl_gpio_direction_output(chip->base + gpio); 139 } 140 141 static void vf610_gpio_irq_handler(struct irq_desc *desc) 142 { 143 struct vf610_gpio_port *port = 144 gpiochip_get_data(irq_desc_get_handler_data(desc)); 145 struct irq_chip *chip = irq_desc_get_chip(desc); 146 int pin; 147 unsigned long irq_isfr; 148 149 chained_irq_enter(chip, desc); 150 151 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 152 153 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 154 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 155 156 generic_handle_domain_irq(port->gc.irq.domain, pin); 157 } 158 159 chained_irq_exit(chip, desc); 160 } 161 162 static void vf610_gpio_irq_ack(struct irq_data *d) 163 { 164 struct vf610_gpio_port *port = 165 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 166 int gpio = d->hwirq; 167 168 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 169 } 170 171 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 172 { 173 struct vf610_gpio_port *port = 174 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 175 u8 irqc; 176 177 switch (type) { 178 case IRQ_TYPE_EDGE_RISING: 179 irqc = PORT_INT_RISING_EDGE; 180 break; 181 case IRQ_TYPE_EDGE_FALLING: 182 irqc = PORT_INT_FALLING_EDGE; 183 break; 184 case IRQ_TYPE_EDGE_BOTH: 185 irqc = PORT_INT_EITHER_EDGE; 186 break; 187 case IRQ_TYPE_LEVEL_LOW: 188 irqc = PORT_INT_LOGIC_ZERO; 189 break; 190 case IRQ_TYPE_LEVEL_HIGH: 191 irqc = PORT_INT_LOGIC_ONE; 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 port->irqc[d->hwirq] = irqc; 198 199 if (type & IRQ_TYPE_LEVEL_MASK) 200 irq_set_handler_locked(d, handle_level_irq); 201 else 202 irq_set_handler_locked(d, handle_edge_irq); 203 204 return 0; 205 } 206 207 static void vf610_gpio_irq_mask(struct irq_data *d) 208 { 209 struct vf610_gpio_port *port = 210 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 211 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 212 213 vf610_gpio_writel(0, pcr_base); 214 } 215 216 static void vf610_gpio_irq_unmask(struct irq_data *d) 217 { 218 struct vf610_gpio_port *port = 219 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 220 void __iomem *pcr_base = port->base + PORT_PCR(d->hwirq); 221 222 vf610_gpio_writel(port->irqc[d->hwirq] << PORT_PCR_IRQC_OFFSET, 223 pcr_base); 224 } 225 226 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 227 { 228 struct vf610_gpio_port *port = 229 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 230 231 if (enable) 232 enable_irq_wake(port->irq); 233 else 234 disable_irq_wake(port->irq); 235 236 return 0; 237 } 238 239 static void vf610_gpio_disable_clk(void *data) 240 { 241 clk_disable_unprepare(data); 242 } 243 244 static int vf610_gpio_probe(struct platform_device *pdev) 245 { 246 struct device *dev = &pdev->dev; 247 struct device_node *np = dev->of_node; 248 struct vf610_gpio_port *port; 249 struct gpio_chip *gc; 250 struct gpio_irq_chip *girq; 251 struct irq_chip *ic; 252 int i; 253 int ret; 254 255 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 256 if (!port) 257 return -ENOMEM; 258 259 port->sdata = of_device_get_match_data(dev); 260 port->base = devm_platform_ioremap_resource(pdev, 0); 261 if (IS_ERR(port->base)) 262 return PTR_ERR(port->base); 263 264 port->gpio_base = devm_platform_ioremap_resource(pdev, 1); 265 if (IS_ERR(port->gpio_base)) 266 return PTR_ERR(port->gpio_base); 267 268 port->irq = platform_get_irq(pdev, 0); 269 if (port->irq < 0) 270 return port->irq; 271 272 port->clk_port = devm_clk_get(dev, "port"); 273 ret = PTR_ERR_OR_ZERO(port->clk_port); 274 if (!ret) { 275 ret = clk_prepare_enable(port->clk_port); 276 if (ret) 277 return ret; 278 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 279 port->clk_port); 280 if (ret) 281 return ret; 282 } else if (ret == -EPROBE_DEFER) { 283 /* 284 * Percolate deferrals, for anything else, 285 * just live without the clocking. 286 */ 287 return ret; 288 } 289 290 port->clk_gpio = devm_clk_get(dev, "gpio"); 291 ret = PTR_ERR_OR_ZERO(port->clk_gpio); 292 if (!ret) { 293 ret = clk_prepare_enable(port->clk_gpio); 294 if (ret) 295 return ret; 296 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 297 port->clk_gpio); 298 if (ret) 299 return ret; 300 } else if (ret == -EPROBE_DEFER) { 301 return ret; 302 } 303 304 gc = &port->gc; 305 gc->parent = dev; 306 gc->label = "vf610-gpio"; 307 gc->ngpio = VF610_GPIO_PER_PORT; 308 gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; 309 310 gc->request = gpiochip_generic_request; 311 gc->free = gpiochip_generic_free; 312 gc->direction_input = vf610_gpio_direction_input; 313 gc->get = vf610_gpio_get; 314 gc->direction_output = vf610_gpio_direction_output; 315 gc->set = vf610_gpio_set; 316 317 ic = &port->ic; 318 ic->name = "gpio-vf610"; 319 ic->irq_ack = vf610_gpio_irq_ack; 320 ic->irq_mask = vf610_gpio_irq_mask; 321 ic->irq_unmask = vf610_gpio_irq_unmask; 322 ic->irq_set_type = vf610_gpio_irq_set_type; 323 ic->irq_set_wake = vf610_gpio_irq_set_wake; 324 325 /* Mask all GPIO interrupts */ 326 for (i = 0; i < gc->ngpio; i++) 327 vf610_gpio_writel(0, port->base + PORT_PCR(i)); 328 329 /* Clear the interrupt status register for all GPIO's */ 330 vf610_gpio_writel(~0, port->base + PORT_ISFR); 331 332 girq = &gc->irq; 333 girq->chip = ic; 334 girq->parent_handler = vf610_gpio_irq_handler; 335 girq->num_parents = 1; 336 girq->parents = devm_kcalloc(&pdev->dev, 1, 337 sizeof(*girq->parents), 338 GFP_KERNEL); 339 if (!girq->parents) 340 return -ENOMEM; 341 girq->parents[0] = port->irq; 342 girq->default_type = IRQ_TYPE_NONE; 343 girq->handler = handle_edge_irq; 344 345 return devm_gpiochip_add_data(dev, gc, port); 346 } 347 348 static struct platform_driver vf610_gpio_driver = { 349 .driver = { 350 .name = "gpio-vf610", 351 .of_match_table = vf610_gpio_dt_ids, 352 }, 353 .probe = vf610_gpio_probe, 354 }; 355 356 builtin_platform_driver(vf610_gpio_driver); 357