1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale vf610 GPIO support through PORT and GPIO 4 * 5 * Copyright (c) 2014 Toradex AG. 6 * 7 * Author: Stefan Agner <stefan@agner.ch>. 8 */ 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/gpio/driver.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/ioport.h> 17 #include <linux/irq.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 22 #define VF610_GPIO_PER_PORT 32 23 24 struct fsl_gpio_soc_data { 25 /* SoCs has a Port Data Direction Register (PDDR) */ 26 bool have_paddr; 27 bool have_dual_base; 28 }; 29 30 struct vf610_gpio_port { 31 struct gpio_chip gc; 32 void __iomem *base; 33 void __iomem *gpio_base; 34 const struct fsl_gpio_soc_data *sdata; 35 u8 irqc[VF610_GPIO_PER_PORT]; 36 struct clk *clk_port; 37 struct clk *clk_gpio; 38 int irq; 39 spinlock_t lock; /* protect gpio direction registers */ 40 }; 41 42 #define GPIO_PDOR 0x00 43 #define GPIO_PSOR 0x04 44 #define GPIO_PCOR 0x08 45 #define GPIO_PTOR 0x0c 46 #define GPIO_PDIR 0x10 47 #define GPIO_PDDR 0x14 48 49 #define PORT_PCR(n) ((n) * 0x4) 50 #define PORT_PCR_IRQC_OFFSET 16 51 52 #define PORT_ISFR 0xa0 53 #define PORT_DFER 0xc0 54 #define PORT_DFCR 0xc4 55 #define PORT_DFWR 0xc8 56 57 #define PORT_INT_OFF 0x0 58 #define PORT_INT_LOGIC_ZERO 0x8 59 #define PORT_INT_RISING_EDGE 0x9 60 #define PORT_INT_FALLING_EDGE 0xa 61 #define PORT_INT_EITHER_EDGE 0xb 62 #define PORT_INT_LOGIC_ONE 0xc 63 64 #define IMX8ULP_GPIO_BASE_OFF 0x40 65 #define IMX8ULP_BASE_OFF 0x80 66 67 static const struct fsl_gpio_soc_data vf610_data = { 68 .have_dual_base = true, 69 }; 70 71 static const struct fsl_gpio_soc_data imx_data = { 72 .have_paddr = true, 73 .have_dual_base = true, 74 }; 75 76 static const struct fsl_gpio_soc_data imx8ulp_data = { 77 .have_paddr = true, 78 }; 79 80 static const struct of_device_id vf610_gpio_dt_ids[] = { 81 { .compatible = "fsl,vf610-gpio", .data = &vf610_data }, 82 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, 83 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, }, 84 { /* sentinel */ } 85 }; 86 87 static inline void vf610_gpio_writel(u32 val, void __iomem *reg) 88 { 89 writel_relaxed(val, reg); 90 } 91 92 static inline u32 vf610_gpio_readl(void __iomem *reg) 93 { 94 return readl_relaxed(reg); 95 } 96 97 static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio) 98 { 99 struct vf610_gpio_port *port = gpiochip_get_data(gc); 100 u32 mask = BIT(gpio); 101 unsigned long offset = GPIO_PDIR; 102 103 if (port->sdata->have_paddr) { 104 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 105 if (mask) 106 offset = GPIO_PDOR; 107 } 108 109 return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio)); 110 } 111 112 static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 113 { 114 struct vf610_gpio_port *port = gpiochip_get_data(gc); 115 u32 mask = BIT(gpio); 116 unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR; 117 118 vf610_gpio_writel(mask, port->gpio_base + offset); 119 } 120 121 static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) 122 { 123 struct vf610_gpio_port *port = gpiochip_get_data(chip); 124 u32 mask = BIT(gpio); 125 u32 val; 126 127 if (port->sdata->have_paddr) { 128 guard(spinlock_irqsave)(&port->lock); 129 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 130 val &= ~mask; 131 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 132 } 133 134 return pinctrl_gpio_direction_input(chip, gpio); 135 } 136 137 static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, 138 int value) 139 { 140 struct vf610_gpio_port *port = gpiochip_get_data(chip); 141 u32 mask = BIT(gpio); 142 u32 val; 143 144 vf610_gpio_set(chip, gpio, value); 145 146 if (port->sdata->have_paddr) { 147 guard(spinlock_irqsave)(&port->lock); 148 val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 149 val |= mask; 150 vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); 151 } 152 153 return pinctrl_gpio_direction_output(chip, gpio); 154 } 155 156 static int vf610_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 157 { 158 struct vf610_gpio_port *port = gpiochip_get_data(gc); 159 u32 mask = BIT(gpio); 160 161 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); 162 163 if (mask) 164 return GPIO_LINE_DIRECTION_OUT; 165 166 return GPIO_LINE_DIRECTION_IN; 167 } 168 169 static void vf610_gpio_irq_handler(struct irq_desc *desc) 170 { 171 struct vf610_gpio_port *port = 172 gpiochip_get_data(irq_desc_get_handler_data(desc)); 173 struct irq_chip *chip = irq_desc_get_chip(desc); 174 int pin; 175 unsigned long irq_isfr; 176 177 chained_irq_enter(chip, desc); 178 179 irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR); 180 181 for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) { 182 vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR); 183 184 generic_handle_domain_irq(port->gc.irq.domain, pin); 185 } 186 187 chained_irq_exit(chip, desc); 188 } 189 190 static void vf610_gpio_irq_ack(struct irq_data *d) 191 { 192 struct vf610_gpio_port *port = 193 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 194 int gpio = d->hwirq; 195 196 vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR); 197 } 198 199 static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type) 200 { 201 struct vf610_gpio_port *port = 202 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 203 u8 irqc; 204 205 switch (type) { 206 case IRQ_TYPE_EDGE_RISING: 207 irqc = PORT_INT_RISING_EDGE; 208 break; 209 case IRQ_TYPE_EDGE_FALLING: 210 irqc = PORT_INT_FALLING_EDGE; 211 break; 212 case IRQ_TYPE_EDGE_BOTH: 213 irqc = PORT_INT_EITHER_EDGE; 214 break; 215 case IRQ_TYPE_LEVEL_LOW: 216 irqc = PORT_INT_LOGIC_ZERO; 217 break; 218 case IRQ_TYPE_LEVEL_HIGH: 219 irqc = PORT_INT_LOGIC_ONE; 220 break; 221 default: 222 return -EINVAL; 223 } 224 225 port->irqc[d->hwirq] = irqc; 226 227 if (type & IRQ_TYPE_LEVEL_MASK) 228 irq_set_handler_locked(d, handle_level_irq); 229 else 230 irq_set_handler_locked(d, handle_edge_irq); 231 232 return 0; 233 } 234 235 static void vf610_gpio_irq_mask(struct irq_data *d) 236 { 237 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 238 struct vf610_gpio_port *port = gpiochip_get_data(gc); 239 irq_hw_number_t gpio_num = irqd_to_hwirq(d); 240 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 241 242 vf610_gpio_writel(0, pcr_base); 243 gpiochip_disable_irq(gc, gpio_num); 244 } 245 246 static void vf610_gpio_irq_unmask(struct irq_data *d) 247 { 248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 249 struct vf610_gpio_port *port = gpiochip_get_data(gc); 250 irq_hw_number_t gpio_num = irqd_to_hwirq(d); 251 void __iomem *pcr_base = port->base + PORT_PCR(gpio_num); 252 253 gpiochip_enable_irq(gc, gpio_num); 254 vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET, 255 pcr_base); 256 } 257 258 static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable) 259 { 260 struct vf610_gpio_port *port = 261 gpiochip_get_data(irq_data_get_irq_chip_data(d)); 262 263 if (enable) 264 enable_irq_wake(port->irq); 265 else 266 disable_irq_wake(port->irq); 267 268 return 0; 269 } 270 271 static const struct irq_chip vf610_irqchip = { 272 .name = "gpio-vf610", 273 .irq_ack = vf610_gpio_irq_ack, 274 .irq_mask = vf610_gpio_irq_mask, 275 .irq_unmask = vf610_gpio_irq_unmask, 276 .irq_set_type = vf610_gpio_irq_set_type, 277 .irq_set_wake = vf610_gpio_irq_set_wake, 278 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND 279 | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 280 GPIOCHIP_IRQ_RESOURCE_HELPERS, 281 }; 282 283 static void vf610_gpio_disable_clk(void *data) 284 { 285 clk_disable_unprepare(data); 286 } 287 288 static int vf610_gpio_probe(struct platform_device *pdev) 289 { 290 struct device *dev = &pdev->dev; 291 struct vf610_gpio_port *port; 292 struct gpio_chip *gc; 293 struct gpio_irq_chip *girq; 294 int i; 295 int ret; 296 bool dual_base; 297 298 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 299 if (!port) 300 return -ENOMEM; 301 302 port->sdata = device_get_match_data(dev); 303 spin_lock_init(&port->lock); 304 305 dual_base = port->sdata->have_dual_base; 306 307 /* 308 * Handle legacy compatible combinations which used two reg values 309 * for the i.MX8ULP and i.MX93. 310 */ 311 if (device_is_compatible(dev, "fsl,imx7ulp-gpio") && 312 (device_is_compatible(dev, "fsl,imx93-gpio") || 313 (device_is_compatible(dev, "fsl,imx8ulp-gpio")))) 314 dual_base = true; 315 316 if (dual_base) { 317 port->base = devm_platform_ioremap_resource(pdev, 0); 318 if (IS_ERR(port->base)) 319 return PTR_ERR(port->base); 320 321 port->gpio_base = devm_platform_ioremap_resource(pdev, 1); 322 if (IS_ERR(port->gpio_base)) 323 return PTR_ERR(port->gpio_base); 324 } else { 325 port->base = devm_platform_ioremap_resource(pdev, 0); 326 if (IS_ERR(port->base)) 327 return PTR_ERR(port->base); 328 329 port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF; 330 port->base = port->base + IMX8ULP_BASE_OFF; 331 } 332 333 port->irq = platform_get_irq(pdev, 0); 334 if (port->irq < 0) 335 return port->irq; 336 337 port->clk_port = devm_clk_get(dev, "port"); 338 ret = PTR_ERR_OR_ZERO(port->clk_port); 339 if (!ret) { 340 ret = clk_prepare_enable(port->clk_port); 341 if (ret) 342 return ret; 343 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 344 port->clk_port); 345 if (ret) 346 return ret; 347 } else if (ret == -EPROBE_DEFER) { 348 /* 349 * Percolate deferrals, for anything else, 350 * just live without the clocking. 351 */ 352 return ret; 353 } 354 355 port->clk_gpio = devm_clk_get(dev, "gpio"); 356 ret = PTR_ERR_OR_ZERO(port->clk_gpio); 357 if (!ret) { 358 ret = clk_prepare_enable(port->clk_gpio); 359 if (ret) 360 return ret; 361 ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk, 362 port->clk_gpio); 363 if (ret) 364 return ret; 365 } else if (ret == -EPROBE_DEFER) { 366 return ret; 367 } 368 369 gc = &port->gc; 370 gc->parent = dev; 371 gc->label = dev_name(dev); 372 gc->ngpio = VF610_GPIO_PER_PORT; 373 gc->base = -1; 374 375 gc->request = gpiochip_generic_request; 376 gc->free = gpiochip_generic_free; 377 gc->direction_input = vf610_gpio_direction_input; 378 gc->get = vf610_gpio_get; 379 gc->direction_output = vf610_gpio_direction_output; 380 gc->set = vf610_gpio_set; 381 /* 382 * only IP has Port Data Direction Register(PDDR) can 383 * support get direction 384 */ 385 if (port->sdata->have_paddr) 386 gc->get_direction = vf610_gpio_get_direction; 387 388 /* Mask all GPIO interrupts */ 389 for (i = 0; i < gc->ngpio; i++) 390 vf610_gpio_writel(0, port->base + PORT_PCR(i)); 391 392 /* Clear the interrupt status register for all GPIO's */ 393 vf610_gpio_writel(~0, port->base + PORT_ISFR); 394 395 girq = &gc->irq; 396 gpio_irq_chip_set_chip(girq, &vf610_irqchip); 397 girq->parent_handler = vf610_gpio_irq_handler; 398 girq->num_parents = 1; 399 girq->parents = devm_kcalloc(&pdev->dev, 1, 400 sizeof(*girq->parents), 401 GFP_KERNEL); 402 if (!girq->parents) 403 return -ENOMEM; 404 girq->parents[0] = port->irq; 405 girq->default_type = IRQ_TYPE_NONE; 406 girq->handler = handle_edge_irq; 407 408 return devm_gpiochip_add_data(dev, gc, port); 409 } 410 411 static struct platform_driver vf610_gpio_driver = { 412 .driver = { 413 .name = "gpio-vf610", 414 .of_match_table = vf610_gpio_dt_ids, 415 }, 416 .probe = vf610_gpio_probe, 417 }; 418 419 builtin_platform_driver(vf610_gpio_driver); 420