1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (C) 2017 Socionext Inc. 4 // Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 6 #include <linux/bits.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/irq.h> 9 #include <linux/irqdomain.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/spinlock.h> 16 #include <dt-bindings/gpio/uniphier-gpio.h> 17 18 #define UNIPHIER_GPIO_BANK_MASK \ 19 GENMASK((UNIPHIER_GPIO_LINES_PER_BANK) - 1, 0) 20 21 #define UNIPHIER_GPIO_IRQ_MAX_NUM 24 22 23 #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */ 24 #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */ 25 #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */ 26 #define UNIPHIER_GPIO_IRQ_MODE 0x94 /* irq mode (1: both edge) */ 27 #define UNIPHIER_GPIO_IRQ_FLT_EN 0x98 /* noise filter enable */ 28 #define UNIPHIER_GPIO_IRQ_FLT_CYC 0x9c /* noise filter clock cycle */ 29 30 struct uniphier_gpio_priv { 31 struct gpio_chip chip; 32 struct irq_chip irq_chip; 33 struct irq_domain *domain; 34 void __iomem *regs; 35 spinlock_t lock; 36 u32 saved_vals[0]; 37 }; 38 39 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) 40 { 41 unsigned int reg; 42 43 reg = (bank + 1) * 8; 44 45 /* 46 * Unfortunately, the GPIO port registers are not contiguous because 47 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region. 48 */ 49 if (reg >= UNIPHIER_GPIO_IRQ_EN) 50 reg += 0x10; 51 52 return reg; 53 } 54 55 static void uniphier_gpio_get_bank_and_mask(unsigned int offset, 56 unsigned int *bank, u32 *mask) 57 { 58 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK; 59 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK); 60 } 61 62 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv, 63 unsigned int reg, u32 mask, u32 val) 64 { 65 unsigned long flags; 66 u32 tmp; 67 68 spin_lock_irqsave(&priv->lock, flags); 69 tmp = readl(priv->regs + reg); 70 tmp &= ~mask; 71 tmp |= mask & val; 72 writel(tmp, priv->regs + reg); 73 spin_unlock_irqrestore(&priv->lock, flags); 74 } 75 76 static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, 77 unsigned int reg, u32 mask, u32 val) 78 { 79 struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); 80 81 if (!mask) 82 return; 83 84 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg, 85 mask, val); 86 } 87 88 static void uniphier_gpio_offset_write(struct gpio_chip *chip, 89 unsigned int offset, unsigned int reg, 90 int val) 91 { 92 unsigned int bank; 93 u32 mask; 94 95 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); 96 97 uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0); 98 } 99 100 static int uniphier_gpio_offset_read(struct gpio_chip *chip, 101 unsigned int offset, unsigned int reg) 102 { 103 struct uniphier_gpio_priv *priv = gpiochip_get_data(chip); 104 unsigned int bank, reg_offset; 105 u32 mask; 106 107 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask); 108 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg; 109 110 return !!(readl(priv->regs + reg_offset) & mask); 111 } 112 113 static int uniphier_gpio_get_direction(struct gpio_chip *chip, 114 unsigned int offset) 115 { 116 if (uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DIR)) 117 return GPIO_LINE_DIRECTION_IN; 118 119 return GPIO_LINE_DIRECTION_OUT; 120 } 121 122 static int uniphier_gpio_direction_input(struct gpio_chip *chip, 123 unsigned int offset) 124 { 125 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 1); 126 127 return 0; 128 } 129 130 static int uniphier_gpio_direction_output(struct gpio_chip *chip, 131 unsigned int offset, int val) 132 { 133 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); 134 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DIR, 0); 135 136 return 0; 137 } 138 139 static int uniphier_gpio_get(struct gpio_chip *chip, unsigned int offset) 140 { 141 return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_PORT_DATA); 142 } 143 144 static void uniphier_gpio_set(struct gpio_chip *chip, 145 unsigned int offset, int val) 146 { 147 uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_PORT_DATA, val); 148 } 149 150 static void uniphier_gpio_set_multiple(struct gpio_chip *chip, 151 unsigned long *mask, unsigned long *bits) 152 { 153 unsigned int bank, shift, bank_mask, bank_bits; 154 int i; 155 156 for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_LINES_PER_BANK) { 157 bank = i / UNIPHIER_GPIO_LINES_PER_BANK; 158 shift = i % BITS_PER_LONG; 159 bank_mask = (mask[BIT_WORD(i)] >> shift) & 160 UNIPHIER_GPIO_BANK_MASK; 161 bank_bits = bits[BIT_WORD(i)] >> shift; 162 163 uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_PORT_DATA, 164 bank_mask, bank_bits); 165 } 166 } 167 168 static int uniphier_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 169 { 170 struct irq_fwspec fwspec; 171 172 if (offset < UNIPHIER_GPIO_IRQ_OFFSET) 173 return -ENXIO; 174 175 fwspec.fwnode = of_node_to_fwnode(chip->parent->of_node); 176 fwspec.param_count = 2; 177 fwspec.param[0] = offset - UNIPHIER_GPIO_IRQ_OFFSET; 178 /* 179 * IRQ_TYPE_NONE is rejected by the parent irq domain. Set LEVEL_HIGH 180 * temporarily. Anyway, ->irq_set_type() will override it later. 181 */ 182 fwspec.param[1] = IRQ_TYPE_LEVEL_HIGH; 183 184 return irq_create_fwspec_mapping(&fwspec); 185 } 186 187 static void uniphier_gpio_irq_mask(struct irq_data *data) 188 { 189 struct uniphier_gpio_priv *priv = data->chip_data; 190 u32 mask = BIT(data->hwirq); 191 192 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, 0); 193 194 return irq_chip_mask_parent(data); 195 } 196 197 static void uniphier_gpio_irq_unmask(struct irq_data *data) 198 { 199 struct uniphier_gpio_priv *priv = data->chip_data; 200 u32 mask = BIT(data->hwirq); 201 202 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_EN, mask, mask); 203 204 return irq_chip_unmask_parent(data); 205 } 206 207 static int uniphier_gpio_irq_set_type(struct irq_data *data, unsigned int type) 208 { 209 struct uniphier_gpio_priv *priv = data->chip_data; 210 u32 mask = BIT(data->hwirq); 211 u32 val = 0; 212 213 if (type == IRQ_TYPE_EDGE_BOTH) { 214 val = mask; 215 type = IRQ_TYPE_EDGE_FALLING; 216 } 217 218 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_MODE, mask, val); 219 /* To enable both edge detection, the noise filter must be enabled. */ 220 uniphier_gpio_reg_update(priv, UNIPHIER_GPIO_IRQ_FLT_EN, mask, val); 221 222 return irq_chip_set_type_parent(data, type); 223 } 224 225 static int uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv, 226 unsigned int hwirq) 227 { 228 struct device_node *np = priv->chip.parent->of_node; 229 const __be32 *range; 230 u32 base, parent_base, size; 231 int len; 232 233 range = of_get_property(np, "socionext,interrupt-ranges", &len); 234 if (!range) 235 return -EINVAL; 236 237 len /= sizeof(*range); 238 239 for (; len >= 3; len -= 3) { 240 base = be32_to_cpu(*range++); 241 parent_base = be32_to_cpu(*range++); 242 size = be32_to_cpu(*range++); 243 244 if (base <= hwirq && hwirq < base + size) 245 return hwirq - base + parent_base; 246 } 247 248 return -ENOENT; 249 } 250 251 static int uniphier_gpio_irq_domain_translate(struct irq_domain *domain, 252 struct irq_fwspec *fwspec, 253 unsigned long *out_hwirq, 254 unsigned int *out_type) 255 { 256 if (WARN_ON(fwspec->param_count < 2)) 257 return -EINVAL; 258 259 *out_hwirq = fwspec->param[0]; 260 *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 261 262 return 0; 263 } 264 265 static int uniphier_gpio_irq_domain_alloc(struct irq_domain *domain, 266 unsigned int virq, 267 unsigned int nr_irqs, void *arg) 268 { 269 struct uniphier_gpio_priv *priv = domain->host_data; 270 struct irq_fwspec parent_fwspec; 271 irq_hw_number_t hwirq; 272 unsigned int type; 273 int ret; 274 275 if (WARN_ON(nr_irqs != 1)) 276 return -EINVAL; 277 278 ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type); 279 if (ret) 280 return ret; 281 282 ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq); 283 if (ret < 0) 284 return ret; 285 286 /* parent is UniPhier AIDET */ 287 parent_fwspec.fwnode = domain->parent->fwnode; 288 parent_fwspec.param_count = 2; 289 parent_fwspec.param[0] = ret; 290 parent_fwspec.param[1] = (type == IRQ_TYPE_EDGE_BOTH) ? 291 IRQ_TYPE_EDGE_FALLING : type; 292 293 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 294 &priv->irq_chip, priv); 295 if (ret) 296 return ret; 297 298 return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); 299 } 300 301 static int uniphier_gpio_irq_domain_activate(struct irq_domain *domain, 302 struct irq_data *data, bool early) 303 { 304 struct uniphier_gpio_priv *priv = domain->host_data; 305 struct gpio_chip *chip = &priv->chip; 306 307 return gpiochip_lock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); 308 } 309 310 static void uniphier_gpio_irq_domain_deactivate(struct irq_domain *domain, 311 struct irq_data *data) 312 { 313 struct uniphier_gpio_priv *priv = domain->host_data; 314 struct gpio_chip *chip = &priv->chip; 315 316 gpiochip_unlock_as_irq(chip, data->hwirq + UNIPHIER_GPIO_IRQ_OFFSET); 317 } 318 319 static const struct irq_domain_ops uniphier_gpio_irq_domain_ops = { 320 .alloc = uniphier_gpio_irq_domain_alloc, 321 .free = irq_domain_free_irqs_common, 322 .activate = uniphier_gpio_irq_domain_activate, 323 .deactivate = uniphier_gpio_irq_domain_deactivate, 324 .translate = uniphier_gpio_irq_domain_translate, 325 }; 326 327 static void uniphier_gpio_hw_init(struct uniphier_gpio_priv *priv) 328 { 329 /* 330 * Due to the hardware design, the noise filter must be enabled to 331 * detect both edge interrupts. This filter is intended to remove the 332 * noise from the irq lines. It does not work for GPIO input, so GPIO 333 * debounce is not supported. Unfortunately, the filter period is 334 * shared among all irq lines. Just choose a sensible period here. 335 */ 336 writel(0xff, priv->regs + UNIPHIER_GPIO_IRQ_FLT_CYC); 337 } 338 339 static unsigned int uniphier_gpio_get_nbanks(unsigned int ngpio) 340 { 341 return DIV_ROUND_UP(ngpio, UNIPHIER_GPIO_LINES_PER_BANK); 342 } 343 344 static int uniphier_gpio_probe(struct platform_device *pdev) 345 { 346 struct device *dev = &pdev->dev; 347 struct device_node *parent_np; 348 struct irq_domain *parent_domain; 349 struct uniphier_gpio_priv *priv; 350 struct gpio_chip *chip; 351 struct irq_chip *irq_chip; 352 unsigned int nregs; 353 u32 ngpios; 354 int ret; 355 356 parent_np = of_irq_find_parent(dev->of_node); 357 if (!parent_np) 358 return -ENXIO; 359 360 parent_domain = irq_find_host(parent_np); 361 of_node_put(parent_np); 362 if (!parent_domain) 363 return -EPROBE_DEFER; 364 365 ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios); 366 if (ret) 367 return ret; 368 369 nregs = uniphier_gpio_get_nbanks(ngpios) * 2 + 3; 370 priv = devm_kzalloc(dev, struct_size(priv, saved_vals, nregs), 371 GFP_KERNEL); 372 if (!priv) 373 return -ENOMEM; 374 375 priv->regs = devm_platform_ioremap_resource(pdev, 0); 376 if (IS_ERR(priv->regs)) 377 return PTR_ERR(priv->regs); 378 379 spin_lock_init(&priv->lock); 380 381 chip = &priv->chip; 382 chip->label = dev_name(dev); 383 chip->parent = dev; 384 chip->request = gpiochip_generic_request; 385 chip->free = gpiochip_generic_free; 386 chip->get_direction = uniphier_gpio_get_direction; 387 chip->direction_input = uniphier_gpio_direction_input; 388 chip->direction_output = uniphier_gpio_direction_output; 389 chip->get = uniphier_gpio_get; 390 chip->set = uniphier_gpio_set; 391 chip->set_multiple = uniphier_gpio_set_multiple; 392 chip->to_irq = uniphier_gpio_to_irq; 393 chip->base = -1; 394 chip->ngpio = ngpios; 395 396 irq_chip = &priv->irq_chip; 397 irq_chip->name = dev_name(dev); 398 irq_chip->irq_mask = uniphier_gpio_irq_mask; 399 irq_chip->irq_unmask = uniphier_gpio_irq_unmask; 400 irq_chip->irq_eoi = irq_chip_eoi_parent; 401 irq_chip->irq_set_affinity = irq_chip_set_affinity_parent; 402 irq_chip->irq_set_type = uniphier_gpio_irq_set_type; 403 404 uniphier_gpio_hw_init(priv); 405 406 ret = devm_gpiochip_add_data(dev, chip, priv); 407 if (ret) 408 return ret; 409 410 priv->domain = irq_domain_create_hierarchy( 411 parent_domain, 0, 412 UNIPHIER_GPIO_IRQ_MAX_NUM, 413 of_node_to_fwnode(dev->of_node), 414 &uniphier_gpio_irq_domain_ops, priv); 415 if (!priv->domain) 416 return -ENOMEM; 417 418 platform_set_drvdata(pdev, priv); 419 420 return 0; 421 } 422 423 static int uniphier_gpio_remove(struct platform_device *pdev) 424 { 425 struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); 426 427 irq_domain_remove(priv->domain); 428 429 return 0; 430 } 431 432 static int __maybe_unused uniphier_gpio_suspend(struct device *dev) 433 { 434 struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); 435 unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); 436 u32 *val = priv->saved_vals; 437 unsigned int reg; 438 int i; 439 440 for (i = 0; i < nbanks; i++) { 441 reg = uniphier_gpio_bank_to_reg(i); 442 443 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); 444 *val++ = readl(priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); 445 } 446 447 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_EN); 448 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_MODE); 449 *val++ = readl(priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); 450 451 return 0; 452 } 453 454 static int __maybe_unused uniphier_gpio_resume(struct device *dev) 455 { 456 struct uniphier_gpio_priv *priv = dev_get_drvdata(dev); 457 unsigned int nbanks = uniphier_gpio_get_nbanks(priv->chip.ngpio); 458 const u32 *val = priv->saved_vals; 459 unsigned int reg; 460 int i; 461 462 for (i = 0; i < nbanks; i++) { 463 reg = uniphier_gpio_bank_to_reg(i); 464 465 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DATA); 466 writel(*val++, priv->regs + reg + UNIPHIER_GPIO_PORT_DIR); 467 } 468 469 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_EN); 470 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_MODE); 471 writel(*val++, priv->regs + UNIPHIER_GPIO_IRQ_FLT_EN); 472 473 uniphier_gpio_hw_init(priv); 474 475 return 0; 476 } 477 478 static const struct dev_pm_ops uniphier_gpio_pm_ops = { 479 SET_LATE_SYSTEM_SLEEP_PM_OPS(uniphier_gpio_suspend, 480 uniphier_gpio_resume) 481 }; 482 483 static const struct of_device_id uniphier_gpio_match[] = { 484 { .compatible = "socionext,uniphier-gpio" }, 485 { /* sentinel */ } 486 }; 487 MODULE_DEVICE_TABLE(of, uniphier_gpio_match); 488 489 static struct platform_driver uniphier_gpio_driver = { 490 .probe = uniphier_gpio_probe, 491 .remove = uniphier_gpio_remove, 492 .driver = { 493 .name = "uniphier-gpio", 494 .of_match_table = uniphier_gpio_match, 495 .pm = &uniphier_gpio_pm_ops, 496 }, 497 }; 498 module_platform_driver(uniphier_gpio_driver); 499 500 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); 501 MODULE_DESCRIPTION("UniPhier GPIO driver"); 502 MODULE_LICENSE("GPL v2"); 503