1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2016, 2017 Cavium Inc. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/spinlock.h> 18 19 20 #define GPIO_RX_DAT 0x0 21 #define GPIO_TX_SET 0x8 22 #define GPIO_TX_CLR 0x10 23 #define GPIO_CONST 0x90 24 #define GPIO_CONST_GPIOS_MASK 0xff 25 #define GPIO_BIT_CFG 0x400 26 #define GPIO_BIT_CFG_TX_OE BIT(0) 27 #define GPIO_BIT_CFG_PIN_XOR BIT(1) 28 #define GPIO_BIT_CFG_INT_EN BIT(2) 29 #define GPIO_BIT_CFG_INT_TYPE BIT(3) 30 #define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4) 31 #define GPIO_BIT_CFG_FIL_CNT_SHIFT 4 32 #define GPIO_BIT_CFG_FIL_SEL_SHIFT 8 33 #define GPIO_BIT_CFG_TX_OD BIT(12) 34 #define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16) 35 #define GPIO_INTR 0x800 36 #define GPIO_INTR_INTR BIT(0) 37 #define GPIO_INTR_INTR_W1S BIT(1) 38 #define GPIO_INTR_ENA_W1C BIT(2) 39 #define GPIO_INTR_ENA_W1S BIT(3) 40 #define GPIO_2ND_BANK 0x1400 41 42 #define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \ 43 (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT)) 44 45 struct thunderx_gpio; 46 47 struct thunderx_line { 48 struct thunderx_gpio *txgpio; 49 unsigned int line; 50 unsigned int fil_bits; 51 }; 52 53 struct thunderx_gpio { 54 struct gpio_chip chip; 55 u8 __iomem *register_base; 56 struct irq_domain *irqd; 57 struct msix_entry *msix_entries; /* per line MSI-X */ 58 struct thunderx_line *line_entries; /* per line irq info */ 59 raw_spinlock_t lock; 60 unsigned long invert_mask[2]; 61 unsigned long od_mask[2]; 62 int base_msi; 63 }; 64 65 static unsigned int bit_cfg_reg(unsigned int line) 66 { 67 return 8 * line + GPIO_BIT_CFG; 68 } 69 70 static unsigned int intr_reg(unsigned int line) 71 { 72 return 8 * line + GPIO_INTR; 73 } 74 75 static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio, 76 unsigned int line) 77 { 78 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 79 80 return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0; 81 } 82 83 /* 84 * Check (and WARN) that the pin is available for GPIO. We will not 85 * allow modification of the state of non-GPIO pins from this driver. 86 */ 87 static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio, 88 unsigned int line) 89 { 90 bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line); 91 92 WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line); 93 94 return rv; 95 } 96 97 static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line) 98 { 99 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 100 101 return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO; 102 } 103 104 static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line) 105 { 106 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 107 108 if (!thunderx_gpio_is_gpio(txgpio, line)) 109 return -EIO; 110 111 raw_spin_lock(&txgpio->lock); 112 clear_bit(line, txgpio->invert_mask); 113 clear_bit(line, txgpio->od_mask); 114 writeq(txgpio->line_entries[line].fil_bits, 115 txgpio->register_base + bit_cfg_reg(line)); 116 raw_spin_unlock(&txgpio->lock); 117 return 0; 118 } 119 120 static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line, 121 int value) 122 { 123 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 124 int bank = line / 64; 125 int bank_bit = line % 64; 126 127 void __iomem *reg = txgpio->register_base + 128 (bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR); 129 130 writeq(BIT_ULL(bank_bit), reg); 131 } 132 133 static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line, 134 int value) 135 { 136 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 137 u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE; 138 139 if (!thunderx_gpio_is_gpio(txgpio, line)) 140 return -EIO; 141 142 raw_spin_lock(&txgpio->lock); 143 144 thunderx_gpio_set(chip, line, value); 145 146 if (test_bit(line, txgpio->invert_mask)) 147 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 148 149 if (test_bit(line, txgpio->od_mask)) 150 bit_cfg |= GPIO_BIT_CFG_TX_OD; 151 152 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 153 154 raw_spin_unlock(&txgpio->lock); 155 return 0; 156 } 157 158 static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line) 159 { 160 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 161 u64 bit_cfg; 162 163 if (!thunderx_gpio_is_gpio_nowarn(txgpio, line)) 164 /* 165 * Say it is input for now to avoid WARNing on 166 * gpiochip_add_data(). We will WARN if someone 167 * requests it or tries to use it. 168 */ 169 return 1; 170 171 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 172 173 if (bit_cfg & GPIO_BIT_CFG_TX_OE) 174 return GPIO_LINE_DIRECTION_OUT; 175 176 return GPIO_LINE_DIRECTION_IN; 177 } 178 179 static int thunderx_gpio_set_config(struct gpio_chip *chip, 180 unsigned int line, 181 unsigned long cfg) 182 { 183 bool orig_invert, orig_od, orig_dat, new_invert, new_od; 184 u32 arg, sel; 185 u64 bit_cfg; 186 int bank = line / 64; 187 int bank_bit = line % 64; 188 int ret = -ENOTSUPP; 189 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 190 void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET; 191 192 if (!thunderx_gpio_is_gpio(txgpio, line)) 193 return -EIO; 194 195 raw_spin_lock(&txgpio->lock); 196 orig_invert = test_bit(line, txgpio->invert_mask); 197 new_invert = orig_invert; 198 orig_od = test_bit(line, txgpio->od_mask); 199 new_od = orig_od; 200 orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert; 201 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line)); 202 switch (pinconf_to_config_param(cfg)) { 203 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 204 /* 205 * Weird, setting open-drain mode causes signal 206 * inversion. Note this so we can compensate in the 207 * dir_out function. 208 */ 209 set_bit(line, txgpio->invert_mask); 210 new_invert = true; 211 set_bit(line, txgpio->od_mask); 212 new_od = true; 213 ret = 0; 214 break; 215 case PIN_CONFIG_DRIVE_PUSH_PULL: 216 clear_bit(line, txgpio->invert_mask); 217 new_invert = false; 218 clear_bit(line, txgpio->od_mask); 219 new_od = false; 220 ret = 0; 221 break; 222 case PIN_CONFIG_INPUT_DEBOUNCE: 223 arg = pinconf_to_config_argument(cfg); 224 if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */ 225 ret = -EINVAL; 226 break; 227 } 228 arg *= 400; /* scale to 2.5nS clocks. */ 229 sel = 0; 230 while (arg > 15) { 231 sel++; 232 arg++; /* always round up */ 233 arg >>= 1; 234 } 235 txgpio->line_entries[line].fil_bits = 236 (sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) | 237 (arg << GPIO_BIT_CFG_FIL_CNT_SHIFT); 238 bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK; 239 bit_cfg |= txgpio->line_entries[line].fil_bits; 240 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line)); 241 ret = 0; 242 break; 243 default: 244 break; 245 } 246 raw_spin_unlock(&txgpio->lock); 247 248 /* 249 * If currently output and OPEN_DRAIN changed, install the new 250 * settings 251 */ 252 if ((new_invert != orig_invert || new_od != orig_od) && 253 (bit_cfg & GPIO_BIT_CFG_TX_OE)) 254 ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert); 255 256 return ret; 257 } 258 259 static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line) 260 { 261 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 262 int bank = line / 64; 263 int bank_bit = line % 64; 264 u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT); 265 u64 masked_bits = read_bits & BIT_ULL(bank_bit); 266 267 if (test_bit(line, txgpio->invert_mask)) 268 return masked_bits == 0; 269 else 270 return masked_bits != 0; 271 } 272 273 static void thunderx_gpio_set_multiple(struct gpio_chip *chip, 274 unsigned long *mask, 275 unsigned long *bits) 276 { 277 int bank; 278 u64 set_bits, clear_bits; 279 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 280 281 for (bank = 0; bank <= chip->ngpio / 64; bank++) { 282 set_bits = bits[bank] & mask[bank]; 283 clear_bits = ~bits[bank] & mask[bank]; 284 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); 285 writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); 286 } 287 } 288 289 static void thunderx_gpio_irq_ack(struct irq_data *data) 290 { 291 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 292 293 writeq(GPIO_INTR_INTR, 294 txline->txgpio->register_base + intr_reg(txline->line)); 295 } 296 297 static void thunderx_gpio_irq_mask(struct irq_data *data) 298 { 299 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 300 301 writeq(GPIO_INTR_ENA_W1C, 302 txline->txgpio->register_base + intr_reg(txline->line)); 303 } 304 305 static void thunderx_gpio_irq_mask_ack(struct irq_data *data) 306 { 307 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 308 309 writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR, 310 txline->txgpio->register_base + intr_reg(txline->line)); 311 } 312 313 static void thunderx_gpio_irq_unmask(struct irq_data *data) 314 { 315 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 316 317 writeq(GPIO_INTR_ENA_W1S, 318 txline->txgpio->register_base + intr_reg(txline->line)); 319 } 320 321 static int thunderx_gpio_irq_set_type(struct irq_data *data, 322 unsigned int flow_type) 323 { 324 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 325 struct thunderx_gpio *txgpio = txline->txgpio; 326 u64 bit_cfg; 327 328 irqd_set_trigger_type(data, flow_type); 329 330 bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN; 331 332 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 333 irq_set_handler_locked(data, handle_fasteoi_ack_irq); 334 bit_cfg |= GPIO_BIT_CFG_INT_TYPE; 335 } else { 336 irq_set_handler_locked(data, handle_fasteoi_mask_irq); 337 } 338 339 raw_spin_lock(&txgpio->lock); 340 if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) { 341 bit_cfg |= GPIO_BIT_CFG_PIN_XOR; 342 set_bit(txline->line, txgpio->invert_mask); 343 } else { 344 clear_bit(txline->line, txgpio->invert_mask); 345 } 346 clear_bit(txline->line, txgpio->od_mask); 347 writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line)); 348 raw_spin_unlock(&txgpio->lock); 349 350 return IRQ_SET_MASK_OK; 351 } 352 353 static void thunderx_gpio_irq_enable(struct irq_data *data) 354 { 355 irq_chip_enable_parent(data); 356 thunderx_gpio_irq_unmask(data); 357 } 358 359 static void thunderx_gpio_irq_disable(struct irq_data *data) 360 { 361 thunderx_gpio_irq_mask(data); 362 irq_chip_disable_parent(data); 363 } 364 365 static int thunderx_gpio_irq_request_resources(struct irq_data *data) 366 { 367 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 368 struct thunderx_gpio *txgpio = txline->txgpio; 369 int r; 370 371 r = gpiochip_lock_as_irq(&txgpio->chip, txline->line); 372 if (r) 373 return r; 374 375 r = irq_chip_request_resources_parent(data); 376 if (r) 377 gpiochip_unlock_as_irq(&txgpio->chip, txline->line); 378 379 return r; 380 } 381 382 static void thunderx_gpio_irq_release_resources(struct irq_data *data) 383 { 384 struct thunderx_line *txline = irq_data_get_irq_chip_data(data); 385 struct thunderx_gpio *txgpio = txline->txgpio; 386 387 irq_chip_release_resources_parent(data); 388 389 gpiochip_unlock_as_irq(&txgpio->chip, txline->line); 390 } 391 392 /* 393 * Interrupts are chained from underlying MSI-X vectors. We have 394 * these irq_chip functions to be able to handle level triggering 395 * semantics and other acknowledgment tasks associated with the GPIO 396 * mechanism. 397 */ 398 static struct irq_chip thunderx_gpio_irq_chip = { 399 .name = "GPIO", 400 .irq_enable = thunderx_gpio_irq_enable, 401 .irq_disable = thunderx_gpio_irq_disable, 402 .irq_ack = thunderx_gpio_irq_ack, 403 .irq_mask = thunderx_gpio_irq_mask, 404 .irq_mask_ack = thunderx_gpio_irq_mask_ack, 405 .irq_unmask = thunderx_gpio_irq_unmask, 406 .irq_eoi = irq_chip_eoi_parent, 407 .irq_set_affinity = irq_chip_set_affinity_parent, 408 .irq_request_resources = thunderx_gpio_irq_request_resources, 409 .irq_release_resources = thunderx_gpio_irq_release_resources, 410 .irq_set_type = thunderx_gpio_irq_set_type, 411 412 .flags = IRQCHIP_SET_TYPE_MASKED 413 }; 414 415 static int thunderx_gpio_irq_translate(struct irq_domain *d, 416 struct irq_fwspec *fwspec, 417 irq_hw_number_t *hwirq, 418 unsigned int *type) 419 { 420 struct thunderx_gpio *txgpio = d->host_data; 421 422 if (WARN_ON(fwspec->param_count < 2)) 423 return -EINVAL; 424 if (fwspec->param[0] >= txgpio->chip.ngpio) 425 return -EINVAL; 426 *hwirq = fwspec->param[0]; 427 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 428 return 0; 429 } 430 431 static int thunderx_gpio_irq_alloc(struct irq_domain *d, unsigned int virq, 432 unsigned int nr_irqs, void *arg) 433 { 434 struct thunderx_line *txline = arg; 435 436 return irq_domain_set_hwirq_and_chip(d, virq, txline->line, 437 &thunderx_gpio_irq_chip, txline); 438 } 439 440 static const struct irq_domain_ops thunderx_gpio_irqd_ops = { 441 .alloc = thunderx_gpio_irq_alloc, 442 .translate = thunderx_gpio_irq_translate 443 }; 444 445 static int thunderx_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) 446 { 447 struct thunderx_gpio *txgpio = gpiochip_get_data(chip); 448 449 return irq_find_mapping(txgpio->irqd, offset); 450 } 451 452 static int thunderx_gpio_probe(struct pci_dev *pdev, 453 const struct pci_device_id *id) 454 { 455 void __iomem * const *tbl; 456 struct device *dev = &pdev->dev; 457 struct thunderx_gpio *txgpio; 458 struct gpio_chip *chip; 459 int ngpio, i; 460 int err = 0; 461 462 txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL); 463 if (!txgpio) 464 return -ENOMEM; 465 466 raw_spin_lock_init(&txgpio->lock); 467 chip = &txgpio->chip; 468 469 pci_set_drvdata(pdev, txgpio); 470 471 err = pcim_enable_device(pdev); 472 if (err) { 473 dev_err(dev, "Failed to enable PCI device: err %d\n", err); 474 goto out; 475 } 476 477 err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME); 478 if (err) { 479 dev_err(dev, "Failed to iomap PCI device: err %d\n", err); 480 goto out; 481 } 482 483 tbl = pcim_iomap_table(pdev); 484 txgpio->register_base = tbl[0]; 485 if (!txgpio->register_base) { 486 dev_err(dev, "Cannot map PCI resource\n"); 487 err = -ENOMEM; 488 goto out; 489 } 490 491 if (pdev->subsystem_device == 0xa10a) { 492 /* CN88XX has no GPIO_CONST register*/ 493 ngpio = 50; 494 txgpio->base_msi = 48; 495 } else { 496 u64 c = readq(txgpio->register_base + GPIO_CONST); 497 498 ngpio = c & GPIO_CONST_GPIOS_MASK; 499 txgpio->base_msi = (c >> 8) & 0xff; 500 } 501 502 txgpio->msix_entries = devm_kcalloc(dev, 503 ngpio, sizeof(struct msix_entry), 504 GFP_KERNEL); 505 if (!txgpio->msix_entries) { 506 err = -ENOMEM; 507 goto out; 508 } 509 510 txgpio->line_entries = devm_kcalloc(dev, 511 ngpio, 512 sizeof(struct thunderx_line), 513 GFP_KERNEL); 514 if (!txgpio->line_entries) { 515 err = -ENOMEM; 516 goto out; 517 } 518 519 for (i = 0; i < ngpio; i++) { 520 u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i)); 521 522 txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i); 523 txgpio->line_entries[i].line = i; 524 txgpio->line_entries[i].txgpio = txgpio; 525 /* 526 * If something has already programmed the pin, use 527 * the existing glitch filter settings, otherwise go 528 * to 400nS. 529 */ 530 txgpio->line_entries[i].fil_bits = bit_cfg ? 531 (bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS; 532 533 if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD)) 534 set_bit(i, txgpio->od_mask); 535 if (bit_cfg & GPIO_BIT_CFG_PIN_XOR) 536 set_bit(i, txgpio->invert_mask); 537 } 538 539 540 /* Enable all MSI-X for interrupts on all possible lines. */ 541 err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio); 542 if (err < 0) 543 goto out; 544 545 /* 546 * Push GPIO specific irqdomain on hierarchy created as a side 547 * effect of the pci_enable_msix() 548 */ 549 txgpio->irqd = irq_domain_create_hierarchy(irq_get_irq_data(txgpio->msix_entries[0].vector)->domain, 550 0, 0, of_node_to_fwnode(dev->of_node), 551 &thunderx_gpio_irqd_ops, txgpio); 552 if (!txgpio->irqd) { 553 err = -ENOMEM; 554 goto out; 555 } 556 557 /* Push on irq_data and the domain for each line. */ 558 for (i = 0; i < ngpio; i++) { 559 err = irq_domain_push_irq(txgpio->irqd, 560 txgpio->msix_entries[i].vector, 561 &txgpio->line_entries[i]); 562 if (err < 0) 563 dev_err(dev, "irq_domain_push_irq: %d\n", err); 564 } 565 566 chip->label = KBUILD_MODNAME; 567 chip->parent = dev; 568 chip->owner = THIS_MODULE; 569 chip->request = thunderx_gpio_request; 570 chip->base = -1; /* System allocated */ 571 chip->can_sleep = false; 572 chip->ngpio = ngpio; 573 chip->get_direction = thunderx_gpio_get_direction; 574 chip->direction_input = thunderx_gpio_dir_in; 575 chip->get = thunderx_gpio_get; 576 chip->direction_output = thunderx_gpio_dir_out; 577 chip->set = thunderx_gpio_set; 578 chip->set_multiple = thunderx_gpio_set_multiple; 579 chip->set_config = thunderx_gpio_set_config; 580 chip->to_irq = thunderx_gpio_to_irq; 581 err = devm_gpiochip_add_data(dev, chip, txgpio); 582 if (err) 583 goto out; 584 585 dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n", 586 ngpio, chip->base); 587 return 0; 588 out: 589 pci_set_drvdata(pdev, NULL); 590 return err; 591 } 592 593 static void thunderx_gpio_remove(struct pci_dev *pdev) 594 { 595 int i; 596 struct thunderx_gpio *txgpio = pci_get_drvdata(pdev); 597 598 for (i = 0; i < txgpio->chip.ngpio; i++) 599 irq_domain_pop_irq(txgpio->irqd, 600 txgpio->msix_entries[i].vector); 601 602 irq_domain_remove(txgpio->irqd); 603 604 pci_set_drvdata(pdev, NULL); 605 } 606 607 static const struct pci_device_id thunderx_gpio_id_table[] = { 608 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) }, 609 { 0, } /* end of table */ 610 }; 611 612 MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table); 613 614 static struct pci_driver thunderx_gpio_driver = { 615 .name = KBUILD_MODNAME, 616 .id_table = thunderx_gpio_id_table, 617 .probe = thunderx_gpio_probe, 618 .remove = thunderx_gpio_remove, 619 }; 620 621 module_pci_driver(thunderx_gpio_driver); 622 623 MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver"); 624 MODULE_LICENSE("GPL"); 625