1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2026 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/hte.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 19 #include <dt-bindings/gpio/tegra186-gpio.h> 20 #include <dt-bindings/gpio/tegra194-gpio.h> 21 #include <dt-bindings/gpio/tegra234-gpio.h> 22 #include <dt-bindings/gpio/tegra241-gpio.h> 23 #include <dt-bindings/gpio/tegra256-gpio.h> 24 #include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 25 26 /* security registers */ 27 #define TEGRA186_GPIO_CTL_SCR 0x0c 28 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 29 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 30 31 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 32 33 #define TEGRA186_GPIO_VM 0x00 34 #define TEGRA186_GPIO_VM_RW_MASK 0x03 35 #define TEGRA186_GPIO_SCR 0x04 36 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 37 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 38 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) 39 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) 40 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) 41 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) 42 43 /* control registers */ 44 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 45 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 46 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 47 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 48 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 49 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 50 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 51 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 52 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 53 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 54 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 55 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 56 57 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 58 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 59 60 #define TEGRA186_GPIO_INPUT 0x08 61 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 62 63 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 64 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 65 66 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 67 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 68 69 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 70 71 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 72 73 /* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */ 74 #define TEGRA410_COMPUTE_GPIO_PORT_A 0 75 #define TEGRA410_COMPUTE_GPIO_PORT_B 1 76 #define TEGRA410_COMPUTE_GPIO_PORT_C 2 77 #define TEGRA410_COMPUTE_GPIO_PORT_D 3 78 #define TEGRA410_COMPUTE_GPIO_PORT_E 4 79 80 /* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */ 81 #define TEGRA410_SYSTEM_GPIO_PORT_A 0 82 #define TEGRA410_SYSTEM_GPIO_PORT_B 1 83 #define TEGRA410_SYSTEM_GPIO_PORT_C 2 84 #define TEGRA410_SYSTEM_GPIO_PORT_D 3 85 #define TEGRA410_SYSTEM_GPIO_PORT_E 4 86 #define TEGRA410_SYSTEM_GPIO_PORT_I 5 87 #define TEGRA410_SYSTEM_GPIO_PORT_J 6 88 #define TEGRA410_SYSTEM_GPIO_PORT_K 7 89 #define TEGRA410_SYSTEM_GPIO_PORT_L 8 90 #define TEGRA410_SYSTEM_GPIO_PORT_M 9 91 #define TEGRA410_SYSTEM_GPIO_PORT_N 10 92 #define TEGRA410_SYSTEM_GPIO_PORT_P 11 93 #define TEGRA410_SYSTEM_GPIO_PORT_Q 12 94 #define TEGRA410_SYSTEM_GPIO_PORT_R 13 95 #define TEGRA410_SYSTEM_GPIO_PORT_V 14 96 97 struct tegra_gpio_port { 98 const char *name; 99 unsigned int bank; 100 unsigned int port; 101 unsigned int pins; 102 }; 103 104 struct tegra186_pin_range { 105 unsigned int offset; 106 const char *group; 107 }; 108 109 struct tegra_gpio_soc { 110 const struct tegra_gpio_port *ports; 111 unsigned int num_ports; 112 const char *name; 113 const char *prefix; 114 unsigned int instance; 115 116 unsigned int num_irqs_per_bank; 117 118 const struct tegra186_pin_range *pin_ranges; 119 unsigned int num_pin_ranges; 120 const char *pinmux; 121 bool has_gte; 122 bool has_vm_support; 123 }; 124 125 struct tegra_gpio { 126 struct gpio_chip gpio; 127 unsigned int num_irq; 128 unsigned int *irq; 129 130 const struct tegra_gpio_soc *soc; 131 unsigned int num_irqs_per_bank; 132 unsigned int num_banks; 133 134 void __iomem *secure; 135 void __iomem *base; 136 }; 137 138 static const struct tegra_gpio_port * 139 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 140 { 141 unsigned int start = 0, i; 142 143 for (i = 0; i < gpio->soc->num_ports; i++) { 144 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 145 146 if (*pin >= start && *pin < start + port->pins) { 147 *pin -= start; 148 return port; 149 } 150 151 start += port->pins; 152 } 153 154 return NULL; 155 } 156 157 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 158 unsigned int pin) 159 { 160 const struct tegra_gpio_port *port; 161 unsigned int offset; 162 163 port = tegra186_gpio_get_port(gpio, &pin); 164 if (!port) 165 return NULL; 166 167 offset = port->bank * 0x1000 + port->port * 0x200; 168 169 return gpio->base + offset + pin * 0x20; 170 } 171 172 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, 173 unsigned int pin) 174 { 175 const struct tegra_gpio_port *port; 176 unsigned int offset; 177 178 port = tegra186_gpio_get_port(gpio, &pin); 179 if (!port) 180 return NULL; 181 182 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; 183 184 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; 185 } 186 187 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin) 188 { 189 void __iomem *secure; 190 u32 value; 191 192 secure = tegra186_gpio_get_secure_base(gpio, pin); 193 194 if (gpio->soc->has_vm_support) { 195 value = readl(secure + TEGRA186_GPIO_VM); 196 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) 197 return false; 198 } 199 200 value = __raw_readl(secure + TEGRA186_GPIO_SCR); 201 202 /* 203 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the 204 * registers for given GPIO pin. 205 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying 206 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given 207 * GPIO pin. 208 */ 209 210 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || 211 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) && 212 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || 213 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W)))) 214 return true; 215 216 return false; 217 } 218 219 static int tegra186_init_valid_mask(struct gpio_chip *chip, 220 unsigned long *valid_mask, unsigned int ngpios) 221 { 222 struct tegra_gpio *gpio = gpiochip_get_data(chip); 223 unsigned int j; 224 225 for (j = 0; j < ngpios; j++) { 226 if (!tegra186_gpio_is_accessible(gpio, j)) 227 clear_bit(j, valid_mask); 228 } 229 return 0; 230 } 231 232 static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 233 int level) 234 { 235 struct tegra_gpio *gpio = gpiochip_get_data(chip); 236 void __iomem *base; 237 u32 value; 238 239 base = tegra186_gpio_get_base(gpio, offset); 240 if (WARN_ON(base == NULL)) 241 return -ENODEV; 242 243 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 244 if (level == 0) 245 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 246 else 247 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 248 249 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 250 251 return 0; 252 } 253 254 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 255 unsigned int offset) 256 { 257 struct tegra_gpio *gpio = gpiochip_get_data(chip); 258 void __iomem *base; 259 u32 value; 260 261 base = tegra186_gpio_get_base(gpio, offset); 262 if (WARN_ON(base == NULL)) 263 return -ENODEV; 264 265 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 266 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 267 return GPIO_LINE_DIRECTION_OUT; 268 269 return GPIO_LINE_DIRECTION_IN; 270 } 271 272 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 273 unsigned int offset) 274 { 275 struct tegra_gpio *gpio = gpiochip_get_data(chip); 276 void __iomem *base; 277 u32 value; 278 279 base = tegra186_gpio_get_base(gpio, offset); 280 if (WARN_ON(base == NULL)) 281 return -ENODEV; 282 283 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 284 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 285 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 286 287 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 288 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 289 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 290 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 291 292 return 0; 293 } 294 295 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 296 unsigned int offset, int level) 297 { 298 struct tegra_gpio *gpio = gpiochip_get_data(chip); 299 void __iomem *base; 300 u32 value; 301 int ret; 302 303 /* configure output level first */ 304 ret = tegra186_gpio_set(chip, offset, level); 305 if (ret) 306 return ret; 307 308 base = tegra186_gpio_get_base(gpio, offset); 309 if (WARN_ON(base == NULL)) 310 return -EINVAL; 311 312 /* set the direction */ 313 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 314 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 315 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 316 317 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 318 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 319 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 320 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 321 322 return 0; 323 } 324 325 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 326 327 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 328 unsigned long flags) 329 { 330 struct tegra_gpio *gpio; 331 void __iomem *base; 332 int value; 333 334 if (!gc) 335 return -EINVAL; 336 337 gpio = gpiochip_get_data(gc); 338 if (!gpio) 339 return -ENODEV; 340 341 base = tegra186_gpio_get_base(gpio, offset); 342 if (WARN_ON(base == NULL)) 343 return -EINVAL; 344 345 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 346 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 347 348 if (flags == HTE_BOTH_EDGES) { 349 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 350 } else if (flags == HTE_RISING_EDGE_TS) { 351 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 352 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 353 } else if (flags == HTE_FALLING_EDGE_TS) { 354 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 355 } 356 357 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 358 359 return 0; 360 } 361 362 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 363 unsigned long flags) 364 { 365 struct tegra_gpio *gpio; 366 void __iomem *base; 367 int value; 368 369 if (!gc) 370 return -EINVAL; 371 372 gpio = gpiochip_get_data(gc); 373 if (!gpio) 374 return -ENODEV; 375 376 base = tegra186_gpio_get_base(gpio, offset); 377 if (WARN_ON(base == NULL)) 378 return -EINVAL; 379 380 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 381 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 382 if (flags == HTE_BOTH_EDGES) { 383 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 384 } else if (flags == HTE_RISING_EDGE_TS) { 385 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 386 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 387 } else if (flags == HTE_FALLING_EDGE_TS) { 388 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 389 } 390 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 391 392 return 0; 393 } 394 395 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 396 { 397 struct tegra_gpio *gpio = gpiochip_get_data(chip); 398 void __iomem *base; 399 u32 value; 400 401 base = tegra186_gpio_get_base(gpio, offset); 402 if (WARN_ON(base == NULL)) 403 return -ENODEV; 404 405 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 406 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 407 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 408 else 409 value = readl(base + TEGRA186_GPIO_INPUT); 410 411 return value & BIT(0); 412 } 413 414 static int tegra186_gpio_set_config(struct gpio_chip *chip, 415 unsigned int offset, 416 unsigned long config) 417 { 418 struct tegra_gpio *gpio = gpiochip_get_data(chip); 419 u32 debounce, value; 420 void __iomem *base; 421 422 base = tegra186_gpio_get_base(gpio, offset); 423 if (base == NULL) 424 return -ENXIO; 425 426 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 427 return -ENOTSUPP; 428 429 debounce = pinconf_to_config_argument(config); 430 431 /* 432 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 433 * time. 434 */ 435 if (debounce > 255000) 436 return -EINVAL; 437 438 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 439 440 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 441 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 442 443 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 444 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 445 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 446 447 return 0; 448 } 449 450 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 451 { 452 struct tegra_gpio *gpio = gpiochip_get_data(chip); 453 struct pinctrl_dev *pctldev; 454 struct device_node *np; 455 unsigned int i, j; 456 int err; 457 458 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 459 return 0; 460 461 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 462 if (!np) 463 return -ENODEV; 464 465 pctldev = of_pinctrl_get(np); 466 of_node_put(np); 467 if (!pctldev) 468 return -EPROBE_DEFER; 469 470 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 471 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 472 const char *group = gpio->soc->pin_ranges[i].group; 473 474 port = pin / 8; 475 pin = pin % 8; 476 477 if (port >= gpio->soc->num_ports) { 478 dev_warn(chip->parent, "invalid port %u for %s\n", 479 port, group); 480 continue; 481 } 482 483 for (j = 0; j < port; j++) 484 pin += gpio->soc->ports[j].pins; 485 486 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 487 if (err < 0) 488 return err; 489 } 490 491 return 0; 492 } 493 494 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 495 const struct of_phandle_args *spec, 496 u32 *flags) 497 { 498 struct tegra_gpio *gpio = gpiochip_get_data(chip); 499 unsigned int port, pin, i, offset = 0; 500 501 if (WARN_ON(chip->of_gpio_n_cells < 2)) 502 return -EINVAL; 503 504 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 505 return -EINVAL; 506 507 port = spec->args[0] / 8; 508 pin = spec->args[0] % 8; 509 510 if (port >= gpio->soc->num_ports) { 511 dev_err(chip->parent, "invalid port number: %u\n", port); 512 return -EINVAL; 513 } 514 515 for (i = 0; i < port; i++) 516 offset += gpio->soc->ports[i].pins; 517 518 if (flags) 519 *flags = spec->args[1]; 520 521 return offset + pin; 522 } 523 524 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 525 526 static void tegra186_irq_ack(struct irq_data *data) 527 { 528 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 529 struct tegra_gpio *gpio = to_tegra_gpio(gc); 530 void __iomem *base; 531 532 base = tegra186_gpio_get_base(gpio, data->hwirq); 533 if (WARN_ON(base == NULL)) 534 return; 535 536 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 537 } 538 539 static void tegra186_irq_mask(struct irq_data *data) 540 { 541 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 542 struct tegra_gpio *gpio = to_tegra_gpio(gc); 543 void __iomem *base; 544 u32 value; 545 546 base = tegra186_gpio_get_base(gpio, data->hwirq); 547 if (WARN_ON(base == NULL)) 548 return; 549 550 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 551 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 552 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 553 554 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 555 } 556 557 static void tegra186_irq_unmask(struct irq_data *data) 558 { 559 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 560 struct tegra_gpio *gpio = to_tegra_gpio(gc); 561 void __iomem *base; 562 u32 value; 563 564 base = tegra186_gpio_get_base(gpio, data->hwirq); 565 if (WARN_ON(base == NULL)) 566 return; 567 568 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 569 570 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 571 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 572 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 573 } 574 575 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 576 { 577 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 578 struct tegra_gpio *gpio = to_tegra_gpio(gc); 579 void __iomem *base; 580 u32 value; 581 582 base = tegra186_gpio_get_base(gpio, data->hwirq); 583 if (WARN_ON(base == NULL)) 584 return -ENODEV; 585 586 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 587 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 588 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 589 590 switch (type & IRQ_TYPE_SENSE_MASK) { 591 case IRQ_TYPE_NONE: 592 break; 593 594 case IRQ_TYPE_EDGE_RISING: 595 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 596 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 597 break; 598 599 case IRQ_TYPE_EDGE_FALLING: 600 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 601 break; 602 603 case IRQ_TYPE_EDGE_BOTH: 604 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 605 break; 606 607 case IRQ_TYPE_LEVEL_HIGH: 608 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 609 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 610 break; 611 612 case IRQ_TYPE_LEVEL_LOW: 613 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 614 break; 615 616 default: 617 return -EINVAL; 618 } 619 620 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 621 622 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 623 irq_set_handler_locked(data, handle_level_irq); 624 else 625 irq_set_handler_locked(data, handle_edge_irq); 626 627 if (data->parent_data) 628 return irq_chip_set_type_parent(data, type); 629 630 return 0; 631 } 632 633 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 634 { 635 if (data->parent_data) 636 return irq_chip_set_wake_parent(data, on); 637 638 return 0; 639 } 640 641 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 642 { 643 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 644 645 seq_puts(p, dev_name(gc->parent)); 646 } 647 648 static const struct irq_chip tegra186_gpio_irq_chip = { 649 .irq_ack = tegra186_irq_ack, 650 .irq_mask = tegra186_irq_mask, 651 .irq_unmask = tegra186_irq_unmask, 652 .irq_set_type = tegra186_irq_set_type, 653 .irq_set_wake = tegra186_irq_set_wake, 654 .irq_print_chip = tegra186_irq_print_chip, 655 .flags = IRQCHIP_IMMUTABLE, 656 GPIOCHIP_IRQ_RESOURCE_HELPERS, 657 }; 658 659 static void tegra186_gpio_irq(struct irq_desc *desc) 660 { 661 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 662 struct irq_domain *domain = gpio->gpio.irq.domain; 663 struct irq_chip *chip = irq_desc_get_chip(desc); 664 unsigned int parent = irq_desc_get_irq(desc); 665 unsigned int i, j, offset = 0; 666 667 chained_irq_enter(chip, desc); 668 669 for (i = 0; i < gpio->soc->num_ports; i++) { 670 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 671 unsigned int pin; 672 unsigned long value; 673 void __iomem *base; 674 675 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 676 677 /* skip ports that are not associated with this bank */ 678 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 679 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 680 break; 681 } 682 683 if (j == gpio->num_irqs_per_bank) 684 goto skip; 685 686 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 687 688 for_each_set_bit(pin, &value, port->pins) { 689 int ret = generic_handle_domain_irq(domain, offset + pin); 690 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 691 } 692 693 skip: 694 offset += port->pins; 695 } 696 697 chained_irq_exit(chip, desc); 698 } 699 700 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 701 struct irq_fwspec *fwspec, 702 unsigned long *hwirq, 703 unsigned int *type) 704 { 705 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 706 unsigned int port, pin, i, offset = 0; 707 708 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 709 return -EINVAL; 710 711 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 712 return -EINVAL; 713 714 port = fwspec->param[0] / 8; 715 pin = fwspec->param[0] % 8; 716 717 if (port >= gpio->soc->num_ports) 718 return -EINVAL; 719 720 for (i = 0; i < port; i++) 721 offset += gpio->soc->ports[i].pins; 722 723 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 724 *hwirq = offset + pin; 725 726 return 0; 727 } 728 729 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 730 union gpio_irq_fwspec *gfwspec, 731 unsigned int parent_hwirq, 732 unsigned int parent_type) 733 { 734 struct tegra_gpio *gpio = gpiochip_get_data(chip); 735 struct irq_fwspec *fwspec = &gfwspec->fwspec; 736 737 fwspec->fwnode = chip->irq.parent_domain->fwnode; 738 fwspec->param_count = 3; 739 fwspec->param[0] = gpio->soc->instance; 740 fwspec->param[1] = parent_hwirq; 741 fwspec->param[2] = parent_type; 742 743 return 0; 744 } 745 746 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 747 unsigned int hwirq, 748 unsigned int type, 749 unsigned int *parent_hwirq, 750 unsigned int *parent_type) 751 { 752 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 753 *parent_type = type; 754 755 return 0; 756 } 757 758 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 759 unsigned int offset) 760 { 761 struct tegra_gpio *gpio = gpiochip_get_data(chip); 762 unsigned int i; 763 764 for (i = 0; i < gpio->soc->num_ports; i++) { 765 if (offset < gpio->soc->ports[i].pins) 766 break; 767 768 offset -= gpio->soc->ports[i].pins; 769 } 770 771 return offset + i * 8; 772 } 773 774 static const struct of_device_id tegra186_pmc_of_match[] = { 775 { .compatible = "nvidia,tegra186-pmc" }, 776 { .compatible = "nvidia,tegra194-pmc" }, 777 { .compatible = "nvidia,tegra234-pmc" }, 778 { /* sentinel */ } 779 }; 780 781 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 782 { 783 struct device *dev = gpio->gpio.parent; 784 unsigned int i; 785 u32 value; 786 787 for (i = 0; i < gpio->soc->num_ports; i++) { 788 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 789 unsigned int offset, p = port->port; 790 void __iomem *base; 791 792 base = gpio->secure + port->bank * 0x1000 + 0x800; 793 794 value = readl(base + TEGRA186_GPIO_CTL_SCR); 795 796 /* 797 * For controllers that haven't been locked down yet, make 798 * sure to program the default interrupt route mapping. 799 */ 800 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 801 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 802 /* 803 * On Tegra194 and later, each pin can be routed to one or more 804 * interrupts. 805 */ 806 dev_dbg(dev, "programming default interrupt routing for port %s\n", 807 port->name); 808 809 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0); 810 811 /* 812 * By default we only want to route GPIO pins to IRQ 0. This works 813 * only under the assumption that we're running as the host kernel 814 * and hence all GPIO pins are owned by Linux. 815 * 816 * For cases where Linux is the guest OS, the hypervisor will have 817 * to configure the interrupt routing and pass only the valid 818 * interrupts via device tree. 819 */ 820 value = readl(base + offset); 821 value = BIT(port->pins) - 1; 822 writel(value, base + offset); 823 } 824 } 825 } 826 827 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 828 { 829 struct device *dev = gpio->gpio.parent; 830 831 if (gpio->num_irq > gpio->num_banks) { 832 if (gpio->num_irq % gpio->num_banks != 0) 833 goto error; 834 } 835 836 if (gpio->num_irq < gpio->num_banks) 837 goto error; 838 839 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 840 841 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 842 goto error; 843 844 return 0; 845 846 error: 847 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 848 gpio->num_irq, gpio->num_banks); 849 return -EINVAL; 850 } 851 852 static int tegra186_gpio_probe(struct platform_device *pdev) 853 { 854 unsigned int i, j, offset; 855 struct gpio_irq_chip *irq; 856 struct tegra_gpio *gpio; 857 struct device_node *np; 858 struct resource *res; 859 char **names; 860 int err; 861 862 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 863 if (!gpio) 864 return -ENOMEM; 865 866 gpio->soc = device_get_match_data(&pdev->dev); 867 gpio->gpio.label = gpio->soc->name; 868 gpio->gpio.parent = &pdev->dev; 869 870 /* count the number of banks in the controller */ 871 for (i = 0; i < gpio->soc->num_ports; i++) 872 if (gpio->soc->ports[i].bank > gpio->num_banks) 873 gpio->num_banks = gpio->soc->ports[i].bank; 874 875 gpio->num_banks++; 876 877 /* get register apertures */ 878 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security"); 879 if (!res) 880 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 881 gpio->secure = devm_ioremap_resource(&pdev->dev, res); 882 if (IS_ERR(gpio->secure)) 883 return PTR_ERR(gpio->secure); 884 885 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); 886 if (!res) 887 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 888 gpio->base = devm_ioremap_resource(&pdev->dev, res); 889 if (IS_ERR(gpio->base)) 890 return PTR_ERR(gpio->base); 891 892 err = platform_irq_count(pdev); 893 if (err < 0) 894 return err; 895 896 gpio->num_irq = err; 897 898 err = tegra186_gpio_irqs_per_bank(gpio); 899 if (err < 0) 900 return err; 901 902 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 903 GFP_KERNEL); 904 if (!gpio->irq) 905 return -ENOMEM; 906 907 for (i = 0; i < gpio->num_irq; i++) { 908 err = platform_get_irq(pdev, i); 909 if (err < 0) 910 return err; 911 912 gpio->irq[i] = err; 913 } 914 915 gpio->gpio.request = gpiochip_generic_request; 916 gpio->gpio.free = gpiochip_generic_free; 917 gpio->gpio.get_direction = tegra186_gpio_get_direction; 918 gpio->gpio.direction_input = tegra186_gpio_direction_input; 919 gpio->gpio.direction_output = tegra186_gpio_direction_output; 920 gpio->gpio.get = tegra186_gpio_get; 921 gpio->gpio.set = tegra186_gpio_set; 922 gpio->gpio.set_config = tegra186_gpio_set_config; 923 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 924 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; 925 if (gpio->soc->has_gte) { 926 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 927 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 928 } 929 930 gpio->gpio.base = -1; 931 932 for (i = 0; i < gpio->soc->num_ports; i++) 933 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 934 935 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 936 sizeof(*names), GFP_KERNEL); 937 if (!names) 938 return -ENOMEM; 939 940 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 941 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 942 char *name; 943 944 for (j = 0; j < port->pins; j++) { 945 if (gpio->soc->prefix) 946 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, "%s-P%s.%02x", 947 gpio->soc->prefix, port->name, j); 948 else 949 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, "P%s.%02x", 950 port->name, j); 951 if (!name) 952 return -ENOMEM; 953 954 names[offset + j] = name; 955 } 956 957 offset += port->pins; 958 } 959 960 gpio->gpio.names = (const char * const *)names; 961 962 #if defined(CONFIG_OF_GPIO) 963 gpio->gpio.of_gpio_n_cells = 2; 964 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 965 #endif /* CONFIG_OF_GPIO */ 966 967 irq = &gpio->gpio.irq; 968 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 969 irq->fwnode = dev_fwnode(&pdev->dev); 970 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 971 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 972 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 973 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 974 irq->handler = handle_simple_irq; 975 irq->default_type = IRQ_TYPE_NONE; 976 irq->parent_handler = tegra186_gpio_irq; 977 irq->parent_handler_data = gpio; 978 irq->num_parents = gpio->num_irq; 979 980 /* 981 * To simplify things, use a single interrupt per bank for now. Some 982 * chips support up to 8 interrupts per bank, which can be useful to 983 * distribute the load and decrease the processing latency for GPIOs 984 * but it also requires a more complicated interrupt routing than we 985 * currently program. 986 */ 987 if (gpio->num_irqs_per_bank > 1) { 988 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 989 sizeof(*irq->parents), GFP_KERNEL); 990 if (!irq->parents) 991 return -ENOMEM; 992 993 for (i = 0; i < gpio->num_banks; i++) 994 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 995 996 irq->num_parents = gpio->num_banks; 997 } else { 998 irq->num_parents = gpio->num_irq; 999 irq->parents = gpio->irq; 1000 } 1001 1002 if (gpio->soc->num_irqs_per_bank > 1) 1003 tegra186_gpio_init_route_mapping(gpio); 1004 1005 np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0); 1006 if (!np) 1007 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 1008 if (np) { 1009 if (of_device_is_available(np)) { 1010 irq->parent_domain = irq_find_host(np); 1011 of_node_put(np); 1012 1013 if (!irq->parent_domain) 1014 return -EPROBE_DEFER; 1015 } else { 1016 of_node_put(np); 1017 } 1018 } 1019 1020 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 1021 sizeof(*irq->map), GFP_KERNEL); 1022 if (!irq->map) 1023 return -ENOMEM; 1024 1025 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 1026 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 1027 1028 for (j = 0; j < port->pins; j++) 1029 irq->map[offset + j] = irq->parents[port->bank]; 1030 1031 offset += port->pins; 1032 } 1033 1034 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 1035 } 1036 1037 #define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \ 1038 [_prefix##_GPIO_PORT_##_name] = { \ 1039 .name = #_name, \ 1040 .bank = _bank, \ 1041 .port = _port, \ 1042 .pins = _pins, \ 1043 } 1044 1045 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1046 TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins) 1047 1048 static const struct tegra_gpio_port tegra186_main_ports[] = { 1049 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 1050 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 1051 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 1052 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 1053 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 1054 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 1055 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 1056 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 1057 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 1058 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 1059 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 1060 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 1061 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 1062 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 1063 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 1064 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 1065 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 1066 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 1067 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 1068 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 1069 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 1070 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 1071 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 1072 }; 1073 1074 static const struct tegra_gpio_soc tegra186_main_soc = { 1075 .num_ports = ARRAY_SIZE(tegra186_main_ports), 1076 .ports = tegra186_main_ports, 1077 .name = "tegra186-gpio", 1078 .instance = 0, 1079 .num_irqs_per_bank = 1, 1080 .has_vm_support = false, 1081 }; 1082 1083 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1084 TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins) 1085 1086 static const struct tegra_gpio_port tegra186_aon_ports[] = { 1087 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 1088 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 1089 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 1090 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 1091 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 1092 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 1093 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 1094 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 1095 }; 1096 1097 static const struct tegra_gpio_soc tegra186_aon_soc = { 1098 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 1099 .ports = tegra186_aon_ports, 1100 .name = "tegra186-gpio-aon", 1101 .instance = 1, 1102 .num_irqs_per_bank = 1, 1103 .has_vm_support = false, 1104 }; 1105 1106 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1107 TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins) 1108 1109 static const struct tegra_gpio_port tegra194_main_ports[] = { 1110 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1111 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1112 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1113 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1114 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1115 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1116 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1117 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1118 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1119 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1120 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1121 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1122 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1123 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1124 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1125 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1126 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1127 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1128 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1129 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1130 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1131 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1132 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1133 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1134 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1135 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1136 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1137 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1138 }; 1139 1140 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1141 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1142 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1143 }; 1144 1145 static const struct tegra_gpio_soc tegra194_main_soc = { 1146 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1147 .ports = tegra194_main_ports, 1148 .name = "tegra194-gpio", 1149 .instance = 0, 1150 .num_irqs_per_bank = 8, 1151 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1152 .pin_ranges = tegra194_main_pin_ranges, 1153 .pinmux = "nvidia,tegra194-pinmux", 1154 .has_vm_support = true, 1155 }; 1156 1157 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1158 TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins) 1159 1160 static const struct tegra_gpio_port tegra194_aon_ports[] = { 1161 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1162 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1163 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1164 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1165 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1166 }; 1167 1168 static const struct tegra_gpio_soc tegra194_aon_soc = { 1169 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1170 .ports = tegra194_aon_ports, 1171 .name = "tegra194-gpio-aon", 1172 .instance = 1, 1173 .num_irqs_per_bank = 8, 1174 .has_gte = true, 1175 .has_vm_support = false, 1176 }; 1177 1178 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1179 TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins) 1180 1181 static const struct tegra_gpio_port tegra234_main_ports[] = { 1182 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1183 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1184 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1185 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1186 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1187 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1188 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1189 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1190 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1191 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1192 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1193 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1194 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1195 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1196 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1197 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1198 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1199 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1200 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1201 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1202 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1203 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1204 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1205 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1206 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1207 }; 1208 1209 static const struct tegra_gpio_soc tegra234_main_soc = { 1210 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1211 .ports = tegra234_main_ports, 1212 .name = "tegra234-gpio", 1213 .instance = 0, 1214 .num_irqs_per_bank = 8, 1215 .has_vm_support = true, 1216 }; 1217 1218 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1219 TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins) 1220 1221 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1222 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1223 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1224 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1225 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1226 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1227 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1228 }; 1229 1230 static const struct tegra_gpio_soc tegra234_aon_soc = { 1231 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1232 .ports = tegra234_aon_ports, 1233 .name = "tegra234-gpio-aon", 1234 .instance = 1, 1235 .num_irqs_per_bank = 8, 1236 .has_gte = true, 1237 .has_vm_support = false, 1238 }; 1239 1240 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1241 TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins) 1242 1243 static const struct tegra_gpio_port tegra241_main_ports[] = { 1244 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1245 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1246 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1247 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1248 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1249 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1250 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1251 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1252 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1253 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1254 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1255 }; 1256 1257 static const struct tegra_gpio_soc tegra241_main_soc = { 1258 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1259 .ports = tegra241_main_ports, 1260 .name = "tegra241-gpio", 1261 .instance = 0, 1262 .num_irqs_per_bank = 8, 1263 .has_vm_support = false, 1264 }; 1265 1266 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1267 TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins) 1268 1269 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1270 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1271 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1272 }; 1273 1274 static const struct tegra_gpio_soc tegra241_aon_soc = { 1275 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1276 .ports = tegra241_aon_ports, 1277 .name = "tegra241-gpio-aon", 1278 .instance = 1, 1279 .num_irqs_per_bank = 8, 1280 .has_vm_support = false, 1281 }; 1282 1283 #define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1284 TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins) 1285 1286 static const struct tegra_gpio_port tegra264_main_ports[] = { 1287 TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8), 1288 TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5), 1289 TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8), 1290 TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8), 1291 TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8), 1292 TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8), 1293 TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6), 1294 TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8), 1295 TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8), 1296 TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8), 1297 TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2), 1298 TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7), 1299 TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8), 1300 TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8), 1301 TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8), 1302 TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6), 1303 TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8), 1304 TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8), 1305 TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3), 1306 }; 1307 1308 static const struct tegra_gpio_soc tegra264_main_soc = { 1309 .num_ports = ARRAY_SIZE(tegra264_main_ports), 1310 .ports = tegra264_main_ports, 1311 .name = "tegra264-gpio", 1312 .instance = 0, 1313 .num_irqs_per_bank = 8, 1314 .has_vm_support = true, 1315 }; 1316 1317 #define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1318 TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins) 1319 1320 static const struct tegra_gpio_port tegra264_aon_ports[] = { 1321 TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8), 1322 TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2), 1323 TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8), 1324 TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8), 1325 TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4) 1326 }; 1327 1328 static const struct tegra_gpio_soc tegra264_aon_soc = { 1329 .num_ports = ARRAY_SIZE(tegra264_aon_ports), 1330 .ports = tegra264_aon_ports, 1331 .name = "tegra264-gpio-aon", 1332 .instance = 1, 1333 .num_irqs_per_bank = 8, 1334 .has_vm_support = true, 1335 }; 1336 1337 #define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \ 1338 TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins) 1339 1340 static const struct tegra_gpio_port tegra264_uphy_ports[] = { 1341 TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6), 1342 TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8), 1343 TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3), 1344 TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8), 1345 TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4), 1346 }; 1347 1348 static const struct tegra_gpio_soc tegra264_uphy_soc = { 1349 .num_ports = ARRAY_SIZE(tegra264_uphy_ports), 1350 .ports = tegra264_uphy_ports, 1351 .name = "tegra264-gpio-uphy", 1352 .instance = 2, 1353 .num_irqs_per_bank = 8, 1354 .has_vm_support = true, 1355 }; 1356 1357 #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1358 TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins) 1359 1360 static const struct tegra_gpio_port tegra256_main_ports[] = { 1361 TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), 1362 TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), 1363 TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), 1364 TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), 1365 }; 1366 1367 static const struct tegra_gpio_soc tegra256_main_soc = { 1368 .num_ports = ARRAY_SIZE(tegra256_main_ports), 1369 .ports = tegra256_main_ports, 1370 .name = "tegra256-gpio-main", 1371 .instance = 1, 1372 .num_irqs_per_bank = 8, 1373 .has_vm_support = true, 1374 }; 1375 1376 #define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \ 1377 TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins) 1378 1379 static const struct tegra_gpio_port tegra410_compute_ports[] = { 1380 TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3), 1381 TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8), 1382 TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3), 1383 TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8), 1384 TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8), 1385 }; 1386 1387 static const struct tegra_gpio_soc tegra410_compute_soc = { 1388 .num_ports = ARRAY_SIZE(tegra410_compute_ports), 1389 .ports = tegra410_compute_ports, 1390 .name = "tegra410-gpio-compute", 1391 .prefix = "COMPUTE", 1392 .num_irqs_per_bank = 8, 1393 .instance = 0, 1394 }; 1395 1396 #define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \ 1397 TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins) 1398 1399 static const struct tegra_gpio_port tegra410_system_ports[] = { 1400 TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7), 1401 TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8), 1402 TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8), 1403 TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8), 1404 TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6), 1405 TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8), 1406 TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7), 1407 TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7), 1408 TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7), 1409 TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7), 1410 TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6), 1411 TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8), 1412 TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3), 1413 TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2), 1414 TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2), 1415 }; 1416 1417 static const struct tegra_gpio_soc tegra410_system_soc = { 1418 .num_ports = ARRAY_SIZE(tegra410_system_ports), 1419 .ports = tegra410_system_ports, 1420 .name = "tegra410-gpio-system", 1421 .prefix = "SYSTEM", 1422 .num_irqs_per_bank = 8, 1423 .instance = 0, 1424 }; 1425 1426 static const struct of_device_id tegra186_gpio_of_match[] = { 1427 { 1428 .compatible = "nvidia,tegra186-gpio", 1429 .data = &tegra186_main_soc 1430 }, { 1431 .compatible = "nvidia,tegra186-gpio-aon", 1432 .data = &tegra186_aon_soc 1433 }, { 1434 .compatible = "nvidia,tegra194-gpio", 1435 .data = &tegra194_main_soc 1436 }, { 1437 .compatible = "nvidia,tegra194-gpio-aon", 1438 .data = &tegra194_aon_soc 1439 }, { 1440 .compatible = "nvidia,tegra234-gpio", 1441 .data = &tegra234_main_soc 1442 }, { 1443 .compatible = "nvidia,tegra234-gpio-aon", 1444 .data = &tegra234_aon_soc 1445 }, { 1446 .compatible = "nvidia,tegra256-gpio", 1447 .data = &tegra256_main_soc 1448 }, { 1449 .compatible = "nvidia,tegra264-gpio", 1450 .data = &tegra264_main_soc 1451 }, { 1452 .compatible = "nvidia,tegra264-gpio-aon", 1453 .data = &tegra264_aon_soc 1454 }, { 1455 .compatible = "nvidia,tegra264-gpio-uphy", 1456 .data = &tegra264_uphy_soc 1457 }, { 1458 /* sentinel */ 1459 } 1460 }; 1461 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1462 1463 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1464 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1465 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1466 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1467 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1468 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1469 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1470 { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc }, 1471 { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc }, 1472 {} 1473 }; 1474 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1475 1476 static struct platform_driver tegra186_gpio_driver = { 1477 .driver = { 1478 .name = "tegra186-gpio", 1479 .of_match_table = tegra186_gpio_of_match, 1480 .acpi_match_table = tegra186_gpio_acpi_match, 1481 }, 1482 .probe = tegra186_gpio_probe, 1483 }; 1484 module_platform_driver(tegra186_gpio_driver); 1485 1486 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1487 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1488 MODULE_LICENSE("GPL v2"); 1489