1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2026 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/hte.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 19 #include <dt-bindings/gpio/tegra186-gpio.h> 20 #include <dt-bindings/gpio/tegra194-gpio.h> 21 #include <dt-bindings/gpio/tegra234-gpio.h> 22 #include <dt-bindings/gpio/nvidia,tegra238-gpio.h> 23 #include <dt-bindings/gpio/tegra241-gpio.h> 24 #include <dt-bindings/gpio/tegra256-gpio.h> 25 #include <dt-bindings/gpio/nvidia,tegra264-gpio.h> 26 27 /* security registers */ 28 #define TEGRA186_GPIO_CTL_SCR 0x0c 29 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 30 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 31 32 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 33 34 #define TEGRA186_GPIO_VM 0x00 35 #define TEGRA186_GPIO_VM_RW_MASK 0x03 36 #define TEGRA186_GPIO_SCR 0x04 37 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 38 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 39 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) 40 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) 41 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) 42 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) 43 44 /* control registers */ 45 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 46 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 47 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 48 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 49 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 50 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 51 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 52 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 53 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 54 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 55 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 56 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 57 58 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 59 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 60 61 #define TEGRA186_GPIO_INPUT 0x08 62 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 63 64 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 65 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 66 67 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 68 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 69 70 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 71 72 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 73 74 /* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */ 75 #define TEGRA410_COMPUTE_GPIO_PORT_A 0 76 #define TEGRA410_COMPUTE_GPIO_PORT_B 1 77 #define TEGRA410_COMPUTE_GPIO_PORT_C 2 78 #define TEGRA410_COMPUTE_GPIO_PORT_D 3 79 #define TEGRA410_COMPUTE_GPIO_PORT_E 4 80 81 /* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */ 82 #define TEGRA410_SYSTEM_GPIO_PORT_A 0 83 #define TEGRA410_SYSTEM_GPIO_PORT_B 1 84 #define TEGRA410_SYSTEM_GPIO_PORT_C 2 85 #define TEGRA410_SYSTEM_GPIO_PORT_D 3 86 #define TEGRA410_SYSTEM_GPIO_PORT_E 4 87 #define TEGRA410_SYSTEM_GPIO_PORT_I 5 88 #define TEGRA410_SYSTEM_GPIO_PORT_J 6 89 #define TEGRA410_SYSTEM_GPIO_PORT_K 7 90 #define TEGRA410_SYSTEM_GPIO_PORT_L 8 91 #define TEGRA410_SYSTEM_GPIO_PORT_M 9 92 #define TEGRA410_SYSTEM_GPIO_PORT_N 10 93 #define TEGRA410_SYSTEM_GPIO_PORT_P 11 94 #define TEGRA410_SYSTEM_GPIO_PORT_Q 12 95 #define TEGRA410_SYSTEM_GPIO_PORT_R 13 96 #define TEGRA410_SYSTEM_GPIO_PORT_V 14 97 98 struct tegra_gpio_port { 99 const char *name; 100 unsigned int bank; 101 unsigned int port; 102 unsigned int pins; 103 }; 104 105 struct tegra186_pin_range { 106 unsigned int offset; 107 const char *group; 108 }; 109 110 struct tegra_gpio_soc { 111 const struct tegra_gpio_port *ports; 112 unsigned int num_ports; 113 const char *name; 114 const char *prefix; 115 unsigned int instance; 116 117 unsigned int num_irqs_per_bank; 118 119 const struct tegra186_pin_range *pin_ranges; 120 unsigned int num_pin_ranges; 121 const char *pinmux; 122 bool has_gte; 123 bool has_vm_support; 124 }; 125 126 struct tegra_gpio { 127 struct gpio_chip gpio; 128 unsigned int num_irq; 129 130 const struct tegra_gpio_soc *soc; 131 unsigned int num_irqs_per_bank; 132 unsigned int num_banks; 133 134 void __iomem *secure; 135 void __iomem *base; 136 137 unsigned int irq[] __counted_by(num_irq); 138 }; 139 140 static const struct tegra_gpio_port * 141 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 142 { 143 unsigned int start = 0, i; 144 145 for (i = 0; i < gpio->soc->num_ports; i++) { 146 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 147 148 if (*pin >= start && *pin < start + port->pins) { 149 *pin -= start; 150 return port; 151 } 152 153 start += port->pins; 154 } 155 156 return NULL; 157 } 158 159 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 160 unsigned int pin) 161 { 162 const struct tegra_gpio_port *port; 163 unsigned int offset; 164 165 port = tegra186_gpio_get_port(gpio, &pin); 166 if (!port) 167 return NULL; 168 169 offset = port->bank * 0x1000 + port->port * 0x200; 170 171 return gpio->base + offset + pin * 0x20; 172 } 173 174 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, 175 unsigned int pin) 176 { 177 const struct tegra_gpio_port *port; 178 unsigned int offset; 179 180 port = tegra186_gpio_get_port(gpio, &pin); 181 if (!port) 182 return NULL; 183 184 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; 185 186 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; 187 } 188 189 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin) 190 { 191 void __iomem *secure; 192 u32 value; 193 194 secure = tegra186_gpio_get_secure_base(gpio, pin); 195 196 if (gpio->soc->has_vm_support) { 197 value = readl(secure + TEGRA186_GPIO_VM); 198 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) 199 return false; 200 } 201 202 value = __raw_readl(secure + TEGRA186_GPIO_SCR); 203 204 /* 205 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the 206 * registers for given GPIO pin. 207 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying 208 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given 209 * GPIO pin. 210 */ 211 212 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || 213 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) && 214 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || 215 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W)))) 216 return true; 217 218 return false; 219 } 220 221 static int tegra186_init_valid_mask(struct gpio_chip *chip, 222 unsigned long *valid_mask, unsigned int ngpios) 223 { 224 struct tegra_gpio *gpio = gpiochip_get_data(chip); 225 unsigned int j; 226 227 for (j = 0; j < ngpios; j++) { 228 if (!tegra186_gpio_is_accessible(gpio, j)) 229 clear_bit(j, valid_mask); 230 } 231 return 0; 232 } 233 234 static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 235 int level) 236 { 237 struct tegra_gpio *gpio = gpiochip_get_data(chip); 238 void __iomem *base; 239 u32 value; 240 241 base = tegra186_gpio_get_base(gpio, offset); 242 if (WARN_ON(base == NULL)) 243 return -ENODEV; 244 245 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 246 if (level == 0) 247 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 248 else 249 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 250 251 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 252 253 return 0; 254 } 255 256 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 257 unsigned int offset) 258 { 259 struct tegra_gpio *gpio = gpiochip_get_data(chip); 260 void __iomem *base; 261 u32 value; 262 263 base = tegra186_gpio_get_base(gpio, offset); 264 if (WARN_ON(base == NULL)) 265 return -ENODEV; 266 267 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 268 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 269 return GPIO_LINE_DIRECTION_OUT; 270 271 return GPIO_LINE_DIRECTION_IN; 272 } 273 274 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 275 unsigned int offset) 276 { 277 struct tegra_gpio *gpio = gpiochip_get_data(chip); 278 void __iomem *base; 279 u32 value; 280 281 base = tegra186_gpio_get_base(gpio, offset); 282 if (WARN_ON(base == NULL)) 283 return -ENODEV; 284 285 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 286 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 287 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 288 289 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 290 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 291 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 292 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 293 294 return 0; 295 } 296 297 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 298 unsigned int offset, int level) 299 { 300 struct tegra_gpio *gpio = gpiochip_get_data(chip); 301 void __iomem *base; 302 u32 value; 303 int ret; 304 305 /* configure output level first */ 306 ret = tegra186_gpio_set(chip, offset, level); 307 if (ret) 308 return ret; 309 310 base = tegra186_gpio_get_base(gpio, offset); 311 if (WARN_ON(base == NULL)) 312 return -EINVAL; 313 314 /* set the direction */ 315 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 316 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 317 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 318 319 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 320 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 321 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 322 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 323 324 return 0; 325 } 326 327 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 328 329 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 330 unsigned long flags) 331 { 332 struct tegra_gpio *gpio; 333 void __iomem *base; 334 int value; 335 336 if (!gc) 337 return -EINVAL; 338 339 gpio = gpiochip_get_data(gc); 340 if (!gpio) 341 return -ENODEV; 342 343 base = tegra186_gpio_get_base(gpio, offset); 344 if (WARN_ON(base == NULL)) 345 return -EINVAL; 346 347 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 348 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 349 350 if (flags == HTE_BOTH_EDGES) { 351 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 352 } else if (flags == HTE_RISING_EDGE_TS) { 353 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 354 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 355 } else if (flags == HTE_FALLING_EDGE_TS) { 356 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 357 } 358 359 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 360 361 return 0; 362 } 363 364 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 365 unsigned long flags) 366 { 367 struct tegra_gpio *gpio; 368 void __iomem *base; 369 int value; 370 371 if (!gc) 372 return -EINVAL; 373 374 gpio = gpiochip_get_data(gc); 375 if (!gpio) 376 return -ENODEV; 377 378 base = tegra186_gpio_get_base(gpio, offset); 379 if (WARN_ON(base == NULL)) 380 return -EINVAL; 381 382 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 383 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 384 if (flags == HTE_BOTH_EDGES) { 385 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 386 } else if (flags == HTE_RISING_EDGE_TS) { 387 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 388 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 389 } else if (flags == HTE_FALLING_EDGE_TS) { 390 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 391 } 392 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 393 394 return 0; 395 } 396 397 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 398 { 399 struct tegra_gpio *gpio = gpiochip_get_data(chip); 400 void __iomem *base; 401 u32 value; 402 403 base = tegra186_gpio_get_base(gpio, offset); 404 if (WARN_ON(base == NULL)) 405 return -ENODEV; 406 407 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 408 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 409 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 410 else 411 value = readl(base + TEGRA186_GPIO_INPUT); 412 413 return value & BIT(0); 414 } 415 416 static int tegra186_gpio_set_config(struct gpio_chip *chip, 417 unsigned int offset, 418 unsigned long config) 419 { 420 struct tegra_gpio *gpio = gpiochip_get_data(chip); 421 u32 debounce, value; 422 void __iomem *base; 423 424 base = tegra186_gpio_get_base(gpio, offset); 425 if (base == NULL) 426 return -ENXIO; 427 428 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 429 return -ENOTSUPP; 430 431 debounce = pinconf_to_config_argument(config); 432 433 /* 434 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 435 * time. 436 */ 437 if (debounce > 255000) 438 return -EINVAL; 439 440 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 441 442 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 443 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 444 445 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 446 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 447 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 448 449 return 0; 450 } 451 452 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 453 { 454 struct tegra_gpio *gpio = gpiochip_get_data(chip); 455 struct pinctrl_dev *pctldev; 456 struct device_node *np; 457 unsigned int i, j; 458 int err; 459 460 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 461 return 0; 462 463 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 464 if (!np) 465 return -ENODEV; 466 467 pctldev = of_pinctrl_get(np); 468 of_node_put(np); 469 if (!pctldev) 470 return -EPROBE_DEFER; 471 472 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 473 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 474 const char *group = gpio->soc->pin_ranges[i].group; 475 476 port = pin / 8; 477 pin = pin % 8; 478 479 if (port >= gpio->soc->num_ports) { 480 dev_warn(chip->parent, "invalid port %u for %s\n", 481 port, group); 482 continue; 483 } 484 485 for (j = 0; j < port; j++) 486 pin += gpio->soc->ports[j].pins; 487 488 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 489 if (err < 0) 490 return err; 491 } 492 493 return 0; 494 } 495 496 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 497 const struct of_phandle_args *spec, 498 u32 *flags) 499 { 500 struct tegra_gpio *gpio = gpiochip_get_data(chip); 501 unsigned int port, pin, i, offset = 0; 502 503 if (WARN_ON(chip->of_gpio_n_cells < 2)) 504 return -EINVAL; 505 506 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 507 return -EINVAL; 508 509 port = spec->args[0] / 8; 510 pin = spec->args[0] % 8; 511 512 if (port >= gpio->soc->num_ports) { 513 dev_err(chip->parent, "invalid port number: %u\n", port); 514 return -EINVAL; 515 } 516 517 for (i = 0; i < port; i++) 518 offset += gpio->soc->ports[i].pins; 519 520 if (flags) 521 *flags = spec->args[1]; 522 523 return offset + pin; 524 } 525 526 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 527 528 static void tegra186_irq_ack(struct irq_data *data) 529 { 530 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 531 struct tegra_gpio *gpio = to_tegra_gpio(gc); 532 void __iomem *base; 533 534 base = tegra186_gpio_get_base(gpio, data->hwirq); 535 if (WARN_ON(base == NULL)) 536 return; 537 538 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 539 } 540 541 static void tegra186_irq_mask(struct irq_data *data) 542 { 543 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 544 struct tegra_gpio *gpio = to_tegra_gpio(gc); 545 void __iomem *base; 546 u32 value; 547 548 base = tegra186_gpio_get_base(gpio, data->hwirq); 549 if (WARN_ON(base == NULL)) 550 return; 551 552 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 553 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 554 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 555 556 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 557 } 558 559 static void tegra186_irq_unmask(struct irq_data *data) 560 { 561 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 562 struct tegra_gpio *gpio = to_tegra_gpio(gc); 563 void __iomem *base; 564 u32 value; 565 566 base = tegra186_gpio_get_base(gpio, data->hwirq); 567 if (WARN_ON(base == NULL)) 568 return; 569 570 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 571 572 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 573 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 574 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 575 } 576 577 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 578 { 579 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 580 struct tegra_gpio *gpio = to_tegra_gpio(gc); 581 void __iomem *base; 582 u32 value; 583 584 base = tegra186_gpio_get_base(gpio, data->hwirq); 585 if (WARN_ON(base == NULL)) 586 return -ENODEV; 587 588 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 589 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 590 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 591 592 switch (type & IRQ_TYPE_SENSE_MASK) { 593 case IRQ_TYPE_NONE: 594 break; 595 596 case IRQ_TYPE_EDGE_RISING: 597 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 598 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 599 break; 600 601 case IRQ_TYPE_EDGE_FALLING: 602 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 603 break; 604 605 case IRQ_TYPE_EDGE_BOTH: 606 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 607 break; 608 609 case IRQ_TYPE_LEVEL_HIGH: 610 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 611 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 612 break; 613 614 case IRQ_TYPE_LEVEL_LOW: 615 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 616 break; 617 618 default: 619 return -EINVAL; 620 } 621 622 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 623 624 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 625 irq_set_handler_locked(data, handle_level_irq); 626 else 627 irq_set_handler_locked(data, handle_edge_irq); 628 629 if (data->parent_data) 630 return irq_chip_set_type_parent(data, type); 631 632 return 0; 633 } 634 635 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 636 { 637 if (data->parent_data) 638 return irq_chip_set_wake_parent(data, on); 639 640 return 0; 641 } 642 643 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 644 { 645 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 646 647 seq_puts(p, dev_name(gc->parent)); 648 } 649 650 static const struct irq_chip tegra186_gpio_irq_chip = { 651 .irq_ack = tegra186_irq_ack, 652 .irq_mask = tegra186_irq_mask, 653 .irq_unmask = tegra186_irq_unmask, 654 .irq_set_type = tegra186_irq_set_type, 655 .irq_set_wake = tegra186_irq_set_wake, 656 .irq_print_chip = tegra186_irq_print_chip, 657 .flags = IRQCHIP_IMMUTABLE, 658 GPIOCHIP_IRQ_RESOURCE_HELPERS, 659 }; 660 661 static void tegra186_gpio_irq(struct irq_desc *desc) 662 { 663 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 664 struct irq_domain *domain = gpio->gpio.irq.domain; 665 struct irq_chip *chip = irq_desc_get_chip(desc); 666 unsigned int parent = irq_desc_get_irq(desc); 667 unsigned int i, j, offset = 0; 668 669 chained_irq_enter(chip, desc); 670 671 for (i = 0; i < gpio->soc->num_ports; i++) { 672 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 673 unsigned int pin; 674 unsigned long value; 675 void __iomem *base; 676 677 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 678 679 /* skip ports that are not associated with this bank */ 680 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 681 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 682 break; 683 } 684 685 if (j == gpio->num_irqs_per_bank) 686 goto skip; 687 688 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 689 690 for_each_set_bit(pin, &value, port->pins) { 691 int ret = generic_handle_domain_irq(domain, offset + pin); 692 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 693 } 694 695 skip: 696 offset += port->pins; 697 } 698 699 chained_irq_exit(chip, desc); 700 } 701 702 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 703 struct irq_fwspec *fwspec, 704 unsigned long *hwirq, 705 unsigned int *type) 706 { 707 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 708 unsigned int port, pin, i, offset = 0; 709 710 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 711 return -EINVAL; 712 713 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 714 return -EINVAL; 715 716 port = fwspec->param[0] / 8; 717 pin = fwspec->param[0] % 8; 718 719 if (port >= gpio->soc->num_ports) 720 return -EINVAL; 721 722 for (i = 0; i < port; i++) 723 offset += gpio->soc->ports[i].pins; 724 725 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 726 *hwirq = offset + pin; 727 728 return 0; 729 } 730 731 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 732 union gpio_irq_fwspec *gfwspec, 733 unsigned int parent_hwirq, 734 unsigned int parent_type) 735 { 736 struct tegra_gpio *gpio = gpiochip_get_data(chip); 737 struct irq_fwspec *fwspec = &gfwspec->fwspec; 738 739 fwspec->fwnode = chip->irq.parent_domain->fwnode; 740 fwspec->param_count = 3; 741 fwspec->param[0] = gpio->soc->instance; 742 fwspec->param[1] = parent_hwirq; 743 fwspec->param[2] = parent_type; 744 745 return 0; 746 } 747 748 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 749 unsigned int hwirq, 750 unsigned int type, 751 unsigned int *parent_hwirq, 752 unsigned int *parent_type) 753 { 754 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 755 *parent_type = type; 756 757 return 0; 758 } 759 760 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 761 unsigned int offset) 762 { 763 struct tegra_gpio *gpio = gpiochip_get_data(chip); 764 unsigned int i; 765 766 for (i = 0; i < gpio->soc->num_ports; i++) { 767 if (offset < gpio->soc->ports[i].pins) 768 break; 769 770 offset -= gpio->soc->ports[i].pins; 771 } 772 773 return offset + i * 8; 774 } 775 776 static const struct of_device_id tegra186_pmc_of_match[] = { 777 { .compatible = "nvidia,tegra186-pmc" }, 778 { .compatible = "nvidia,tegra194-pmc" }, 779 { .compatible = "nvidia,tegra234-pmc" }, 780 { /* sentinel */ } 781 }; 782 783 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 784 { 785 struct device *dev = gpio->gpio.parent; 786 unsigned int i; 787 u32 value; 788 789 for (i = 0; i < gpio->soc->num_ports; i++) { 790 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 791 unsigned int offset, p = port->port; 792 void __iomem *base; 793 794 base = gpio->secure + port->bank * 0x1000 + 0x800; 795 796 value = readl(base + TEGRA186_GPIO_CTL_SCR); 797 798 /* 799 * For controllers that haven't been locked down yet, make 800 * sure to program the default interrupt route mapping. 801 */ 802 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 803 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 804 /* 805 * On Tegra194 and later, each pin can be routed to one or more 806 * interrupts. 807 */ 808 dev_dbg(dev, "programming default interrupt routing for port %s\n", 809 port->name); 810 811 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0); 812 813 /* 814 * By default we only want to route GPIO pins to IRQ 0. This works 815 * only under the assumption that we're running as the host kernel 816 * and hence all GPIO pins are owned by Linux. 817 * 818 * For cases where Linux is the guest OS, the hypervisor will have 819 * to configure the interrupt routing and pass only the valid 820 * interrupts via device tree. 821 */ 822 value = readl(base + offset); 823 value = BIT(port->pins) - 1; 824 writel(value, base + offset); 825 } 826 } 827 } 828 829 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 830 { 831 struct device *dev = gpio->gpio.parent; 832 833 if (gpio->num_irq > gpio->num_banks) { 834 if (gpio->num_irq % gpio->num_banks != 0) 835 goto error; 836 } 837 838 if (gpio->num_irq < gpio->num_banks) 839 goto error; 840 841 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 842 843 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 844 goto error; 845 846 return 0; 847 848 error: 849 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 850 gpio->num_irq, gpio->num_banks); 851 return -EINVAL; 852 } 853 854 static int tegra186_gpio_probe(struct platform_device *pdev) 855 { 856 unsigned int i, j, offset; 857 struct gpio_irq_chip *irq; 858 struct tegra_gpio *gpio; 859 struct device_node *np; 860 struct resource *res; 861 char **names; 862 int node, err; 863 864 err = platform_irq_count(pdev); 865 if (err < 0) 866 return err; 867 868 gpio = devm_kzalloc(&pdev->dev, struct_size(gpio, irq, err), GFP_KERNEL); 869 if (!gpio) 870 return -ENOMEM; 871 872 gpio->num_irq = err; 873 874 gpio->soc = device_get_match_data(&pdev->dev); 875 gpio->gpio.label = gpio->soc->name; 876 gpio->gpio.parent = &pdev->dev; 877 878 /* count the number of banks in the controller */ 879 for (i = 0; i < gpio->soc->num_ports; i++) 880 if (gpio->soc->ports[i].bank > gpio->num_banks) 881 gpio->num_banks = gpio->soc->ports[i].bank; 882 883 gpio->num_banks++; 884 885 /* get register apertures */ 886 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security"); 887 if (!res) 888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 889 gpio->secure = devm_ioremap_resource(&pdev->dev, res); 890 if (IS_ERR(gpio->secure)) 891 return PTR_ERR(gpio->secure); 892 893 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); 894 if (!res) 895 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 896 gpio->base = devm_ioremap_resource(&pdev->dev, res); 897 if (IS_ERR(gpio->base)) 898 return PTR_ERR(gpio->base); 899 900 err = tegra186_gpio_irqs_per_bank(gpio); 901 if (err < 0) 902 return err; 903 904 for (i = 0; i < gpio->num_irq; i++) { 905 err = platform_get_irq(pdev, i); 906 if (err < 0) 907 return err; 908 909 gpio->irq[i] = err; 910 } 911 912 gpio->gpio.request = gpiochip_generic_request; 913 gpio->gpio.free = gpiochip_generic_free; 914 gpio->gpio.get_direction = tegra186_gpio_get_direction; 915 gpio->gpio.direction_input = tegra186_gpio_direction_input; 916 gpio->gpio.direction_output = tegra186_gpio_direction_output; 917 gpio->gpio.get = tegra186_gpio_get; 918 gpio->gpio.set = tegra186_gpio_set; 919 gpio->gpio.set_config = tegra186_gpio_set_config; 920 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 921 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; 922 if (gpio->soc->has_gte) { 923 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 924 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 925 } 926 927 gpio->gpio.base = -1; 928 929 for (i = 0; i < gpio->soc->num_ports; i++) 930 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 931 932 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 933 sizeof(*names), GFP_KERNEL); 934 if (!names) 935 return -ENOMEM; 936 937 node = dev_to_node(&pdev->dev); 938 939 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 940 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 941 char *name; 942 943 for (j = 0; j < port->pins; j++) { 944 if (node >= 0) 945 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 946 "%d-%sP%s.%02x", node, 947 gpio->soc->prefix ?: "", 948 port->name, j); 949 else 950 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 951 "%sP%s.%02x", 952 gpio->soc->prefix ?: "", 953 port->name, j); 954 if (!name) 955 return -ENOMEM; 956 957 names[offset + j] = name; 958 } 959 960 offset += port->pins; 961 } 962 963 gpio->gpio.names = (const char * const *)names; 964 965 #if defined(CONFIG_OF_GPIO) 966 gpio->gpio.of_gpio_n_cells = 2; 967 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 968 #endif /* CONFIG_OF_GPIO */ 969 970 irq = &gpio->gpio.irq; 971 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 972 irq->fwnode = dev_fwnode(&pdev->dev); 973 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 974 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 975 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 976 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 977 irq->handler = handle_simple_irq; 978 irq->default_type = IRQ_TYPE_NONE; 979 irq->parent_handler = tegra186_gpio_irq; 980 irq->parent_handler_data = gpio; 981 irq->num_parents = gpio->num_irq; 982 983 /* 984 * To simplify things, use a single interrupt per bank for now. Some 985 * chips support up to 8 interrupts per bank, which can be useful to 986 * distribute the load and decrease the processing latency for GPIOs 987 * but it also requires a more complicated interrupt routing than we 988 * currently program. 989 */ 990 if (gpio->num_irqs_per_bank > 1) { 991 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 992 sizeof(*irq->parents), GFP_KERNEL); 993 if (!irq->parents) 994 return -ENOMEM; 995 996 for (i = 0; i < gpio->num_banks; i++) 997 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 998 999 irq->num_parents = gpio->num_banks; 1000 } else { 1001 irq->num_parents = gpio->num_irq; 1002 irq->parents = gpio->irq; 1003 } 1004 1005 if (gpio->soc->num_irqs_per_bank > 1) 1006 tegra186_gpio_init_route_mapping(gpio); 1007 1008 np = of_parse_phandle(pdev->dev.of_node, "wakeup-parent", 0); 1009 if (!np) 1010 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 1011 if (np) { 1012 if (of_device_is_available(np)) { 1013 irq->parent_domain = irq_find_host(np); 1014 of_node_put(np); 1015 1016 if (!irq->parent_domain) 1017 return -EPROBE_DEFER; 1018 } else { 1019 of_node_put(np); 1020 } 1021 } 1022 1023 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 1024 sizeof(*irq->map), GFP_KERNEL); 1025 if (!irq->map) 1026 return -ENOMEM; 1027 1028 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 1029 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 1030 1031 for (j = 0; j < port->pins; j++) 1032 irq->map[offset + j] = irq->parents[port->bank]; 1033 1034 offset += port->pins; 1035 } 1036 1037 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 1038 } 1039 1040 #define TEGRA_GPIO_PORT(_prefix, _name, _bank, _port, _pins) \ 1041 [_prefix##_GPIO_PORT_##_name] = { \ 1042 .name = #_name, \ 1043 .bank = _bank, \ 1044 .port = _port, \ 1045 .pins = _pins, \ 1046 } 1047 1048 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1049 TEGRA_GPIO_PORT(TEGRA186_MAIN, _name, _bank, _port, _pins) 1050 1051 static const struct tegra_gpio_port tegra186_main_ports[] = { 1052 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 1053 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 1054 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 1055 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 1056 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 1057 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 1058 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 1059 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 1060 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 1061 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 1062 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 1063 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 1064 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 1065 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 1066 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 1067 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 1068 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 1069 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 1070 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 1071 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 1072 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 1073 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 1074 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 1075 }; 1076 1077 static const struct tegra_gpio_soc tegra186_main_soc = { 1078 .num_ports = ARRAY_SIZE(tegra186_main_ports), 1079 .ports = tegra186_main_ports, 1080 .name = "tegra186-gpio", 1081 .instance = 0, 1082 .num_irqs_per_bank = 1, 1083 .has_vm_support = false, 1084 }; 1085 1086 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1087 TEGRA_GPIO_PORT(TEGRA186_AON, _name, _bank, _port, _pins) 1088 1089 static const struct tegra_gpio_port tegra186_aon_ports[] = { 1090 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 1091 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 1092 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 1093 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 1094 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 1095 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 1096 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 1097 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 1098 }; 1099 1100 static const struct tegra_gpio_soc tegra186_aon_soc = { 1101 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 1102 .ports = tegra186_aon_ports, 1103 .name = "tegra186-gpio-aon", 1104 .instance = 1, 1105 .num_irqs_per_bank = 1, 1106 .has_vm_support = false, 1107 }; 1108 1109 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1110 TEGRA_GPIO_PORT(TEGRA194_MAIN, _name, _bank, _port, _pins) 1111 1112 static const struct tegra_gpio_port tegra194_main_ports[] = { 1113 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1114 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1115 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1116 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1117 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1118 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1119 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1120 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1121 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1122 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1123 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1124 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1125 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1126 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1127 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1128 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1129 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1130 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1131 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1132 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1133 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1134 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1135 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1136 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1137 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1138 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1139 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1140 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1141 }; 1142 1143 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1144 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1145 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1146 }; 1147 1148 static const struct tegra_gpio_soc tegra194_main_soc = { 1149 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1150 .ports = tegra194_main_ports, 1151 .name = "tegra194-gpio", 1152 .instance = 0, 1153 .num_irqs_per_bank = 8, 1154 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1155 .pin_ranges = tegra194_main_pin_ranges, 1156 .pinmux = "nvidia,tegra194-pinmux", 1157 .has_vm_support = true, 1158 }; 1159 1160 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1161 TEGRA_GPIO_PORT(TEGRA194_AON, _name, _bank, _port, _pins) 1162 1163 static const struct tegra_gpio_port tegra194_aon_ports[] = { 1164 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1165 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1166 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1167 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1168 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1169 }; 1170 1171 static const struct tegra_gpio_soc tegra194_aon_soc = { 1172 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1173 .ports = tegra194_aon_ports, 1174 .name = "tegra194-gpio-aon", 1175 .instance = 1, 1176 .num_irqs_per_bank = 8, 1177 .has_gte = true, 1178 .has_vm_support = false, 1179 }; 1180 1181 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1182 TEGRA_GPIO_PORT(TEGRA234_MAIN, _name, _bank, _port, _pins) 1183 1184 static const struct tegra_gpio_port tegra234_main_ports[] = { 1185 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1186 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1187 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1188 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1189 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1190 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1191 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1192 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1193 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1194 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1195 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1196 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1197 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1198 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1199 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1200 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1201 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1202 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1203 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1204 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1205 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1206 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1207 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1208 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1209 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1210 }; 1211 1212 static const struct tegra_gpio_soc tegra234_main_soc = { 1213 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1214 .ports = tegra234_main_ports, 1215 .name = "tegra234-gpio", 1216 .instance = 0, 1217 .num_irqs_per_bank = 8, 1218 .has_vm_support = true, 1219 }; 1220 1221 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1222 TEGRA_GPIO_PORT(TEGRA234_AON, _name, _bank, _port, _pins) 1223 1224 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1225 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1226 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1227 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1228 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1229 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1230 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1231 }; 1232 1233 static const struct tegra_gpio_soc tegra234_aon_soc = { 1234 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1235 .ports = tegra234_aon_ports, 1236 .name = "tegra234-gpio-aon", 1237 .instance = 1, 1238 .num_irqs_per_bank = 8, 1239 .has_gte = true, 1240 .has_vm_support = false, 1241 }; 1242 1243 #define TEGRA238_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1244 TEGRA_GPIO_PORT(TEGRA238_MAIN, _name, _bank, _port, _pins) 1245 1246 static const struct tegra_gpio_port tegra238_main_ports[] = { 1247 TEGRA238_MAIN_GPIO_PORT(A, 0, 0, 8), 1248 TEGRA238_MAIN_GPIO_PORT(B, 0, 1, 5), 1249 TEGRA238_MAIN_GPIO_PORT(C, 0, 2, 8), 1250 TEGRA238_MAIN_GPIO_PORT(D, 0, 3, 8), 1251 TEGRA238_MAIN_GPIO_PORT(E, 0, 4, 4), 1252 TEGRA238_MAIN_GPIO_PORT(F, 0, 5, 8), 1253 TEGRA238_MAIN_GPIO_PORT(G, 0, 6, 8), 1254 TEGRA238_MAIN_GPIO_PORT(H, 0, 7, 6), 1255 TEGRA238_MAIN_GPIO_PORT(J, 1, 0, 8), 1256 TEGRA238_MAIN_GPIO_PORT(K, 1, 1, 4), 1257 TEGRA238_MAIN_GPIO_PORT(L, 1, 2, 8), 1258 TEGRA238_MAIN_GPIO_PORT(M, 1, 3, 8), 1259 TEGRA238_MAIN_GPIO_PORT(N, 1, 4, 3), 1260 TEGRA238_MAIN_GPIO_PORT(P, 1, 5, 8), 1261 TEGRA238_MAIN_GPIO_PORT(Q, 1, 6, 3), 1262 TEGRA238_MAIN_GPIO_PORT(R, 2, 0, 8), 1263 TEGRA238_MAIN_GPIO_PORT(S, 2, 1, 8), 1264 TEGRA238_MAIN_GPIO_PORT(T, 2, 2, 8), 1265 TEGRA238_MAIN_GPIO_PORT(U, 2, 3, 6), 1266 TEGRA238_MAIN_GPIO_PORT(V, 2, 4, 2), 1267 TEGRA238_MAIN_GPIO_PORT(W, 3, 0, 8), 1268 TEGRA238_MAIN_GPIO_PORT(X, 3, 1, 2) 1269 }; 1270 1271 static const struct tegra_gpio_soc tegra238_main_soc = { 1272 .num_ports = ARRAY_SIZE(tegra238_main_ports), 1273 .ports = tegra238_main_ports, 1274 .name = "tegra238-gpio", 1275 .instance = 0, 1276 .num_irqs_per_bank = 8, 1277 .has_vm_support = true, 1278 }; 1279 1280 #define TEGRA238_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1281 TEGRA_GPIO_PORT(TEGRA238_AON, _name, _bank, _port, _pins) 1282 1283 static const struct tegra_gpio_port tegra238_aon_ports[] = { 1284 TEGRA238_AON_GPIO_PORT(AA, 0, 0, 8), 1285 TEGRA238_AON_GPIO_PORT(BB, 0, 1, 1), 1286 TEGRA238_AON_GPIO_PORT(CC, 0, 2, 8), 1287 TEGRA238_AON_GPIO_PORT(DD, 0, 3, 8), 1288 TEGRA238_AON_GPIO_PORT(EE, 0, 4, 6), 1289 TEGRA238_AON_GPIO_PORT(FF, 0, 5, 8), 1290 TEGRA238_AON_GPIO_PORT(GG, 0, 6, 8), 1291 TEGRA238_AON_GPIO_PORT(HH, 0, 7, 4) 1292 }; 1293 1294 static const struct tegra_gpio_soc tegra238_aon_soc = { 1295 .num_ports = ARRAY_SIZE(tegra238_aon_ports), 1296 .ports = tegra238_aon_ports, 1297 .name = "tegra238-gpio-aon", 1298 .instance = 1, 1299 .num_irqs_per_bank = 8, 1300 .has_gte = true, 1301 .has_vm_support = false, 1302 }; 1303 1304 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1305 TEGRA_GPIO_PORT(TEGRA241_MAIN, _name, _bank, _port, _pins) 1306 1307 static const struct tegra_gpio_port tegra241_main_ports[] = { 1308 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1309 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1310 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1311 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1312 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1313 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1314 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1315 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1316 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1317 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1318 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1319 }; 1320 1321 static const struct tegra_gpio_soc tegra241_main_soc = { 1322 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1323 .ports = tegra241_main_ports, 1324 .name = "tegra241-gpio", 1325 .instance = 0, 1326 .num_irqs_per_bank = 8, 1327 .has_vm_support = false, 1328 }; 1329 1330 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1331 TEGRA_GPIO_PORT(TEGRA241_AON, _name, _bank, _port, _pins) 1332 1333 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1334 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1335 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1336 }; 1337 1338 static const struct tegra_gpio_soc tegra241_aon_soc = { 1339 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1340 .ports = tegra241_aon_ports, 1341 .name = "tegra241-gpio-aon", 1342 .instance = 1, 1343 .num_irqs_per_bank = 8, 1344 .has_vm_support = false, 1345 }; 1346 1347 #define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1348 TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins) 1349 1350 static const struct tegra_gpio_port tegra264_main_ports[] = { 1351 TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8), 1352 TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5), 1353 TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8), 1354 TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8), 1355 TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8), 1356 TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8), 1357 TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6), 1358 TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8), 1359 TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8), 1360 TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8), 1361 TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2), 1362 TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7), 1363 TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8), 1364 TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8), 1365 TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8), 1366 TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6), 1367 TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8), 1368 TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8), 1369 TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3), 1370 }; 1371 1372 static const struct tegra_gpio_soc tegra264_main_soc = { 1373 .num_ports = ARRAY_SIZE(tegra264_main_ports), 1374 .ports = tegra264_main_ports, 1375 .name = "tegra264-gpio", 1376 .instance = 0, 1377 .num_irqs_per_bank = 8, 1378 .has_vm_support = true, 1379 }; 1380 1381 #define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1382 TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins) 1383 1384 static const struct tegra_gpio_port tegra264_aon_ports[] = { 1385 TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8), 1386 TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2), 1387 TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8), 1388 TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8), 1389 TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4) 1390 }; 1391 1392 static const struct tegra_gpio_soc tegra264_aon_soc = { 1393 .num_ports = ARRAY_SIZE(tegra264_aon_ports), 1394 .ports = tegra264_aon_ports, 1395 .name = "tegra264-gpio-aon", 1396 .instance = 1, 1397 .num_irqs_per_bank = 8, 1398 .has_gte = true, 1399 .has_vm_support = true, 1400 }; 1401 1402 #define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \ 1403 TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins) 1404 1405 static const struct tegra_gpio_port tegra264_uphy_ports[] = { 1406 TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6), 1407 TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8), 1408 TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3), 1409 TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8), 1410 TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4), 1411 }; 1412 1413 static const struct tegra_gpio_soc tegra264_uphy_soc = { 1414 .num_ports = ARRAY_SIZE(tegra264_uphy_ports), 1415 .ports = tegra264_uphy_ports, 1416 .name = "tegra264-gpio-uphy", 1417 .instance = 2, 1418 .num_irqs_per_bank = 8, 1419 .has_vm_support = true, 1420 }; 1421 1422 #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1423 TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins) 1424 1425 static const struct tegra_gpio_port tegra256_main_ports[] = { 1426 TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), 1427 TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), 1428 TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), 1429 TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), 1430 }; 1431 1432 static const struct tegra_gpio_soc tegra256_main_soc = { 1433 .num_ports = ARRAY_SIZE(tegra256_main_ports), 1434 .ports = tegra256_main_ports, 1435 .name = "tegra256-gpio-main", 1436 .instance = 1, 1437 .num_irqs_per_bank = 8, 1438 .has_vm_support = true, 1439 }; 1440 1441 /* Macro to define GPIO name prefix with separator */ 1442 #define TEGRA_GPIO_PREFIX(_x) _x "-" 1443 1444 #define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \ 1445 TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins) 1446 1447 static const struct tegra_gpio_port tegra410_compute_ports[] = { 1448 TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3), 1449 TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8), 1450 TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3), 1451 TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8), 1452 TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8), 1453 }; 1454 1455 static const struct tegra_gpio_soc tegra410_compute_soc = { 1456 .num_ports = ARRAY_SIZE(tegra410_compute_ports), 1457 .ports = tegra410_compute_ports, 1458 .name = "tegra410-gpio-compute", 1459 .prefix = TEGRA_GPIO_PREFIX("COMPUTE"), 1460 .num_irqs_per_bank = 8, 1461 .instance = 0, 1462 }; 1463 1464 #define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \ 1465 TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins) 1466 1467 static const struct tegra_gpio_port tegra410_system_ports[] = { 1468 TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7), 1469 TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8), 1470 TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8), 1471 TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8), 1472 TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6), 1473 TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8), 1474 TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7), 1475 TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7), 1476 TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7), 1477 TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7), 1478 TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6), 1479 TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8), 1480 TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3), 1481 TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2), 1482 TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2), 1483 }; 1484 1485 static const struct tegra_gpio_soc tegra410_system_soc = { 1486 .num_ports = ARRAY_SIZE(tegra410_system_ports), 1487 .ports = tegra410_system_ports, 1488 .name = "tegra410-gpio-system", 1489 .prefix = TEGRA_GPIO_PREFIX("SYSTEM"), 1490 .num_irqs_per_bank = 8, 1491 .instance = 0, 1492 }; 1493 1494 static const struct of_device_id tegra186_gpio_of_match[] = { 1495 { 1496 .compatible = "nvidia,tegra186-gpio", 1497 .data = &tegra186_main_soc 1498 }, { 1499 .compatible = "nvidia,tegra186-gpio-aon", 1500 .data = &tegra186_aon_soc 1501 }, { 1502 .compatible = "nvidia,tegra194-gpio", 1503 .data = &tegra194_main_soc 1504 }, { 1505 .compatible = "nvidia,tegra194-gpio-aon", 1506 .data = &tegra194_aon_soc 1507 }, { 1508 .compatible = "nvidia,tegra234-gpio", 1509 .data = &tegra234_main_soc 1510 }, { 1511 .compatible = "nvidia,tegra234-gpio-aon", 1512 .data = &tegra234_aon_soc 1513 }, { 1514 .compatible = "nvidia,tegra238-gpio", 1515 .data = &tegra238_main_soc 1516 }, { 1517 .compatible = "nvidia,tegra238-gpio-aon", 1518 .data = &tegra238_aon_soc 1519 }, { 1520 .compatible = "nvidia,tegra256-gpio", 1521 .data = &tegra256_main_soc 1522 }, { 1523 .compatible = "nvidia,tegra264-gpio", 1524 .data = &tegra264_main_soc 1525 }, { 1526 .compatible = "nvidia,tegra264-gpio-aon", 1527 .data = &tegra264_aon_soc 1528 }, { 1529 .compatible = "nvidia,tegra264-gpio-uphy", 1530 .data = &tegra264_uphy_soc 1531 }, { 1532 /* sentinel */ 1533 } 1534 }; 1535 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1536 1537 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1538 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1539 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1540 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1541 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1542 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1543 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1544 { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc }, 1545 { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc }, 1546 {} 1547 }; 1548 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1549 1550 static struct platform_driver tegra186_gpio_driver = { 1551 .driver = { 1552 .name = "tegra186-gpio", 1553 .of_match_table = tegra186_gpio_of_match, 1554 .acpi_match_table = tegra186_gpio_acpi_match, 1555 }, 1556 .probe = tegra186_gpio_probe, 1557 }; 1558 module_platform_driver(tegra186_gpio_driver); 1559 1560 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1561 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1562 MODULE_LICENSE("GPL v2"); 1563