1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2022 NVIDIA Corporation 4 * 5 * Author: Thierry Reding <treding@nvidia.com> 6 * Dipen Patel <dpatel@nvidia.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/hte.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/seq_file.h> 18 19 #include <dt-bindings/gpio/tegra186-gpio.h> 20 #include <dt-bindings/gpio/tegra194-gpio.h> 21 #include <dt-bindings/gpio/tegra234-gpio.h> 22 #include <dt-bindings/gpio/tegra241-gpio.h> 23 #include <dt-bindings/gpio/tegra256-gpio.h> 24 25 /* security registers */ 26 #define TEGRA186_GPIO_CTL_SCR 0x0c 27 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) 28 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) 29 30 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) 31 32 #define TEGRA186_GPIO_VM 0x00 33 #define TEGRA186_GPIO_VM_RW_MASK 0x03 34 #define TEGRA186_GPIO_SCR 0x04 35 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 36 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 37 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) 38 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27) 39 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) 40 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) 41 42 /* control registers */ 43 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 44 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 45 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 46 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) 47 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) 48 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) 49 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) 50 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) 51 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) 52 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) 53 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) 54 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) 55 56 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 57 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) 58 59 #define TEGRA186_GPIO_INPUT 0x08 60 #define TEGRA186_GPIO_INPUT_HIGH BIT(0) 61 62 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 63 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 64 65 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 66 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) 67 68 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 69 70 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) 71 72 struct tegra_gpio_port { 73 const char *name; 74 unsigned int bank; 75 unsigned int port; 76 unsigned int pins; 77 }; 78 79 struct tegra186_pin_range { 80 unsigned int offset; 81 const char *group; 82 }; 83 84 struct tegra_gpio_soc { 85 const struct tegra_gpio_port *ports; 86 unsigned int num_ports; 87 const char *name; 88 unsigned int instance; 89 90 unsigned int num_irqs_per_bank; 91 92 const struct tegra186_pin_range *pin_ranges; 93 unsigned int num_pin_ranges; 94 const char *pinmux; 95 bool has_gte; 96 bool has_vm_support; 97 }; 98 99 struct tegra_gpio { 100 struct gpio_chip gpio; 101 unsigned int num_irq; 102 unsigned int *irq; 103 104 const struct tegra_gpio_soc *soc; 105 unsigned int num_irqs_per_bank; 106 unsigned int num_banks; 107 108 void __iomem *secure; 109 void __iomem *base; 110 }; 111 112 static const struct tegra_gpio_port * 113 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) 114 { 115 unsigned int start = 0, i; 116 117 for (i = 0; i < gpio->soc->num_ports; i++) { 118 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 119 120 if (*pin >= start && *pin < start + port->pins) { 121 *pin -= start; 122 return port; 123 } 124 125 start += port->pins; 126 } 127 128 return NULL; 129 } 130 131 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, 132 unsigned int pin) 133 { 134 const struct tegra_gpio_port *port; 135 unsigned int offset; 136 137 port = tegra186_gpio_get_port(gpio, &pin); 138 if (!port) 139 return NULL; 140 141 offset = port->bank * 0x1000 + port->port * 0x200; 142 143 return gpio->base + offset + pin * 0x20; 144 } 145 146 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, 147 unsigned int pin) 148 { 149 const struct tegra_gpio_port *port; 150 unsigned int offset; 151 152 port = tegra186_gpio_get_port(gpio, &pin); 153 if (!port) 154 return NULL; 155 156 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; 157 158 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; 159 } 160 161 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin) 162 { 163 void __iomem *secure; 164 u32 value; 165 166 secure = tegra186_gpio_get_secure_base(gpio, pin); 167 168 if (gpio->soc->has_vm_support) { 169 value = readl(secure + TEGRA186_GPIO_VM); 170 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) 171 return false; 172 } 173 174 value = __raw_readl(secure + TEGRA186_GPIO_SCR); 175 176 /* 177 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the 178 * registers for given GPIO pin. 179 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying 180 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given 181 * GPIO pin. 182 */ 183 184 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 || 185 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) && 186 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 || 187 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W)))) 188 return true; 189 190 return false; 191 } 192 193 static int tegra186_init_valid_mask(struct gpio_chip *chip, 194 unsigned long *valid_mask, unsigned int ngpios) 195 { 196 struct tegra_gpio *gpio = gpiochip_get_data(chip); 197 unsigned int j; 198 199 for (j = 0; j < ngpios; j++) { 200 if (!tegra186_gpio_is_accessible(gpio, j)) 201 clear_bit(j, valid_mask); 202 } 203 return 0; 204 } 205 206 static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, 207 int level) 208 { 209 struct tegra_gpio *gpio = gpiochip_get_data(chip); 210 void __iomem *base; 211 u32 value; 212 213 base = tegra186_gpio_get_base(gpio, offset); 214 if (WARN_ON(base == NULL)) 215 return -ENODEV; 216 217 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 218 if (level == 0) 219 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 220 else 221 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; 222 223 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); 224 225 return 0; 226 } 227 228 static int tegra186_gpio_get_direction(struct gpio_chip *chip, 229 unsigned int offset) 230 { 231 struct tegra_gpio *gpio = gpiochip_get_data(chip); 232 void __iomem *base; 233 u32 value; 234 235 base = tegra186_gpio_get_base(gpio, offset); 236 if (WARN_ON(base == NULL)) 237 return -ENODEV; 238 239 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 240 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 241 return GPIO_LINE_DIRECTION_OUT; 242 243 return GPIO_LINE_DIRECTION_IN; 244 } 245 246 static int tegra186_gpio_direction_input(struct gpio_chip *chip, 247 unsigned int offset) 248 { 249 struct tegra_gpio *gpio = gpiochip_get_data(chip); 250 void __iomem *base; 251 u32 value; 252 253 base = tegra186_gpio_get_base(gpio, offset); 254 if (WARN_ON(base == NULL)) 255 return -ENODEV; 256 257 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 258 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 259 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 260 261 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 262 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 263 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; 264 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 265 266 return 0; 267 } 268 269 static int tegra186_gpio_direction_output(struct gpio_chip *chip, 270 unsigned int offset, int level) 271 { 272 struct tegra_gpio *gpio = gpiochip_get_data(chip); 273 void __iomem *base; 274 u32 value; 275 int ret; 276 277 /* configure output level first */ 278 ret = tegra186_gpio_set(chip, offset, level); 279 if (ret) 280 return ret; 281 282 base = tegra186_gpio_get_base(gpio, offset); 283 if (WARN_ON(base == NULL)) 284 return -EINVAL; 285 286 /* set the direction */ 287 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); 288 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; 289 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); 290 291 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 292 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; 293 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; 294 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 295 296 return 0; 297 } 298 299 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) 300 301 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, 302 unsigned long flags) 303 { 304 struct tegra_gpio *gpio; 305 void __iomem *base; 306 int value; 307 308 if (!gc) 309 return -EINVAL; 310 311 gpio = gpiochip_get_data(gc); 312 if (!gpio) 313 return -ENODEV; 314 315 base = tegra186_gpio_get_base(gpio, offset); 316 if (WARN_ON(base == NULL)) 317 return -EINVAL; 318 319 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 320 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 321 322 if (flags == HTE_BOTH_EDGES) { 323 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 324 } else if (flags == HTE_RISING_EDGE_TS) { 325 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 326 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 327 } else if (flags == HTE_FALLING_EDGE_TS) { 328 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 329 } 330 331 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 332 333 return 0; 334 } 335 336 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, 337 unsigned long flags) 338 { 339 struct tegra_gpio *gpio; 340 void __iomem *base; 341 int value; 342 343 if (!gc) 344 return -EINVAL; 345 346 gpio = gpiochip_get_data(gc); 347 if (!gpio) 348 return -ENODEV; 349 350 base = tegra186_gpio_get_base(gpio, offset); 351 if (WARN_ON(base == NULL)) 352 return -EINVAL; 353 354 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 355 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; 356 if (flags == HTE_BOTH_EDGES) { 357 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 358 } else if (flags == HTE_RISING_EDGE_TS) { 359 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 360 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 361 } else if (flags == HTE_FALLING_EDGE_TS) { 362 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 363 } 364 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 365 366 return 0; 367 } 368 369 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) 370 { 371 struct tegra_gpio *gpio = gpiochip_get_data(chip); 372 void __iomem *base; 373 u32 value; 374 375 base = tegra186_gpio_get_base(gpio, offset); 376 if (WARN_ON(base == NULL)) 377 return -ENODEV; 378 379 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 380 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) 381 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); 382 else 383 value = readl(base + TEGRA186_GPIO_INPUT); 384 385 return value & BIT(0); 386 } 387 388 static int tegra186_gpio_set_config(struct gpio_chip *chip, 389 unsigned int offset, 390 unsigned long config) 391 { 392 struct tegra_gpio *gpio = gpiochip_get_data(chip); 393 u32 debounce, value; 394 void __iomem *base; 395 396 base = tegra186_gpio_get_base(gpio, offset); 397 if (base == NULL) 398 return -ENXIO; 399 400 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 401 return -ENOTSUPP; 402 403 debounce = pinconf_to_config_argument(config); 404 405 /* 406 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce 407 * time. 408 */ 409 if (debounce > 255000) 410 return -EINVAL; 411 412 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); 413 414 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); 415 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); 416 417 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 418 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; 419 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 420 421 return 0; 422 } 423 424 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) 425 { 426 struct tegra_gpio *gpio = gpiochip_get_data(chip); 427 struct pinctrl_dev *pctldev; 428 struct device_node *np; 429 unsigned int i, j; 430 int err; 431 432 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) 433 return 0; 434 435 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); 436 if (!np) 437 return -ENODEV; 438 439 pctldev = of_pinctrl_get(np); 440 of_node_put(np); 441 if (!pctldev) 442 return -EPROBE_DEFER; 443 444 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { 445 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; 446 const char *group = gpio->soc->pin_ranges[i].group; 447 448 port = pin / 8; 449 pin = pin % 8; 450 451 if (port >= gpio->soc->num_ports) { 452 dev_warn(chip->parent, "invalid port %u for %s\n", 453 port, group); 454 continue; 455 } 456 457 for (j = 0; j < port; j++) 458 pin += gpio->soc->ports[j].pins; 459 460 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); 461 if (err < 0) 462 return err; 463 } 464 465 return 0; 466 } 467 468 static int tegra186_gpio_of_xlate(struct gpio_chip *chip, 469 const struct of_phandle_args *spec, 470 u32 *flags) 471 { 472 struct tegra_gpio *gpio = gpiochip_get_data(chip); 473 unsigned int port, pin, i, offset = 0; 474 475 if (WARN_ON(chip->of_gpio_n_cells < 2)) 476 return -EINVAL; 477 478 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) 479 return -EINVAL; 480 481 port = spec->args[0] / 8; 482 pin = spec->args[0] % 8; 483 484 if (port >= gpio->soc->num_ports) { 485 dev_err(chip->parent, "invalid port number: %u\n", port); 486 return -EINVAL; 487 } 488 489 for (i = 0; i < port; i++) 490 offset += gpio->soc->ports[i].pins; 491 492 if (flags) 493 *flags = spec->args[1]; 494 495 return offset + pin; 496 } 497 498 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio) 499 500 static void tegra186_irq_ack(struct irq_data *data) 501 { 502 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 503 struct tegra_gpio *gpio = to_tegra_gpio(gc); 504 void __iomem *base; 505 506 base = tegra186_gpio_get_base(gpio, data->hwirq); 507 if (WARN_ON(base == NULL)) 508 return; 509 510 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); 511 } 512 513 static void tegra186_irq_mask(struct irq_data *data) 514 { 515 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 516 struct tegra_gpio *gpio = to_tegra_gpio(gc); 517 void __iomem *base; 518 u32 value; 519 520 base = tegra186_gpio_get_base(gpio, data->hwirq); 521 if (WARN_ON(base == NULL)) 522 return; 523 524 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 525 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 526 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 527 528 gpiochip_disable_irq(&gpio->gpio, data->hwirq); 529 } 530 531 static void tegra186_irq_unmask(struct irq_data *data) 532 { 533 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 534 struct tegra_gpio *gpio = to_tegra_gpio(gc); 535 void __iomem *base; 536 u32 value; 537 538 base = tegra186_gpio_get_base(gpio, data->hwirq); 539 if (WARN_ON(base == NULL)) 540 return; 541 542 gpiochip_enable_irq(&gpio->gpio, data->hwirq); 543 544 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 545 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; 546 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 547 } 548 549 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) 550 { 551 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 552 struct tegra_gpio *gpio = to_tegra_gpio(gc); 553 void __iomem *base; 554 u32 value; 555 556 base = tegra186_gpio_get_base(gpio, data->hwirq); 557 if (WARN_ON(base == NULL)) 558 return -ENODEV; 559 560 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); 561 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; 562 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 563 564 switch (type & IRQ_TYPE_SENSE_MASK) { 565 case IRQ_TYPE_NONE: 566 break; 567 568 case IRQ_TYPE_EDGE_RISING: 569 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 570 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 571 break; 572 573 case IRQ_TYPE_EDGE_FALLING: 574 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; 575 break; 576 577 case IRQ_TYPE_EDGE_BOTH: 578 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; 579 break; 580 581 case IRQ_TYPE_LEVEL_HIGH: 582 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 583 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; 584 break; 585 586 case IRQ_TYPE_LEVEL_LOW: 587 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; 588 break; 589 590 default: 591 return -EINVAL; 592 } 593 594 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); 595 596 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) 597 irq_set_handler_locked(data, handle_level_irq); 598 else 599 irq_set_handler_locked(data, handle_edge_irq); 600 601 if (data->parent_data) 602 return irq_chip_set_type_parent(data, type); 603 604 return 0; 605 } 606 607 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) 608 { 609 if (data->parent_data) 610 return irq_chip_set_wake_parent(data, on); 611 612 return 0; 613 } 614 615 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p) 616 { 617 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 618 619 seq_puts(p, dev_name(gc->parent)); 620 } 621 622 static const struct irq_chip tegra186_gpio_irq_chip = { 623 .irq_ack = tegra186_irq_ack, 624 .irq_mask = tegra186_irq_mask, 625 .irq_unmask = tegra186_irq_unmask, 626 .irq_set_type = tegra186_irq_set_type, 627 .irq_set_wake = tegra186_irq_set_wake, 628 .irq_print_chip = tegra186_irq_print_chip, 629 .flags = IRQCHIP_IMMUTABLE, 630 GPIOCHIP_IRQ_RESOURCE_HELPERS, 631 }; 632 633 static void tegra186_gpio_irq(struct irq_desc *desc) 634 { 635 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); 636 struct irq_domain *domain = gpio->gpio.irq.domain; 637 struct irq_chip *chip = irq_desc_get_chip(desc); 638 unsigned int parent = irq_desc_get_irq(desc); 639 unsigned int i, j, offset = 0; 640 641 chained_irq_enter(chip, desc); 642 643 for (i = 0; i < gpio->soc->num_ports; i++) { 644 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 645 unsigned int pin; 646 unsigned long value; 647 void __iomem *base; 648 649 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; 650 651 /* skip ports that are not associated with this bank */ 652 for (j = 0; j < gpio->num_irqs_per_bank; j++) { 653 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) 654 break; 655 } 656 657 if (j == gpio->num_irqs_per_bank) 658 goto skip; 659 660 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); 661 662 for_each_set_bit(pin, &value, port->pins) { 663 int ret = generic_handle_domain_irq(domain, offset + pin); 664 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin); 665 } 666 667 skip: 668 offset += port->pins; 669 } 670 671 chained_irq_exit(chip, desc); 672 } 673 674 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, 675 struct irq_fwspec *fwspec, 676 unsigned long *hwirq, 677 unsigned int *type) 678 { 679 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); 680 unsigned int port, pin, i, offset = 0; 681 682 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) 683 return -EINVAL; 684 685 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) 686 return -EINVAL; 687 688 port = fwspec->param[0] / 8; 689 pin = fwspec->param[0] % 8; 690 691 if (port >= gpio->soc->num_ports) 692 return -EINVAL; 693 694 for (i = 0; i < port; i++) 695 offset += gpio->soc->ports[i].pins; 696 697 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; 698 *hwirq = offset + pin; 699 700 return 0; 701 } 702 703 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, 704 union gpio_irq_fwspec *gfwspec, 705 unsigned int parent_hwirq, 706 unsigned int parent_type) 707 { 708 struct tegra_gpio *gpio = gpiochip_get_data(chip); 709 struct irq_fwspec *fwspec = &gfwspec->fwspec; 710 711 fwspec->fwnode = chip->irq.parent_domain->fwnode; 712 fwspec->param_count = 3; 713 fwspec->param[0] = gpio->soc->instance; 714 fwspec->param[1] = parent_hwirq; 715 fwspec->param[2] = parent_type; 716 717 return 0; 718 } 719 720 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, 721 unsigned int hwirq, 722 unsigned int type, 723 unsigned int *parent_hwirq, 724 unsigned int *parent_type) 725 { 726 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); 727 *parent_type = type; 728 729 return 0; 730 } 731 732 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, 733 unsigned int offset) 734 { 735 struct tegra_gpio *gpio = gpiochip_get_data(chip); 736 unsigned int i; 737 738 for (i = 0; i < gpio->soc->num_ports; i++) { 739 if (offset < gpio->soc->ports[i].pins) 740 break; 741 742 offset -= gpio->soc->ports[i].pins; 743 } 744 745 return offset + i * 8; 746 } 747 748 static const struct of_device_id tegra186_pmc_of_match[] = { 749 { .compatible = "nvidia,tegra186-pmc" }, 750 { .compatible = "nvidia,tegra194-pmc" }, 751 { .compatible = "nvidia,tegra234-pmc" }, 752 { /* sentinel */ } 753 }; 754 755 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) 756 { 757 struct device *dev = gpio->gpio.parent; 758 unsigned int i; 759 u32 value; 760 761 for (i = 0; i < gpio->soc->num_ports; i++) { 762 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 763 unsigned int offset, p = port->port; 764 void __iomem *base; 765 766 base = gpio->secure + port->bank * 0x1000 + 0x800; 767 768 value = readl(base + TEGRA186_GPIO_CTL_SCR); 769 770 /* 771 * For controllers that haven't been locked down yet, make 772 * sure to program the default interrupt route mapping. 773 */ 774 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && 775 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { 776 /* 777 * On Tegra194 and later, each pin can be routed to one or more 778 * interrupts. 779 */ 780 dev_dbg(dev, "programming default interrupt routing for port %s\n", 781 port->name); 782 783 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0); 784 785 /* 786 * By default we only want to route GPIO pins to IRQ 0. This works 787 * only under the assumption that we're running as the host kernel 788 * and hence all GPIO pins are owned by Linux. 789 * 790 * For cases where Linux is the guest OS, the hypervisor will have 791 * to configure the interrupt routing and pass only the valid 792 * interrupts via device tree. 793 */ 794 value = readl(base + offset); 795 value = BIT(port->pins) - 1; 796 writel(value, base + offset); 797 } 798 } 799 } 800 801 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio) 802 { 803 struct device *dev = gpio->gpio.parent; 804 805 if (gpio->num_irq > gpio->num_banks) { 806 if (gpio->num_irq % gpio->num_banks != 0) 807 goto error; 808 } 809 810 if (gpio->num_irq < gpio->num_banks) 811 goto error; 812 813 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; 814 815 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) 816 goto error; 817 818 return 0; 819 820 error: 821 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n", 822 gpio->num_irq, gpio->num_banks); 823 return -EINVAL; 824 } 825 826 static int tegra186_gpio_probe(struct platform_device *pdev) 827 { 828 unsigned int i, j, offset; 829 struct gpio_irq_chip *irq; 830 struct tegra_gpio *gpio; 831 struct device_node *np; 832 struct resource *res; 833 char **names; 834 int err; 835 836 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 837 if (!gpio) 838 return -ENOMEM; 839 840 gpio->soc = device_get_match_data(&pdev->dev); 841 gpio->gpio.label = gpio->soc->name; 842 gpio->gpio.parent = &pdev->dev; 843 844 /* count the number of banks in the controller */ 845 for (i = 0; i < gpio->soc->num_ports; i++) 846 if (gpio->soc->ports[i].bank > gpio->num_banks) 847 gpio->num_banks = gpio->soc->ports[i].bank; 848 849 gpio->num_banks++; 850 851 /* get register apertures */ 852 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security"); 853 if (!res) 854 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 855 gpio->secure = devm_ioremap_resource(&pdev->dev, res); 856 if (IS_ERR(gpio->secure)) 857 return PTR_ERR(gpio->secure); 858 859 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); 860 if (!res) 861 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 862 gpio->base = devm_ioremap_resource(&pdev->dev, res); 863 if (IS_ERR(gpio->base)) 864 return PTR_ERR(gpio->base); 865 866 err = platform_irq_count(pdev); 867 if (err < 0) 868 return err; 869 870 gpio->num_irq = err; 871 872 err = tegra186_gpio_irqs_per_bank(gpio); 873 if (err < 0) 874 return err; 875 876 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), 877 GFP_KERNEL); 878 if (!gpio->irq) 879 return -ENOMEM; 880 881 for (i = 0; i < gpio->num_irq; i++) { 882 err = platform_get_irq(pdev, i); 883 if (err < 0) 884 return err; 885 886 gpio->irq[i] = err; 887 } 888 889 gpio->gpio.request = gpiochip_generic_request; 890 gpio->gpio.free = gpiochip_generic_free; 891 gpio->gpio.get_direction = tegra186_gpio_get_direction; 892 gpio->gpio.direction_input = tegra186_gpio_direction_input; 893 gpio->gpio.direction_output = tegra186_gpio_direction_output; 894 gpio->gpio.get = tegra186_gpio_get; 895 gpio->gpio.set = tegra186_gpio_set; 896 gpio->gpio.set_config = tegra186_gpio_set_config; 897 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; 898 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; 899 if (gpio->soc->has_gte) { 900 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; 901 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; 902 } 903 904 gpio->gpio.base = -1; 905 906 for (i = 0; i < gpio->soc->num_ports; i++) 907 gpio->gpio.ngpio += gpio->soc->ports[i].pins; 908 909 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, 910 sizeof(*names), GFP_KERNEL); 911 if (!names) 912 return -ENOMEM; 913 914 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 915 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 916 char *name; 917 918 for (j = 0; j < port->pins; j++) { 919 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, 920 "P%s.%02x", port->name, j); 921 if (!name) 922 return -ENOMEM; 923 924 names[offset + j] = name; 925 } 926 927 offset += port->pins; 928 } 929 930 gpio->gpio.names = (const char * const *)names; 931 932 #if defined(CONFIG_OF_GPIO) 933 gpio->gpio.of_gpio_n_cells = 2; 934 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; 935 #endif /* CONFIG_OF_GPIO */ 936 937 irq = &gpio->gpio.irq; 938 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip); 939 irq->fwnode = dev_fwnode(&pdev->dev); 940 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; 941 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; 942 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; 943 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; 944 irq->handler = handle_simple_irq; 945 irq->default_type = IRQ_TYPE_NONE; 946 irq->parent_handler = tegra186_gpio_irq; 947 irq->parent_handler_data = gpio; 948 irq->num_parents = gpio->num_irq; 949 950 /* 951 * To simplify things, use a single interrupt per bank for now. Some 952 * chips support up to 8 interrupts per bank, which can be useful to 953 * distribute the load and decrease the processing latency for GPIOs 954 * but it also requires a more complicated interrupt routing than we 955 * currently program. 956 */ 957 if (gpio->num_irqs_per_bank > 1) { 958 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, 959 sizeof(*irq->parents), GFP_KERNEL); 960 if (!irq->parents) 961 return -ENOMEM; 962 963 for (i = 0; i < gpio->num_banks; i++) 964 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; 965 966 irq->num_parents = gpio->num_banks; 967 } else { 968 irq->num_parents = gpio->num_irq; 969 irq->parents = gpio->irq; 970 } 971 972 if (gpio->soc->num_irqs_per_bank > 1) 973 tegra186_gpio_init_route_mapping(gpio); 974 975 np = of_find_matching_node(NULL, tegra186_pmc_of_match); 976 if (np) { 977 if (of_device_is_available(np)) { 978 irq->parent_domain = irq_find_host(np); 979 of_node_put(np); 980 981 if (!irq->parent_domain) 982 return -EPROBE_DEFER; 983 } else { 984 of_node_put(np); 985 } 986 } 987 988 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, 989 sizeof(*irq->map), GFP_KERNEL); 990 if (!irq->map) 991 return -ENOMEM; 992 993 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { 994 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; 995 996 for (j = 0; j < port->pins; j++) 997 irq->map[offset + j] = irq->parents[port->bank]; 998 999 offset += port->pins; 1000 } 1001 1002 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); 1003 } 1004 1005 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1006 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ 1007 .name = #_name, \ 1008 .bank = _bank, \ 1009 .port = _port, \ 1010 .pins = _pins, \ 1011 } 1012 1013 static const struct tegra_gpio_port tegra186_main_ports[] = { 1014 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), 1015 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), 1016 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), 1017 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), 1018 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), 1019 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), 1020 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), 1021 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), 1022 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), 1023 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), 1024 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), 1025 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), 1026 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), 1027 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), 1028 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), 1029 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), 1030 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), 1031 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), 1032 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), 1033 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), 1034 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), 1035 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), 1036 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), 1037 }; 1038 1039 static const struct tegra_gpio_soc tegra186_main_soc = { 1040 .num_ports = ARRAY_SIZE(tegra186_main_ports), 1041 .ports = tegra186_main_ports, 1042 .name = "tegra186-gpio", 1043 .instance = 0, 1044 .num_irqs_per_bank = 1, 1045 .has_vm_support = false, 1046 }; 1047 1048 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1049 [TEGRA186_AON_GPIO_PORT_##_name] = { \ 1050 .name = #_name, \ 1051 .bank = _bank, \ 1052 .port = _port, \ 1053 .pins = _pins, \ 1054 } 1055 1056 static const struct tegra_gpio_port tegra186_aon_ports[] = { 1057 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), 1058 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), 1059 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), 1060 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), 1061 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), 1062 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), 1063 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), 1064 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), 1065 }; 1066 1067 static const struct tegra_gpio_soc tegra186_aon_soc = { 1068 .num_ports = ARRAY_SIZE(tegra186_aon_ports), 1069 .ports = tegra186_aon_ports, 1070 .name = "tegra186-gpio-aon", 1071 .instance = 1, 1072 .num_irqs_per_bank = 1, 1073 .has_vm_support = false, 1074 }; 1075 1076 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1077 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ 1078 .name = #_name, \ 1079 .bank = _bank, \ 1080 .port = _port, \ 1081 .pins = _pins, \ 1082 } 1083 1084 static const struct tegra_gpio_port tegra194_main_ports[] = { 1085 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), 1086 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), 1087 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), 1088 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), 1089 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), 1090 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), 1091 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), 1092 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), 1093 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), 1094 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), 1095 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), 1096 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), 1097 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), 1098 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), 1099 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), 1100 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), 1101 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), 1102 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), 1103 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), 1104 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), 1105 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), 1106 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), 1107 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), 1108 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), 1109 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), 1110 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), 1111 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), 1112 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) 1113 }; 1114 1115 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { 1116 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, 1117 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, 1118 }; 1119 1120 static const struct tegra_gpio_soc tegra194_main_soc = { 1121 .num_ports = ARRAY_SIZE(tegra194_main_ports), 1122 .ports = tegra194_main_ports, 1123 .name = "tegra194-gpio", 1124 .instance = 0, 1125 .num_irqs_per_bank = 8, 1126 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), 1127 .pin_ranges = tegra194_main_pin_ranges, 1128 .pinmux = "nvidia,tegra194-pinmux", 1129 .has_vm_support = true, 1130 }; 1131 1132 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1133 [TEGRA194_AON_GPIO_PORT_##_name] = { \ 1134 .name = #_name, \ 1135 .bank = _bank, \ 1136 .port = _port, \ 1137 .pins = _pins, \ 1138 } 1139 1140 static const struct tegra_gpio_port tegra194_aon_ports[] = { 1141 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), 1142 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), 1143 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), 1144 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), 1145 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) 1146 }; 1147 1148 static const struct tegra_gpio_soc tegra194_aon_soc = { 1149 .num_ports = ARRAY_SIZE(tegra194_aon_ports), 1150 .ports = tegra194_aon_ports, 1151 .name = "tegra194-gpio-aon", 1152 .instance = 1, 1153 .num_irqs_per_bank = 8, 1154 .has_gte = true, 1155 .has_vm_support = false, 1156 }; 1157 1158 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1159 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \ 1160 .name = #_name, \ 1161 .bank = _bank, \ 1162 .port = _port, \ 1163 .pins = _pins, \ 1164 } 1165 1166 static const struct tegra_gpio_port tegra234_main_ports[] = { 1167 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8), 1168 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1), 1169 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8), 1170 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4), 1171 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8), 1172 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6), 1173 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8), 1174 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8), 1175 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7), 1176 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6), 1177 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8), 1178 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4), 1179 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8), 1180 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8), 1181 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8), 1182 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8), 1183 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6), 1184 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8), 1185 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8), 1186 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8), 1187 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8), 1188 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4), 1189 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2), 1190 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4), 1191 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8), 1192 }; 1193 1194 static const struct tegra_gpio_soc tegra234_main_soc = { 1195 .num_ports = ARRAY_SIZE(tegra234_main_ports), 1196 .ports = tegra234_main_ports, 1197 .name = "tegra234-gpio", 1198 .instance = 0, 1199 .num_irqs_per_bank = 8, 1200 .has_vm_support = true, 1201 }; 1202 1203 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1204 [TEGRA234_AON_GPIO_PORT_##_name] = { \ 1205 .name = #_name, \ 1206 .bank = _bank, \ 1207 .port = _port, \ 1208 .pins = _pins, \ 1209 } 1210 1211 static const struct tegra_gpio_port tegra234_aon_ports[] = { 1212 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8), 1213 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4), 1214 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8), 1215 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3), 1216 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8), 1217 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1), 1218 }; 1219 1220 static const struct tegra_gpio_soc tegra234_aon_soc = { 1221 .num_ports = ARRAY_SIZE(tegra234_aon_ports), 1222 .ports = tegra234_aon_ports, 1223 .name = "tegra234-gpio-aon", 1224 .instance = 1, 1225 .num_irqs_per_bank = 8, 1226 .has_gte = true, 1227 .has_vm_support = false, 1228 }; 1229 1230 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1231 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \ 1232 .name = #_name, \ 1233 .bank = _bank, \ 1234 .port = _port, \ 1235 .pins = _pins, \ 1236 } 1237 1238 static const struct tegra_gpio_port tegra241_main_ports[] = { 1239 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8), 1240 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8), 1241 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2), 1242 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6), 1243 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8), 1244 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8), 1245 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8), 1246 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8), 1247 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8), 1248 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4), 1249 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6), 1250 }; 1251 1252 static const struct tegra_gpio_soc tegra241_main_soc = { 1253 .num_ports = ARRAY_SIZE(tegra241_main_ports), 1254 .ports = tegra241_main_ports, 1255 .name = "tegra241-gpio", 1256 .instance = 0, 1257 .num_irqs_per_bank = 8, 1258 .has_vm_support = false, 1259 }; 1260 1261 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \ 1262 [TEGRA241_AON_GPIO_PORT_##_name] = { \ 1263 .name = #_name, \ 1264 .bank = _bank, \ 1265 .port = _port, \ 1266 .pins = _pins, \ 1267 } 1268 1269 static const struct tegra_gpio_port tegra241_aon_ports[] = { 1270 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8), 1271 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4), 1272 }; 1273 1274 static const struct tegra_gpio_soc tegra241_aon_soc = { 1275 .num_ports = ARRAY_SIZE(tegra241_aon_ports), 1276 .ports = tegra241_aon_ports, 1277 .name = "tegra241-gpio-aon", 1278 .instance = 1, 1279 .num_irqs_per_bank = 8, 1280 .has_vm_support = false, 1281 }; 1282 1283 #define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ 1284 [TEGRA256_MAIN_GPIO_PORT_##_name] = { \ 1285 .name = #_name, \ 1286 .bank = _bank, \ 1287 .port = _port, \ 1288 .pins = _pins, \ 1289 } 1290 1291 static const struct tegra_gpio_port tegra256_main_ports[] = { 1292 TEGRA256_MAIN_GPIO_PORT(A, 0, 0, 8), 1293 TEGRA256_MAIN_GPIO_PORT(B, 0, 1, 8), 1294 TEGRA256_MAIN_GPIO_PORT(C, 0, 2, 8), 1295 TEGRA256_MAIN_GPIO_PORT(D, 0, 3, 8), 1296 }; 1297 1298 static const struct tegra_gpio_soc tegra256_main_soc = { 1299 .num_ports = ARRAY_SIZE(tegra256_main_ports), 1300 .ports = tegra256_main_ports, 1301 .name = "tegra256-gpio-main", 1302 .instance = 1, 1303 .num_irqs_per_bank = 8, 1304 .has_vm_support = true, 1305 }; 1306 1307 static const struct of_device_id tegra186_gpio_of_match[] = { 1308 { 1309 .compatible = "nvidia,tegra186-gpio", 1310 .data = &tegra186_main_soc 1311 }, { 1312 .compatible = "nvidia,tegra186-gpio-aon", 1313 .data = &tegra186_aon_soc 1314 }, { 1315 .compatible = "nvidia,tegra194-gpio", 1316 .data = &tegra194_main_soc 1317 }, { 1318 .compatible = "nvidia,tegra194-gpio-aon", 1319 .data = &tegra194_aon_soc 1320 }, { 1321 .compatible = "nvidia,tegra234-gpio", 1322 .data = &tegra234_main_soc 1323 }, { 1324 .compatible = "nvidia,tegra234-gpio-aon", 1325 .data = &tegra234_aon_soc 1326 }, { 1327 .compatible = "nvidia,tegra256-gpio", 1328 .data = &tegra256_main_soc 1329 }, { 1330 /* sentinel */ 1331 } 1332 }; 1333 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); 1334 1335 static const struct acpi_device_id tegra186_gpio_acpi_match[] = { 1336 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc }, 1337 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc }, 1338 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc }, 1339 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, 1340 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, 1341 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, 1342 {} 1343 }; 1344 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); 1345 1346 static struct platform_driver tegra186_gpio_driver = { 1347 .driver = { 1348 .name = "tegra186-gpio", 1349 .of_match_table = tegra186_gpio_of_match, 1350 .acpi_match_table = tegra186_gpio_acpi_match, 1351 }, 1352 .probe = tegra186_gpio_probe, 1353 }; 1354 module_platform_driver(tegra186_gpio_driver); 1355 1356 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); 1357 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1358 MODULE_LICENSE("GPL v2"); 1359