1 /* 2 * arch/arm/mach-tegra/gpio.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Erik Gilling <konkers@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #include <linux/err.h> 21 #include <linux/init.h> 22 #include <linux/irq.h> 23 #include <linux/interrupt.h> 24 #include <linux/io.h> 25 #include <linux/gpio.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/module.h> 29 #include <linux/irqdomain.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pm.h> 32 33 #include <asm/mach/irq.h> 34 35 #define GPIO_BANK(x) ((x) >> 5) 36 #define GPIO_PORT(x) (((x) >> 3) & 0x3) 37 #define GPIO_BIT(x) ((x) & 0x7) 38 39 #define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \ 40 GPIO_PORT(x) * 4) 41 42 #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) 43 #define GPIO_OE(x) (GPIO_REG(x) + 0x10) 44 #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) 45 #define GPIO_IN(x) (GPIO_REG(x) + 0x30) 46 #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) 47 #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) 48 #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) 49 #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) 50 51 #define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00) 52 #define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10) 53 #define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20) 54 #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40) 55 #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50) 56 #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60) 57 58 #define GPIO_INT_LVL_MASK 0x010101 59 #define GPIO_INT_LVL_EDGE_RISING 0x000101 60 #define GPIO_INT_LVL_EDGE_FALLING 0x000100 61 #define GPIO_INT_LVL_EDGE_BOTH 0x010100 62 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 63 #define GPIO_INT_LVL_LEVEL_LOW 0x000000 64 65 struct tegra_gpio_bank { 66 int bank; 67 int irq; 68 spinlock_t lvl_lock[4]; 69 #ifdef CONFIG_PM_SLEEP 70 u32 cnf[4]; 71 u32 out[4]; 72 u32 oe[4]; 73 u32 int_enb[4]; 74 u32 int_lvl[4]; 75 #endif 76 }; 77 78 static struct irq_domain *irq_domain; 79 static void __iomem *regs; 80 static u32 tegra_gpio_bank_count; 81 static u32 tegra_gpio_bank_stride; 82 static u32 tegra_gpio_upper_offset; 83 static struct tegra_gpio_bank *tegra_gpio_banks; 84 85 static inline void tegra_gpio_writel(u32 val, u32 reg) 86 { 87 __raw_writel(val, regs + reg); 88 } 89 90 static inline u32 tegra_gpio_readl(u32 reg) 91 { 92 return __raw_readl(regs + reg); 93 } 94 95 static int tegra_gpio_compose(int bank, int port, int bit) 96 { 97 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); 98 } 99 100 static void tegra_gpio_mask_write(u32 reg, int gpio, int value) 101 { 102 u32 val; 103 104 val = 0x100 << GPIO_BIT(gpio); 105 if (value) 106 val |= 1 << GPIO_BIT(gpio); 107 tegra_gpio_writel(val, reg); 108 } 109 110 static void tegra_gpio_enable(int gpio) 111 { 112 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); 113 } 114 115 static void tegra_gpio_disable(int gpio) 116 { 117 tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); 118 } 119 120 static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) 121 { 122 return pinctrl_request_gpio(offset); 123 } 124 125 static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) 126 { 127 pinctrl_free_gpio(offset); 128 tegra_gpio_disable(offset); 129 } 130 131 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 132 { 133 tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); 134 } 135 136 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) 137 { 138 /* If gpio is in output mode then read from the out value */ 139 if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1) 140 return (tegra_gpio_readl(GPIO_OUT(offset)) >> 141 GPIO_BIT(offset)) & 0x1; 142 143 return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; 144 } 145 146 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 147 { 148 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); 149 tegra_gpio_enable(offset); 150 return 0; 151 } 152 153 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 154 int value) 155 { 156 tegra_gpio_set(chip, offset, value); 157 tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); 158 tegra_gpio_enable(offset); 159 return 0; 160 } 161 162 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 163 { 164 return irq_find_mapping(irq_domain, offset); 165 } 166 167 static struct gpio_chip tegra_gpio_chip = { 168 .label = "tegra-gpio", 169 .request = tegra_gpio_request, 170 .free = tegra_gpio_free, 171 .direction_input = tegra_gpio_direction_input, 172 .get = tegra_gpio_get, 173 .direction_output = tegra_gpio_direction_output, 174 .set = tegra_gpio_set, 175 .to_irq = tegra_gpio_to_irq, 176 .base = 0, 177 }; 178 179 static void tegra_gpio_irq_ack(struct irq_data *d) 180 { 181 int gpio = d->hwirq; 182 183 tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); 184 } 185 186 static void tegra_gpio_irq_mask(struct irq_data *d) 187 { 188 int gpio = d->hwirq; 189 190 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); 191 } 192 193 static void tegra_gpio_irq_unmask(struct irq_data *d) 194 { 195 int gpio = d->hwirq; 196 197 tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); 198 } 199 200 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) 201 { 202 int gpio = d->hwirq; 203 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 204 int port = GPIO_PORT(gpio); 205 int lvl_type; 206 int val; 207 unsigned long flags; 208 209 switch (type & IRQ_TYPE_SENSE_MASK) { 210 case IRQ_TYPE_EDGE_RISING: 211 lvl_type = GPIO_INT_LVL_EDGE_RISING; 212 break; 213 214 case IRQ_TYPE_EDGE_FALLING: 215 lvl_type = GPIO_INT_LVL_EDGE_FALLING; 216 break; 217 218 case IRQ_TYPE_EDGE_BOTH: 219 lvl_type = GPIO_INT_LVL_EDGE_BOTH; 220 break; 221 222 case IRQ_TYPE_LEVEL_HIGH: 223 lvl_type = GPIO_INT_LVL_LEVEL_HIGH; 224 break; 225 226 case IRQ_TYPE_LEVEL_LOW: 227 lvl_type = GPIO_INT_LVL_LEVEL_LOW; 228 break; 229 230 default: 231 return -EINVAL; 232 } 233 234 spin_lock_irqsave(&bank->lvl_lock[port], flags); 235 236 val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 237 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); 238 val |= lvl_type << GPIO_BIT(gpio); 239 tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); 240 241 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 242 243 tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); 244 tegra_gpio_enable(gpio); 245 246 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 247 __irq_set_handler_locked(d->irq, handle_level_irq); 248 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 249 __irq_set_handler_locked(d->irq, handle_edge_irq); 250 251 return 0; 252 } 253 254 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 255 { 256 struct tegra_gpio_bank *bank; 257 int port; 258 int pin; 259 int unmasked = 0; 260 struct irq_chip *chip = irq_desc_get_chip(desc); 261 262 chained_irq_enter(chip, desc); 263 264 bank = irq_get_handler_data(irq); 265 266 for (port = 0; port < 4; port++) { 267 int gpio = tegra_gpio_compose(bank->bank, port, 0); 268 unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & 269 tegra_gpio_readl(GPIO_INT_ENB(gpio)); 270 u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 271 272 for_each_set_bit(pin, &sta, 8) { 273 tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); 274 275 /* if gpio is edge triggered, clear condition 276 * before executing the hander so that we don't 277 * miss edges 278 */ 279 if (lvl & (0x100 << pin)) { 280 unmasked = 1; 281 chained_irq_exit(chip, desc); 282 } 283 284 generic_handle_irq(gpio_to_irq(gpio + pin)); 285 } 286 } 287 288 if (!unmasked) 289 chained_irq_exit(chip, desc); 290 291 } 292 293 #ifdef CONFIG_PM_SLEEP 294 static int tegra_gpio_resume(struct device *dev) 295 { 296 unsigned long flags; 297 int b; 298 int p; 299 300 local_irq_save(flags); 301 302 for (b = 0; b < tegra_gpio_bank_count; b++) { 303 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 304 305 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 306 unsigned int gpio = (b<<5) | (p<<3); 307 tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); 308 tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); 309 tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); 310 tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); 311 tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); 312 } 313 } 314 315 local_irq_restore(flags); 316 return 0; 317 } 318 319 static int tegra_gpio_suspend(struct device *dev) 320 { 321 unsigned long flags; 322 int b; 323 int p; 324 325 local_irq_save(flags); 326 for (b = 0; b < tegra_gpio_bank_count; b++) { 327 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; 328 329 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { 330 unsigned int gpio = (b<<5) | (p<<3); 331 bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); 332 bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); 333 bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); 334 bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); 335 bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); 336 } 337 } 338 local_irq_restore(flags); 339 return 0; 340 } 341 342 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) 343 { 344 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); 345 return irq_set_irq_wake(bank->irq, enable); 346 } 347 #endif 348 349 static struct irq_chip tegra_gpio_irq_chip = { 350 .name = "GPIO", 351 .irq_ack = tegra_gpio_irq_ack, 352 .irq_mask = tegra_gpio_irq_mask, 353 .irq_unmask = tegra_gpio_irq_unmask, 354 .irq_set_type = tegra_gpio_irq_set_type, 355 #ifdef CONFIG_PM_SLEEP 356 .irq_set_wake = tegra_gpio_wake_enable, 357 #endif 358 }; 359 360 static const struct dev_pm_ops tegra_gpio_pm_ops = { 361 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) 362 }; 363 364 struct tegra_gpio_soc_config { 365 u32 bank_stride; 366 u32 upper_offset; 367 }; 368 369 static struct tegra_gpio_soc_config tegra20_gpio_config = { 370 .bank_stride = 0x80, 371 .upper_offset = 0x800, 372 }; 373 374 static struct tegra_gpio_soc_config tegra30_gpio_config = { 375 .bank_stride = 0x100, 376 .upper_offset = 0x80, 377 }; 378 379 static struct of_device_id tegra_gpio_of_match[] = { 380 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, 381 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, 382 { }, 383 }; 384 385 /* This lock class tells lockdep that GPIO irqs are in a different 386 * category than their parents, so it won't report false recursion. 387 */ 388 static struct lock_class_key gpio_lock_class; 389 390 static int tegra_gpio_probe(struct platform_device *pdev) 391 { 392 const struct of_device_id *match; 393 struct tegra_gpio_soc_config *config; 394 struct resource *res; 395 struct tegra_gpio_bank *bank; 396 int gpio; 397 int i; 398 int j; 399 400 match = of_match_device(tegra_gpio_of_match, &pdev->dev); 401 if (match) 402 config = (struct tegra_gpio_soc_config *)match->data; 403 else 404 config = &tegra20_gpio_config; 405 406 tegra_gpio_bank_stride = config->bank_stride; 407 tegra_gpio_upper_offset = config->upper_offset; 408 409 for (;;) { 410 res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); 411 if (!res) 412 break; 413 tegra_gpio_bank_count++; 414 } 415 if (!tegra_gpio_bank_count) { 416 dev_err(&pdev->dev, "Missing IRQ resource\n"); 417 return -ENODEV; 418 } 419 420 tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; 421 422 tegra_gpio_banks = devm_kzalloc(&pdev->dev, 423 tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), 424 GFP_KERNEL); 425 if (!tegra_gpio_banks) { 426 dev_err(&pdev->dev, "Couldn't allocate bank structure\n"); 427 return -ENODEV; 428 } 429 430 irq_domain = irq_domain_add_linear(pdev->dev.of_node, 431 tegra_gpio_chip.ngpio, 432 &irq_domain_simple_ops, NULL); 433 if (!irq_domain) 434 return -ENODEV; 435 436 for (i = 0; i < tegra_gpio_bank_count; i++) { 437 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 438 if (!res) { 439 dev_err(&pdev->dev, "Missing IRQ resource\n"); 440 return -ENODEV; 441 } 442 443 bank = &tegra_gpio_banks[i]; 444 bank->bank = i; 445 bank->irq = res->start; 446 } 447 448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 449 if (!res) { 450 dev_err(&pdev->dev, "Missing MEM resource\n"); 451 return -ENODEV; 452 } 453 454 regs = devm_ioremap_resource(&pdev->dev, res); 455 if (IS_ERR(regs)) 456 return PTR_ERR(regs); 457 458 for (i = 0; i < tegra_gpio_bank_count; i++) { 459 for (j = 0; j < 4; j++) { 460 int gpio = tegra_gpio_compose(i, j, 0); 461 tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); 462 } 463 } 464 465 #ifdef CONFIG_OF_GPIO 466 tegra_gpio_chip.of_node = pdev->dev.of_node; 467 #endif 468 469 gpiochip_add(&tegra_gpio_chip); 470 471 for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { 472 int irq = irq_create_mapping(irq_domain, gpio); 473 /* No validity check; all Tegra GPIOs are valid IRQs */ 474 475 bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; 476 477 irq_set_lockdep_class(irq, &gpio_lock_class); 478 irq_set_chip_data(irq, bank); 479 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, 480 handle_simple_irq); 481 set_irq_flags(irq, IRQF_VALID); 482 } 483 484 for (i = 0; i < tegra_gpio_bank_count; i++) { 485 bank = &tegra_gpio_banks[i]; 486 487 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); 488 irq_set_handler_data(bank->irq, bank); 489 490 for (j = 0; j < 4; j++) 491 spin_lock_init(&bank->lvl_lock[j]); 492 } 493 494 return 0; 495 } 496 497 static struct platform_driver tegra_gpio_driver = { 498 .driver = { 499 .name = "tegra-gpio", 500 .owner = THIS_MODULE, 501 .pm = &tegra_gpio_pm_ops, 502 .of_match_table = tegra_gpio_of_match, 503 }, 504 .probe = tegra_gpio_probe, 505 }; 506 507 static int __init tegra_gpio_init(void) 508 { 509 return platform_driver_register(&tegra_gpio_driver); 510 } 511 postcore_initcall(tegra_gpio_init); 512 513 #ifdef CONFIG_DEBUG_FS 514 515 #include <linux/debugfs.h> 516 #include <linux/seq_file.h> 517 518 static int dbg_gpio_show(struct seq_file *s, void *unused) 519 { 520 int i; 521 int j; 522 523 for (i = 0; i < tegra_gpio_bank_count; i++) { 524 for (j = 0; j < 4; j++) { 525 int gpio = tegra_gpio_compose(i, j, 0); 526 seq_printf(s, 527 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", 528 i, j, 529 tegra_gpio_readl(GPIO_CNF(gpio)), 530 tegra_gpio_readl(GPIO_OE(gpio)), 531 tegra_gpio_readl(GPIO_OUT(gpio)), 532 tegra_gpio_readl(GPIO_IN(gpio)), 533 tegra_gpio_readl(GPIO_INT_STA(gpio)), 534 tegra_gpio_readl(GPIO_INT_ENB(gpio)), 535 tegra_gpio_readl(GPIO_INT_LVL(gpio))); 536 } 537 } 538 return 0; 539 } 540 541 static int dbg_gpio_open(struct inode *inode, struct file *file) 542 { 543 return single_open(file, dbg_gpio_show, &inode->i_private); 544 } 545 546 static const struct file_operations debug_fops = { 547 .open = dbg_gpio_open, 548 .read = seq_read, 549 .llseek = seq_lseek, 550 .release = single_release, 551 }; 552 553 static int __init tegra_gpio_debuginit(void) 554 { 555 (void) debugfs_create_file("tegra_gpio", S_IRUGO, 556 NULL, NULL, &debug_fops); 557 return 0; 558 } 559 late_initcall(tegra_gpio_debuginit); 560 #endif 561