1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SYSCON GPIO driver 4 * 5 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 6 */ 7 8 #include <linux/err.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/mfd/syscon.h> 15 16 #define GPIO_SYSCON_FEAT_IN BIT(0) 17 #define GPIO_SYSCON_FEAT_OUT BIT(1) 18 #define GPIO_SYSCON_FEAT_DIR BIT(2) 19 20 /* SYSCON driver is designed to use 32-bit wide registers */ 21 #define SYSCON_REG_SIZE (4) 22 #define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) 23 24 /** 25 * struct syscon_gpio_data - Configuration for the device. 26 * @flags: Set of GPIO_SYSCON_FEAT_ flags: 27 * GPIO_SYSCON_FEAT_IN: GPIOs supports input, 28 * GPIO_SYSCON_FEAT_OUT: GPIOs supports output, 29 * GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. 30 * @bit_count: Number of bits used as GPIOs. 31 * @dat_bit_offset: Offset (in bits) to the first GPIO bit. 32 * @dir_bit_offset: Optional offset (in bits) to the first bit to switch 33 * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). 34 * @set: HW specific callback to assigns output value 35 * for signal "offset" 36 */ 37 38 struct syscon_gpio_data { 39 unsigned int flags; 40 unsigned int bit_count; 41 unsigned int dat_bit_offset; 42 unsigned int dir_bit_offset; 43 int (*set)(struct gpio_chip *chip, unsigned int offset, 44 int value); 45 }; 46 47 struct syscon_gpio_priv { 48 struct gpio_chip chip; 49 struct regmap *syscon; 50 const struct syscon_gpio_data *data; 51 u32 dreg_offset; 52 u32 dir_reg_offset; 53 }; 54 55 static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) 56 { 57 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 58 unsigned int val, offs; 59 int ret; 60 61 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 62 63 ret = regmap_read(priv->syscon, 64 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); 65 if (ret) 66 return ret; 67 68 return !!(val & BIT(offs % SYSCON_REG_BITS)); 69 } 70 71 static int syscon_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 72 { 73 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 74 unsigned int offs; 75 76 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 77 78 return regmap_update_bits(priv->syscon, 79 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 80 BIT(offs % SYSCON_REG_BITS), 81 val ? BIT(offs % SYSCON_REG_BITS) : 0); 82 } 83 84 static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) 85 { 86 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 87 88 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 89 unsigned int offs; 90 91 offs = priv->dir_reg_offset + 92 priv->data->dir_bit_offset + offset; 93 94 regmap_update_bits(priv->syscon, 95 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 96 BIT(offs % SYSCON_REG_BITS), 0); 97 } 98 99 return 0; 100 } 101 102 static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) 103 { 104 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 105 106 if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { 107 unsigned int offs; 108 109 offs = priv->dir_reg_offset + 110 priv->data->dir_bit_offset + offset; 111 112 regmap_update_bits(priv->syscon, 113 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 114 BIT(offs % SYSCON_REG_BITS), 115 BIT(offs % SYSCON_REG_BITS)); 116 } 117 118 return chip->set(chip, offset, val); 119 } 120 121 static const struct syscon_gpio_data clps711x_mctrl_gpio = { 122 /* ARM CLPS711X SYSFLG1 Bits 8-10 */ 123 .flags = GPIO_SYSCON_FEAT_IN, 124 .bit_count = 3, 125 .dat_bit_offset = 0x40 * 8 + 8, 126 }; 127 128 static int rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset, 129 int val) 130 { 131 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 132 unsigned int offs; 133 u8 bit; 134 u32 data; 135 int ret; 136 137 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 138 bit = offs % SYSCON_REG_BITS; 139 data = (val ? BIT(bit) : 0) | BIT(bit + 16); 140 ret = regmap_write(priv->syscon, 141 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 142 data); 143 if (ret < 0) 144 dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 145 146 return ret; 147 } 148 149 static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = { 150 /* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */ 151 .flags = GPIO_SYSCON_FEAT_OUT, 152 .bit_count = 1, 153 .dat_bit_offset = 0x0428 * 8 + 1, 154 .set = rockchip_gpio_set, 155 }; 156 157 #define KEYSTONE_LOCK_BIT BIT(0) 158 159 static int keystone_gpio_set(struct gpio_chip *chip, unsigned int offset, 160 int val) 161 { 162 struct syscon_gpio_priv *priv = gpiochip_get_data(chip); 163 unsigned int offs; 164 int ret; 165 166 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; 167 168 if (!val) 169 return 0; 170 171 ret = regmap_update_bits( 172 priv->syscon, 173 (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, 174 BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, 175 BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); 176 if (ret < 0) 177 dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); 178 179 return ret; 180 } 181 182 static const struct syscon_gpio_data keystone_dsp_gpio = { 183 /* ARM Keystone 2 */ 184 .flags = GPIO_SYSCON_FEAT_OUT, 185 .bit_count = 28, 186 .dat_bit_offset = 4, 187 .set = keystone_gpio_set, 188 }; 189 190 static const struct of_device_id syscon_gpio_ids[] = { 191 { 192 .compatible = "cirrus,ep7209-mctrl-gpio", 193 .data = &clps711x_mctrl_gpio, 194 }, 195 { 196 .compatible = "ti,keystone-dsp-gpio", 197 .data = &keystone_dsp_gpio, 198 }, 199 { 200 .compatible = "rockchip,rk3328-grf-gpio", 201 .data = &rockchip_rk3328_gpio_mute, 202 }, 203 { } 204 }; 205 MODULE_DEVICE_TABLE(of, syscon_gpio_ids); 206 207 static int syscon_gpio_probe(struct platform_device *pdev) 208 { 209 struct device *dev = &pdev->dev; 210 struct syscon_gpio_priv *priv; 211 struct device_node *np = dev->of_node; 212 int ret; 213 bool use_parent_regmap = false; 214 215 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 216 if (!priv) 217 return -ENOMEM; 218 219 priv->data = of_device_get_match_data(dev); 220 221 priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); 222 if (IS_ERR(priv->syscon) && np->parent) { 223 priv->syscon = syscon_node_to_regmap(np->parent); 224 use_parent_regmap = true; 225 } 226 if (IS_ERR(priv->syscon)) 227 return PTR_ERR(priv->syscon); 228 229 if (!use_parent_regmap) { 230 ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, 231 &priv->dreg_offset); 232 if (ret) 233 dev_err(dev, "can't read the data register offset!\n"); 234 235 priv->dreg_offset <<= 3; 236 237 ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, 238 &priv->dir_reg_offset); 239 if (ret) 240 dev_dbg(dev, "can't read the dir register offset!\n"); 241 242 priv->dir_reg_offset <<= 3; 243 } 244 245 priv->chip.parent = dev; 246 priv->chip.owner = THIS_MODULE; 247 priv->chip.label = dev_name(dev); 248 priv->chip.base = -1; 249 priv->chip.ngpio = priv->data->bit_count; 250 priv->chip.get = syscon_gpio_get; 251 if (priv->data->flags & GPIO_SYSCON_FEAT_IN) 252 priv->chip.direction_input = syscon_gpio_dir_in; 253 if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { 254 priv->chip.set = priv->data->set ? : syscon_gpio_set; 255 priv->chip.direction_output = syscon_gpio_dir_out; 256 } 257 258 return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); 259 } 260 261 static struct platform_driver syscon_gpio_driver = { 262 .driver = { 263 .name = "gpio-syscon", 264 .of_match_table = syscon_gpio_ids, 265 }, 266 .probe = syscon_gpio_probe, 267 }; 268 module_platform_driver(syscon_gpio_driver); 269 270 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 271 MODULE_DESCRIPTION("SYSCON GPIO driver"); 272 MODULE_LICENSE("GPL"); 273