1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License, version 2 5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6 */ 7 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <linux/gpio.h> 13 #include <linux/interrupt.h> 14 #include <linux/of.h> 15 #include <linux/mfd/stmpe.h> 16 #include <linux/seq_file.h> 17 18 /* 19 * These registers are modified under the irq bus lock and cached to avoid 20 * unnecessary writes in bus_sync_unlock. 21 */ 22 enum { REG_RE, REG_FE, REG_IE }; 23 24 #define CACHE_NR_REGS 3 25 /* No variant has more than 24 GPIOs */ 26 #define CACHE_NR_BANKS (24 / 8) 27 28 struct stmpe_gpio { 29 struct gpio_chip chip; 30 struct stmpe *stmpe; 31 struct device *dev; 32 struct mutex irq_lock; 33 u32 norequest_mask; 34 /* Caches of interrupt control registers for bus_lock */ 35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 36 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 37 }; 38 39 static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip) 40 { 41 return container_of(chip, struct stmpe_gpio, chip); 42 } 43 44 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 45 { 46 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 47 struct stmpe *stmpe = stmpe_gpio->stmpe; 48 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8); 49 u8 mask = 1 << (offset % 8); 50 int ret; 51 52 ret = stmpe_reg_read(stmpe, reg); 53 if (ret < 0) 54 return ret; 55 56 return !!(ret & mask); 57 } 58 59 static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 60 { 61 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 62 struct stmpe *stmpe = stmpe_gpio->stmpe; 63 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 64 u8 reg = stmpe->regs[which] - (offset / 8); 65 u8 mask = 1 << (offset % 8); 66 67 /* 68 * Some variants have single register for gpio set/clear functionality. 69 * For them we need to write 0 to clear and 1 to set. 70 */ 71 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 72 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 73 else 74 stmpe_reg_write(stmpe, reg, mask); 75 } 76 77 static int stmpe_gpio_direction_output(struct gpio_chip *chip, 78 unsigned offset, int val) 79 { 80 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 81 struct stmpe *stmpe = stmpe_gpio->stmpe; 82 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 83 u8 mask = 1 << (offset % 8); 84 85 stmpe_gpio_set(chip, offset, val); 86 87 return stmpe_set_bits(stmpe, reg, mask, mask); 88 } 89 90 static int stmpe_gpio_direction_input(struct gpio_chip *chip, 91 unsigned offset) 92 { 93 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 94 struct stmpe *stmpe = stmpe_gpio->stmpe; 95 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 96 u8 mask = 1 << (offset % 8); 97 98 return stmpe_set_bits(stmpe, reg, mask, 0); 99 } 100 101 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 102 { 103 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip); 104 struct stmpe *stmpe = stmpe_gpio->stmpe; 105 106 if (stmpe_gpio->norequest_mask & (1 << offset)) 107 return -EINVAL; 108 109 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO); 110 } 111 112 static struct gpio_chip template_chip = { 113 .label = "stmpe", 114 .owner = THIS_MODULE, 115 .direction_input = stmpe_gpio_direction_input, 116 .get = stmpe_gpio_get, 117 .direction_output = stmpe_gpio_direction_output, 118 .set = stmpe_gpio_set, 119 .request = stmpe_gpio_request, 120 .can_sleep = true, 121 }; 122 123 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 124 { 125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 126 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 127 int offset = d->hwirq; 128 int regoffset = offset / 8; 129 int mask = 1 << (offset % 8); 130 131 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) 132 return -EINVAL; 133 134 /* STMPE801 doesn't have RE and FE registers */ 135 if (stmpe_gpio->stmpe->partnum == STMPE801) 136 return 0; 137 138 if (type & IRQ_TYPE_EDGE_RISING) 139 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 140 else 141 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 142 143 if (type & IRQ_TYPE_EDGE_FALLING) 144 stmpe_gpio->regs[REG_FE][regoffset] |= mask; 145 else 146 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 147 148 return 0; 149 } 150 151 static void stmpe_gpio_irq_lock(struct irq_data *d) 152 { 153 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 154 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 155 156 mutex_lock(&stmpe_gpio->irq_lock); 157 } 158 159 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 160 { 161 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 162 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 163 struct stmpe *stmpe = stmpe_gpio->stmpe; 164 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 165 static const u8 regmap[] = { 166 [REG_RE] = STMPE_IDX_GPRER_LSB, 167 [REG_FE] = STMPE_IDX_GPFER_LSB, 168 [REG_IE] = STMPE_IDX_IEGPIOR_LSB, 169 }; 170 int i, j; 171 172 for (i = 0; i < CACHE_NR_REGS; i++) { 173 /* STMPE801 doesn't have RE and FE registers */ 174 if ((stmpe->partnum == STMPE801) && 175 (i != REG_IE)) 176 continue; 177 178 for (j = 0; j < num_banks; j++) { 179 u8 old = stmpe_gpio->oldregs[i][j]; 180 u8 new = stmpe_gpio->regs[i][j]; 181 182 if (new == old) 183 continue; 184 185 stmpe_gpio->oldregs[i][j] = new; 186 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new); 187 } 188 } 189 190 mutex_unlock(&stmpe_gpio->irq_lock); 191 } 192 193 static void stmpe_gpio_irq_mask(struct irq_data *d) 194 { 195 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 196 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 197 int offset = d->hwirq; 198 int regoffset = offset / 8; 199 int mask = 1 << (offset % 8); 200 201 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 202 } 203 204 static void stmpe_gpio_irq_unmask(struct irq_data *d) 205 { 206 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 207 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 208 int offset = d->hwirq; 209 int regoffset = offset / 8; 210 int mask = 1 << (offset % 8); 211 212 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 213 } 214 215 static void stmpe_dbg_show_one(struct seq_file *s, 216 struct gpio_chip *gc, 217 unsigned offset, unsigned gpio) 218 { 219 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc); 220 struct stmpe *stmpe = stmpe_gpio->stmpe; 221 const char *label = gpiochip_is_requested(gc, offset); 222 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 223 bool val = !!stmpe_gpio_get(gc, offset); 224 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 225 u8 mask = 1 << (offset % 8); 226 int ret; 227 u8 dir; 228 229 ret = stmpe_reg_read(stmpe, dir_reg); 230 if (ret < 0) 231 return; 232 dir = !!(ret & mask); 233 234 if (dir) { 235 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 236 gpio, label ?: "(none)", 237 val ? "hi" : "lo"); 238 } else { 239 u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8); 240 u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8); 241 u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8); 242 u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8); 243 bool edge_det; 244 bool rise; 245 bool fall; 246 bool irqen; 247 248 ret = stmpe_reg_read(stmpe, edge_det_reg); 249 if (ret < 0) 250 return; 251 edge_det = !!(ret & mask); 252 ret = stmpe_reg_read(stmpe, rise_reg); 253 if (ret < 0) 254 return; 255 rise = !!(ret & mask); 256 ret = stmpe_reg_read(stmpe, fall_reg); 257 if (ret < 0) 258 return; 259 fall = !!(ret & mask); 260 ret = stmpe_reg_read(stmpe, irqen_reg); 261 if (ret < 0) 262 return; 263 irqen = !!(ret & mask); 264 265 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s", 266 gpio, label ?: "(none)", 267 val ? "hi" : "lo", 268 edge_det ? "edge-asserted" : "edge-inactive", 269 irqen ? "IRQ-enabled" : "", 270 rise ? " rising-edge-detection" : "", 271 fall ? " falling-edge-detection" : ""); 272 } 273 } 274 275 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) 276 { 277 unsigned i; 278 unsigned gpio = gc->base; 279 280 for (i = 0; i < gc->ngpio; i++, gpio++) { 281 stmpe_dbg_show_one(s, gc, i, gpio); 282 seq_printf(s, "\n"); 283 } 284 } 285 286 static struct irq_chip stmpe_gpio_irq_chip = { 287 .name = "stmpe-gpio", 288 .irq_bus_lock = stmpe_gpio_irq_lock, 289 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 290 .irq_mask = stmpe_gpio_irq_mask, 291 .irq_unmask = stmpe_gpio_irq_unmask, 292 .irq_set_type = stmpe_gpio_irq_set_type, 293 }; 294 295 static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 296 { 297 struct stmpe_gpio *stmpe_gpio = dev; 298 struct stmpe *stmpe = stmpe_gpio->stmpe; 299 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 300 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 301 u8 status[num_banks]; 302 int ret; 303 int i; 304 305 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 306 if (ret < 0) 307 return IRQ_NONE; 308 309 for (i = 0; i < num_banks; i++) { 310 int bank = num_banks - i - 1; 311 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 312 unsigned int stat = status[i]; 313 314 stat &= enabled; 315 if (!stat) 316 continue; 317 318 while (stat) { 319 int bit = __ffs(stat); 320 int line = bank * 8 + bit; 321 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain, 322 line); 323 324 handle_nested_irq(child_irq); 325 stat &= ~(1 << bit); 326 } 327 328 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 329 330 /* Edge detect register is not present on 801 */ 331 if (stmpe->partnum != STMPE801) 332 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] 333 + i, status[i]); 334 } 335 336 return IRQ_HANDLED; 337 } 338 339 static int stmpe_gpio_probe(struct platform_device *pdev) 340 { 341 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); 342 struct device_node *np = pdev->dev.of_node; 343 struct stmpe_gpio *stmpe_gpio; 344 int ret; 345 int irq = 0; 346 347 irq = platform_get_irq(pdev, 0); 348 349 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL); 350 if (!stmpe_gpio) 351 return -ENOMEM; 352 353 mutex_init(&stmpe_gpio->irq_lock); 354 355 stmpe_gpio->dev = &pdev->dev; 356 stmpe_gpio->stmpe = stmpe; 357 stmpe_gpio->chip = template_chip; 358 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 359 stmpe_gpio->chip.dev = &pdev->dev; 360 stmpe_gpio->chip.of_node = np; 361 stmpe_gpio->chip.base = -1; 362 363 if (IS_ENABLED(CONFIG_DEBUG_FS)) 364 stmpe_gpio->chip.dbg_show = stmpe_dbg_show; 365 366 of_property_read_u32(np, "st,norequest-mask", 367 &stmpe_gpio->norequest_mask); 368 369 if (irq < 0) 370 dev_info(&pdev->dev, 371 "device configured in no-irq mode: " 372 "irqs are not available\n"); 373 374 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 375 if (ret) 376 goto out_free; 377 378 ret = gpiochip_add(&stmpe_gpio->chip); 379 if (ret) { 380 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); 381 goto out_disable; 382 } 383 384 if (irq > 0) { 385 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 386 stmpe_gpio_irq, IRQF_ONESHOT, 387 "stmpe-gpio", stmpe_gpio); 388 if (ret) { 389 dev_err(&pdev->dev, "unable to get irq: %d\n", ret); 390 goto out_disable; 391 } 392 ret = gpiochip_irqchip_add(&stmpe_gpio->chip, 393 &stmpe_gpio_irq_chip, 394 0, 395 handle_simple_irq, 396 IRQ_TYPE_NONE); 397 if (ret) { 398 dev_err(&pdev->dev, 399 "could not connect irqchip to gpiochip\n"); 400 goto out_disable; 401 } 402 403 gpiochip_set_chained_irqchip(&stmpe_gpio->chip, 404 &stmpe_gpio_irq_chip, 405 irq, 406 NULL); 407 } 408 409 platform_set_drvdata(pdev, stmpe_gpio); 410 411 return 0; 412 413 out_disable: 414 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 415 gpiochip_remove(&stmpe_gpio->chip); 416 out_free: 417 kfree(stmpe_gpio); 418 return ret; 419 } 420 421 static int stmpe_gpio_remove(struct platform_device *pdev) 422 { 423 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev); 424 struct stmpe *stmpe = stmpe_gpio->stmpe; 425 426 gpiochip_remove(&stmpe_gpio->chip); 427 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 428 kfree(stmpe_gpio); 429 430 return 0; 431 } 432 433 static struct platform_driver stmpe_gpio_driver = { 434 .driver.name = "stmpe-gpio", 435 .driver.owner = THIS_MODULE, 436 .probe = stmpe_gpio_probe, 437 .remove = stmpe_gpio_remove, 438 }; 439 440 static int __init stmpe_gpio_init(void) 441 { 442 return platform_driver_register(&stmpe_gpio_driver); 443 } 444 subsys_initcall(stmpe_gpio_init); 445 446 static void __exit stmpe_gpio_exit(void) 447 { 448 platform_driver_unregister(&stmpe_gpio_driver); 449 } 450 module_exit(stmpe_gpio_exit); 451 452 MODULE_LICENSE("GPL v2"); 453 MODULE_DESCRIPTION("STMPExxxx GPIO driver"); 454 MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>"); 455