1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/cleanup.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/stmpe.h> 14 #include <linux/property.h> 15 #include <linux/platform_device.h> 16 #include <linux/seq_file.h> 17 #include <linux/slab.h> 18 #include <linux/string_choices.h> 19 20 /* 21 * These registers are modified under the irq bus lock and cached to avoid 22 * unnecessary writes in bus_sync_unlock. 23 */ 24 enum { REG_RE, REG_FE, REG_IE }; 25 26 enum { LSB, CSB, MSB }; 27 28 #define CACHE_NR_REGS 3 29 /* No variant has more than 24 GPIOs */ 30 #define CACHE_NR_BANKS (24 / 8) 31 32 struct stmpe_gpio { 33 struct gpio_chip chip; 34 struct stmpe *stmpe; 35 struct mutex irq_lock; 36 u32 norequest_mask; 37 /* Caches of interrupt control registers for bus_lock */ 38 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; 39 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; 40 }; 41 42 static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) 43 { 44 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 45 struct stmpe *stmpe = stmpe_gpio->stmpe; 46 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; 47 u8 mask = BIT(offset % 8); 48 int ret; 49 50 ret = stmpe_reg_read(stmpe, reg); 51 if (ret < 0) 52 return ret; 53 54 return !!(ret & mask); 55 } 56 57 static int stmpe_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) 58 { 59 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 60 struct stmpe *stmpe = stmpe_gpio->stmpe; 61 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; 62 u8 reg = stmpe->regs[which + (offset / 8)]; 63 u8 mask = BIT(offset % 8); 64 65 /* 66 * Some variants have single register for gpio set/clear functionality. 67 * For them we need to write 0 to clear and 1 to set. 68 */ 69 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) 70 return stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); 71 72 return stmpe_reg_write(stmpe, reg, mask); 73 } 74 75 static int stmpe_gpio_get_direction(struct gpio_chip *chip, 76 unsigned offset) 77 { 78 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 79 struct stmpe *stmpe = stmpe_gpio->stmpe; 80 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); 81 u8 mask = BIT(offset % 8); 82 int ret; 83 84 ret = stmpe_reg_read(stmpe, reg); 85 if (ret < 0) 86 return ret; 87 88 if (ret & mask) 89 return GPIO_LINE_DIRECTION_OUT; 90 91 return GPIO_LINE_DIRECTION_IN; 92 } 93 94 static int stmpe_gpio_direction_output(struct gpio_chip *chip, 95 unsigned offset, int val) 96 { 97 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 98 struct stmpe *stmpe = stmpe_gpio->stmpe; 99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 100 u8 mask = BIT(offset % 8); 101 int ret; 102 103 ret = stmpe_gpio_set(chip, offset, val); 104 if (ret) 105 return ret; 106 107 return stmpe_set_bits(stmpe, reg, mask, mask); 108 } 109 110 static int stmpe_gpio_direction_input(struct gpio_chip *chip, 111 unsigned offset) 112 { 113 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 114 struct stmpe *stmpe = stmpe_gpio->stmpe; 115 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; 116 u8 mask = BIT(offset % 8); 117 118 return stmpe_set_bits(stmpe, reg, mask, 0); 119 } 120 121 static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) 122 { 123 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); 124 struct stmpe *stmpe = stmpe_gpio->stmpe; 125 126 if (stmpe_gpio->norequest_mask & BIT(offset)) 127 return -EINVAL; 128 129 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); 130 } 131 132 static const struct gpio_chip template_chip = { 133 .label = "stmpe", 134 .owner = THIS_MODULE, 135 .get_direction = stmpe_gpio_get_direction, 136 .direction_input = stmpe_gpio_direction_input, 137 .get = stmpe_gpio_get, 138 .direction_output = stmpe_gpio_direction_output, 139 .set = stmpe_gpio_set, 140 .request = stmpe_gpio_request, 141 .can_sleep = true, 142 }; 143 144 static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) 145 { 146 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 147 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 148 int offset = d->hwirq; 149 int regoffset = offset / 8; 150 int mask = BIT(offset % 8); 151 152 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) 153 return -EINVAL; 154 155 /* STMPE801 and STMPE 1600 don't have RE and FE registers */ 156 if (stmpe_gpio->stmpe->partnum == STMPE801 || 157 stmpe_gpio->stmpe->partnum == STMPE1600) 158 return 0; 159 160 if (type & IRQ_TYPE_EDGE_RISING) 161 stmpe_gpio->regs[REG_RE][regoffset] |= mask; 162 else 163 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; 164 165 if (type & IRQ_TYPE_EDGE_FALLING) 166 stmpe_gpio->regs[REG_FE][regoffset] |= mask; 167 else 168 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; 169 170 return 0; 171 } 172 173 static void stmpe_gpio_irq_lock(struct irq_data *d) 174 { 175 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 176 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 177 178 mutex_lock(&stmpe_gpio->irq_lock); 179 } 180 181 static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) 182 { 183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 184 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 185 struct stmpe *stmpe = stmpe_gpio->stmpe; 186 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 187 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { 188 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB, 189 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB, 190 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB, 191 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB, 192 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB, 193 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB, 194 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, 195 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, 196 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, 197 }; 198 int ret, i, j; 199 200 /* 201 * STMPE1600: to be able to get IRQ from pins, 202 * a read must be done on GPMR register, or a write in 203 * GPSR or GPCR registers 204 */ 205 if (stmpe->partnum == STMPE1600) { 206 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); 207 if (ret < 0) { 208 dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret); 209 goto err; 210 } 211 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); 212 if (ret < 0) { 213 dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret); 214 goto err; 215 } 216 } 217 218 for (i = 0; i < CACHE_NR_REGS; i++) { 219 /* STMPE801 and STMPE1600 don't have RE and FE registers */ 220 if ((stmpe->partnum == STMPE801 || 221 stmpe->partnum == STMPE1600) && 222 (i != REG_IE)) 223 continue; 224 225 for (j = 0; j < num_banks; j++) { 226 u8 old = stmpe_gpio->oldregs[i][j]; 227 u8 new = stmpe_gpio->regs[i][j]; 228 229 if (new == old) 230 continue; 231 232 stmpe_gpio->oldregs[i][j] = new; 233 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); 234 } 235 } 236 237 err: 238 mutex_unlock(&stmpe_gpio->irq_lock); 239 } 240 241 static void stmpe_gpio_irq_mask(struct irq_data *d) 242 { 243 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 244 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 245 int offset = d->hwirq; 246 int regoffset = offset / 8; 247 int mask = BIT(offset % 8); 248 249 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; 250 gpiochip_disable_irq(gc, offset); 251 } 252 253 static void stmpe_gpio_irq_unmask(struct irq_data *d) 254 { 255 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 256 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 257 int offset = d->hwirq; 258 int regoffset = offset / 8; 259 int mask = BIT(offset % 8); 260 261 gpiochip_enable_irq(gc, offset); 262 stmpe_gpio->regs[REG_IE][regoffset] |= mask; 263 } 264 265 static void stmpe_dbg_show_one(struct seq_file *s, 266 struct gpio_chip *gc, 267 unsigned offset, unsigned gpio) 268 { 269 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 270 struct stmpe *stmpe = stmpe_gpio->stmpe; 271 bool val = !!stmpe_gpio_get(gc, offset); 272 u8 bank = offset / 8; 273 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; 274 u8 mask = BIT(offset % 8); 275 int ret; 276 u8 dir; 277 278 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset); 279 if (IS_ERR(label)) 280 return; 281 282 ret = stmpe_reg_read(stmpe, dir_reg); 283 if (ret < 0) 284 return; 285 dir = !!(ret & mask); 286 287 if (dir) { 288 seq_printf(s, " gpio-%-3d (%-20.20s) out %s", 289 gpio, label ?: "(none)", str_hi_lo(val)); 290 } else { 291 u8 edge_det_reg; 292 u8 rise_reg; 293 u8 fall_reg; 294 u8 irqen_reg; 295 296 static const char * const edge_det_values[] = { 297 "edge-inactive", 298 "edge-asserted", 299 "not-supported" 300 }; 301 static const char * const rise_values[] = { 302 "no-rising-edge-detection", 303 "rising-edge-detection", 304 "not-supported" 305 }; 306 static const char * const fall_values[] = { 307 "no-falling-edge-detection", 308 "falling-edge-detection", 309 "not-supported" 310 }; 311 #define NOT_SUPPORTED_IDX 2 312 u8 edge_det = NOT_SUPPORTED_IDX; 313 u8 rise = NOT_SUPPORTED_IDX; 314 u8 fall = NOT_SUPPORTED_IDX; 315 bool irqen; 316 317 switch (stmpe->partnum) { 318 case STMPE610: 319 case STMPE811: 320 case STMPE1601: 321 case STMPE2401: 322 case STMPE2403: 323 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; 324 ret = stmpe_reg_read(stmpe, edge_det_reg); 325 if (ret < 0) 326 return; 327 edge_det = !!(ret & mask); 328 fallthrough; 329 case STMPE1801: 330 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; 331 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; 332 333 ret = stmpe_reg_read(stmpe, rise_reg); 334 if (ret < 0) 335 return; 336 rise = !!(ret & mask); 337 ret = stmpe_reg_read(stmpe, fall_reg); 338 if (ret < 0) 339 return; 340 fall = !!(ret & mask); 341 fallthrough; 342 case STMPE801: 343 case STMPE1600: 344 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; 345 break; 346 347 default: 348 return; 349 } 350 351 ret = stmpe_reg_read(stmpe, irqen_reg); 352 if (ret < 0) 353 return; 354 irqen = !!(ret & mask); 355 356 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", 357 gpio, label ?: "(none)", 358 str_hi_lo(val), 359 edge_det_values[edge_det], 360 irqen ? "IRQ-enabled" : "IRQ-disabled", 361 rise_values[rise], 362 fall_values[fall]); 363 } 364 } 365 366 static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) 367 { 368 unsigned i; 369 unsigned gpio = gc->base; 370 371 for (i = 0; i < gc->ngpio; i++, gpio++) { 372 stmpe_dbg_show_one(s, gc, i, gpio); 373 seq_putc(s, '\n'); 374 } 375 } 376 377 static const struct irq_chip stmpe_gpio_irq_chip = { 378 .name = "stmpe-gpio", 379 .irq_bus_lock = stmpe_gpio_irq_lock, 380 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, 381 .irq_mask = stmpe_gpio_irq_mask, 382 .irq_unmask = stmpe_gpio_irq_unmask, 383 .irq_set_type = stmpe_gpio_irq_set_type, 384 .flags = IRQCHIP_IMMUTABLE, 385 GPIOCHIP_IRQ_RESOURCE_HELPERS, 386 }; 387 388 #define MAX_GPIOS 24 389 390 static irqreturn_t stmpe_gpio_irq(int irq, void *dev) 391 { 392 struct stmpe_gpio *stmpe_gpio = dev; 393 struct stmpe *stmpe = stmpe_gpio->stmpe; 394 u8 statmsbreg; 395 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); 396 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)]; 397 int ret; 398 int i; 399 400 /* 401 * the stmpe_block_read() call below, imposes to set statmsbreg 402 * with the register located at the lowest address. As STMPE1600 403 * variant is the only one which respect registers address's order 404 * (LSB regs located at lowest address than MSB ones) whereas all 405 * the others have a registers layout with MSB located before the 406 * LSB regs. 407 */ 408 if (stmpe->partnum == STMPE1600) 409 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; 410 else 411 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; 412 413 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); 414 if (ret < 0) 415 return IRQ_NONE; 416 417 for (i = 0; i < num_banks; i++) { 418 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : 419 num_banks - i - 1; 420 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; 421 unsigned int stat = status[i]; 422 423 stat &= enabled; 424 if (!stat) 425 continue; 426 427 while (stat) { 428 int bit = __ffs(stat); 429 int line = bank * 8 + bit; 430 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, 431 line); 432 433 handle_nested_irq(child_irq); 434 stat &= ~BIT(bit); 435 } 436 437 /* 438 * interrupt status register write has no effect on 439 * 801/1801/1600, bits are cleared when read. 440 * Edge detect register is not present on 801/1600/1801 441 */ 442 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && 443 stmpe->partnum != STMPE1801) { 444 stmpe_reg_write(stmpe, statmsbreg + i, status[i]); 445 stmpe_reg_write(stmpe, 446 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, 447 status[i]); 448 } 449 } 450 451 return IRQ_HANDLED; 452 } 453 454 static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, 455 unsigned long *valid_mask, 456 unsigned int ngpios) 457 { 458 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); 459 int i; 460 461 if (!stmpe_gpio->norequest_mask) 462 return; 463 464 /* Forbid unused lines to be mapped as IRQs */ 465 for (i = 0; i < sizeof(u32); i++) { 466 if (stmpe_gpio->norequest_mask & BIT(i)) 467 clear_bit(i, valid_mask); 468 } 469 } 470 471 static void stmpe_gpio_disable(void *stmpe) 472 { 473 stmpe_disable(stmpe, STMPE_BLOCK_GPIO); 474 } 475 476 static int stmpe_gpio_probe(struct platform_device *pdev) 477 { 478 struct device *dev = &pdev->dev; 479 struct stmpe *stmpe = dev_get_drvdata(dev->parent); 480 struct stmpe_gpio *stmpe_gpio; 481 int ret, irq; 482 483 if (stmpe->num_gpios > MAX_GPIOS) { 484 dev_err(dev, "Need to increase maximum GPIO number\n"); 485 return -EINVAL; 486 } 487 488 stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL); 489 if (!stmpe_gpio) 490 return -ENOMEM; 491 492 mutex_init(&stmpe_gpio->irq_lock); 493 494 stmpe_gpio->stmpe = stmpe; 495 stmpe_gpio->chip = template_chip; 496 stmpe_gpio->chip.ngpio = stmpe->num_gpios; 497 stmpe_gpio->chip.parent = dev; 498 stmpe_gpio->chip.base = -1; 499 500 if (IS_ENABLED(CONFIG_DEBUG_FS)) 501 stmpe_gpio->chip.dbg_show = stmpe_dbg_show; 502 503 device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask); 504 505 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); 506 if (ret) 507 return ret; 508 509 ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe); 510 if (ret) 511 return ret; 512 513 irq = platform_get_irq(pdev, 0); 514 if (irq > 0) { 515 struct gpio_irq_chip *girq; 516 517 ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq, 518 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio); 519 if (ret) 520 return dev_err_probe(dev, ret, "unable to register IRQ handler\n"); 521 522 girq = &stmpe_gpio->chip.irq; 523 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip); 524 /* This will let us handle the parent IRQ in the driver */ 525 girq->parent_handler = NULL; 526 girq->num_parents = 0; 527 girq->parents = NULL; 528 girq->default_type = IRQ_TYPE_NONE; 529 girq->handler = handle_simple_irq; 530 girq->threaded = true; 531 girq->init_valid_mask = stmpe_init_irq_valid_mask; 532 } 533 534 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio); 535 } 536 537 static struct platform_driver stmpe_gpio_driver = { 538 .driver = { 539 .suppress_bind_attrs = true, 540 .name = "stmpe-gpio", 541 }, 542 .probe = stmpe_gpio_probe, 543 }; 544 545 static int __init stmpe_gpio_init(void) 546 { 547 return platform_driver_register(&stmpe_gpio_driver); 548 } 549 subsys_initcall(stmpe_gpio_init); 550