1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * GPIO interface for Intel Poulsbo SCH 4 * 5 * Copyright (c) 2010 CompuLab Ltd 6 * Author: Denis Turischev <denis@compulab.co.il> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/io.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/pci_ids.h> 16 #include <linux/platform_device.h> 17 18 #define GEN 0x00 19 #define GIO 0x04 20 #define GLV 0x08 21 22 struct sch_gpio { 23 struct gpio_chip chip; 24 spinlock_t lock; 25 unsigned short iobase; 26 unsigned short resume_base; 27 }; 28 29 static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio, 30 unsigned int reg) 31 { 32 unsigned int base = 0; 33 34 if (gpio >= sch->resume_base) { 35 gpio -= sch->resume_base; 36 base += 0x20; 37 } 38 39 return base + reg + gpio / 8; 40 } 41 42 static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio) 43 { 44 if (gpio >= sch->resume_base) 45 gpio -= sch->resume_base; 46 return gpio % 8; 47 } 48 49 static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg) 50 { 51 unsigned short offset, bit; 52 u8 reg_val; 53 54 offset = sch_gpio_offset(sch, gpio, reg); 55 bit = sch_gpio_bit(sch, gpio); 56 57 reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); 58 59 return reg_val; 60 } 61 62 static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg, 63 int val) 64 { 65 unsigned short offset, bit; 66 u8 reg_val; 67 68 offset = sch_gpio_offset(sch, gpio, reg); 69 bit = sch_gpio_bit(sch, gpio); 70 71 reg_val = inb(sch->iobase + offset); 72 73 if (val) 74 outb(reg_val | BIT(bit), sch->iobase + offset); 75 else 76 outb((reg_val & ~BIT(bit)), sch->iobase + offset); 77 } 78 79 static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num) 80 { 81 struct sch_gpio *sch = gpiochip_get_data(gc); 82 83 spin_lock(&sch->lock); 84 sch_gpio_reg_set(sch, gpio_num, GIO, 1); 85 spin_unlock(&sch->lock); 86 return 0; 87 } 88 89 static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num) 90 { 91 struct sch_gpio *sch = gpiochip_get_data(gc); 92 93 return sch_gpio_reg_get(sch, gpio_num, GLV); 94 } 95 96 static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val) 97 { 98 struct sch_gpio *sch = gpiochip_get_data(gc); 99 100 spin_lock(&sch->lock); 101 sch_gpio_reg_set(sch, gpio_num, GLV, val); 102 spin_unlock(&sch->lock); 103 } 104 105 static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num, 106 int val) 107 { 108 struct sch_gpio *sch = gpiochip_get_data(gc); 109 110 spin_lock(&sch->lock); 111 sch_gpio_reg_set(sch, gpio_num, GIO, 0); 112 spin_unlock(&sch->lock); 113 114 /* 115 * according to the datasheet, writing to the level register has no 116 * effect when GPIO is programmed as input. 117 * Actually the the level register is read-only when configured as input. 118 * Thus presetting the output level before switching to output is _NOT_ possible. 119 * Hence we set the level after configuring the GPIO as output. 120 * But we cannot prevent a short low pulse if direction is set to high 121 * and an external pull-up is connected. 122 */ 123 sch_gpio_set(gc, gpio_num, val); 124 return 0; 125 } 126 127 static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num) 128 { 129 struct sch_gpio *sch = gpiochip_get_data(gc); 130 131 if (sch_gpio_reg_get(sch, gpio_num, GIO)) 132 return GPIO_LINE_DIRECTION_IN; 133 134 return GPIO_LINE_DIRECTION_OUT; 135 } 136 137 static const struct gpio_chip sch_gpio_chip = { 138 .label = "sch_gpio", 139 .owner = THIS_MODULE, 140 .direction_input = sch_gpio_direction_in, 141 .get = sch_gpio_get, 142 .direction_output = sch_gpio_direction_out, 143 .set = sch_gpio_set, 144 .get_direction = sch_gpio_get_direction, 145 }; 146 147 static int sch_gpio_probe(struct platform_device *pdev) 148 { 149 struct sch_gpio *sch; 150 struct resource *res; 151 152 sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL); 153 if (!sch) 154 return -ENOMEM; 155 156 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 157 if (!res) 158 return -EBUSY; 159 160 if (!devm_request_region(&pdev->dev, res->start, resource_size(res), 161 pdev->name)) 162 return -EBUSY; 163 164 spin_lock_init(&sch->lock); 165 sch->iobase = res->start; 166 sch->chip = sch_gpio_chip; 167 sch->chip.label = dev_name(&pdev->dev); 168 sch->chip.parent = &pdev->dev; 169 170 switch (pdev->id) { 171 case PCI_DEVICE_ID_INTEL_SCH_LPC: 172 sch->resume_base = 10; 173 sch->chip.ngpio = 14; 174 175 /* 176 * GPIO[6:0] enabled by default 177 * GPIO7 is configured by the CMC as SLPIOVR 178 * Enable GPIO[9:8] core powered gpios explicitly 179 */ 180 sch_gpio_reg_set(sch, 8, GEN, 1); 181 sch_gpio_reg_set(sch, 9, GEN, 1); 182 /* 183 * SUS_GPIO[2:0] enabled by default 184 * Enable SUS_GPIO3 resume powered gpio explicitly 185 */ 186 sch_gpio_reg_set(sch, 13, GEN, 1); 187 break; 188 189 case PCI_DEVICE_ID_INTEL_ITC_LPC: 190 sch->resume_base = 5; 191 sch->chip.ngpio = 14; 192 break; 193 194 case PCI_DEVICE_ID_INTEL_CENTERTON_ILB: 195 sch->resume_base = 21; 196 sch->chip.ngpio = 30; 197 break; 198 199 case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB: 200 sch->resume_base = 2; 201 sch->chip.ngpio = 8; 202 break; 203 204 default: 205 return -ENODEV; 206 } 207 208 platform_set_drvdata(pdev, sch); 209 210 return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch); 211 } 212 213 static struct platform_driver sch_gpio_driver = { 214 .driver = { 215 .name = "sch_gpio", 216 }, 217 .probe = sch_gpio_probe, 218 }; 219 220 module_platform_driver(sch_gpio_driver); 221 222 MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>"); 223 MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH"); 224 MODULE_LICENSE("GPL v2"); 225 MODULE_ALIAS("platform:sch_gpio"); 226