1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-sa1100/gpio.c 4 * 5 * Generic SA-1100 GPIO handling 6 */ 7 #include <linux/gpio/driver.h> 8 #include <linux/init.h> 9 #include <linux/module.h> 10 #include <linux/io.h> 11 #include <linux/syscore_ops.h> 12 #include <soc/sa1100/pwer.h> 13 #include <mach/hardware.h> 14 #include <mach/irqs.h> 15 #include <mach/generic.h> 16 #include <linux/property.h> 17 18 const struct software_node sa1100_gpiochip_node = { 19 .name = "sa1100-gpio", 20 }; 21 22 struct sa1100_gpio_chip { 23 struct gpio_chip chip; 24 void __iomem *membase; 25 int irqbase; 26 u32 irqmask; 27 u32 irqrising; 28 u32 irqfalling; 29 u32 irqwake; 30 }; 31 32 #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip) 33 34 enum { 35 R_GPLR = 0x00, 36 R_GPDR = 0x04, 37 R_GPSR = 0x08, 38 R_GPCR = 0x0c, 39 R_GRER = 0x10, 40 R_GFER = 0x14, 41 R_GEDR = 0x18, 42 R_GAFR = 0x1c, 43 }; 44 45 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) 46 { 47 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & 48 BIT(offset); 49 } 50 51 static int sa1100_gpio_set(struct gpio_chip *chip, unsigned int offset, 52 int value) 53 { 54 int reg = value ? R_GPSR : R_GPCR; 55 56 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); 57 58 return 0; 59 } 60 61 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset) 62 { 63 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 64 65 if (readl_relaxed(gpdr) & BIT(offset)) 66 return GPIO_LINE_DIRECTION_OUT; 67 68 return GPIO_LINE_DIRECTION_IN; 69 } 70 71 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset) 72 { 73 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 74 unsigned long flags; 75 76 local_irq_save(flags); 77 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr); 78 local_irq_restore(flags); 79 80 return 0; 81 } 82 83 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value) 84 { 85 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; 86 unsigned long flags; 87 88 local_irq_save(flags); 89 sa1100_gpio_set(chip, offset, value); 90 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr); 91 local_irq_restore(flags); 92 93 return 0; 94 } 95 96 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset) 97 { 98 return sa1100_gpio_chip(chip)->irqbase + offset; 99 } 100 101 static struct sa1100_gpio_chip sa1100_gpio_chip = { 102 .chip = { 103 .label = "gpio", 104 .get_direction = sa1100_get_direction, 105 .direction_input = sa1100_direction_input, 106 .direction_output = sa1100_direction_output, 107 .set = sa1100_gpio_set, 108 .get = sa1100_gpio_get, 109 .to_irq = sa1100_to_irq, 110 .base = 0, 111 .ngpio = GPIO_MAX + 1, 112 }, 113 .membase = (void *)&GPLR, 114 .irqbase = IRQ_GPIO0, 115 }; 116 117 /* 118 * SA1100 GPIO edge detection for IRQs: 119 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 120 * Use this instead of directly setting GRER/GFER. 121 */ 122 static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc) 123 { 124 void *base = sgc->membase; 125 u32 grer, gfer; 126 127 grer = sgc->irqrising & sgc->irqmask; 128 gfer = sgc->irqfalling & sgc->irqmask; 129 130 writel_relaxed(grer, base + R_GRER); 131 writel_relaxed(gfer, base + R_GFER); 132 } 133 134 static int sa1100_gpio_type(struct irq_data *d, unsigned int type) 135 { 136 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 137 unsigned int mask = BIT(d->hwirq); 138 139 if (type == IRQ_TYPE_PROBE) { 140 if ((sgc->irqrising | sgc->irqfalling) & mask) 141 return 0; 142 type = IRQ_TYPE_EDGE_BOTH; 143 } 144 145 if (type & IRQ_TYPE_EDGE_RISING) 146 sgc->irqrising |= mask; 147 else 148 sgc->irqrising &= ~mask; 149 if (type & IRQ_TYPE_EDGE_FALLING) 150 sgc->irqfalling |= mask; 151 else 152 sgc->irqfalling &= ~mask; 153 154 sa1100_update_edge_regs(sgc); 155 156 return 0; 157 } 158 159 /* 160 * GPIO IRQs must be acknowledged. 161 */ 162 static void sa1100_gpio_ack(struct irq_data *d) 163 { 164 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 165 166 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); 167 } 168 169 static void sa1100_gpio_mask(struct irq_data *d) 170 { 171 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 172 unsigned int mask = BIT(d->hwirq); 173 174 sgc->irqmask &= ~mask; 175 176 sa1100_update_edge_regs(sgc); 177 } 178 179 static void sa1100_gpio_unmask(struct irq_data *d) 180 { 181 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 182 unsigned int mask = BIT(d->hwirq); 183 184 sgc->irqmask |= mask; 185 186 sa1100_update_edge_regs(sgc); 187 } 188 189 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on) 190 { 191 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d); 192 int ret = sa11x0_gpio_set_wake(d->hwirq, on); 193 if (!ret) { 194 if (on) 195 sgc->irqwake |= BIT(d->hwirq); 196 else 197 sgc->irqwake &= ~BIT(d->hwirq); 198 } 199 return ret; 200 } 201 202 /* 203 * This is for GPIO IRQs 204 */ 205 static struct irq_chip sa1100_gpio_irq_chip = { 206 .name = "GPIO", 207 .irq_ack = sa1100_gpio_ack, 208 .irq_mask = sa1100_gpio_mask, 209 .irq_unmask = sa1100_gpio_unmask, 210 .irq_set_type = sa1100_gpio_type, 211 .irq_set_wake = sa1100_gpio_wake, 212 }; 213 214 static int sa1100_gpio_irqdomain_map(struct irq_domain *d, 215 unsigned int irq, irq_hw_number_t hwirq) 216 { 217 struct sa1100_gpio_chip *sgc = d->host_data; 218 219 irq_set_chip_data(irq, sgc); 220 irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq); 221 irq_set_probe(irq); 222 223 return 0; 224 } 225 226 static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = { 227 .map = sa1100_gpio_irqdomain_map, 228 .xlate = irq_domain_xlate_onetwocell, 229 }; 230 231 static struct irq_domain *sa1100_gpio_irqdomain; 232 233 /* 234 * IRQ 0-11 (GPIO) handler. We enter here with the 235 * irq_controller_lock held, and IRQs disabled. Decode the IRQ 236 * and call the handler. 237 */ 238 static void sa1100_gpio_handler(struct irq_desc *desc) 239 { 240 struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc); 241 unsigned int irq, mask; 242 void __iomem *gedr = sgc->membase + R_GEDR; 243 244 mask = readl_relaxed(gedr); 245 do { 246 /* 247 * clear down all currently active IRQ sources. 248 * We will be processing them all. 249 */ 250 writel_relaxed(mask, gedr); 251 252 irq = sgc->irqbase; 253 do { 254 if (mask & 1) 255 generic_handle_irq(irq); 256 mask >>= 1; 257 irq++; 258 } while (mask); 259 260 mask = readl_relaxed(gedr); 261 } while (mask); 262 } 263 264 static int sa1100_gpio_suspend(void *data) 265 { 266 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; 267 268 /* 269 * Set the appropriate edges for wakeup. 270 */ 271 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER); 272 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER); 273 274 /* 275 * Clear any pending GPIO interrupts. 276 */ 277 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR), 278 sgc->membase + R_GEDR); 279 280 return 0; 281 } 282 283 static void sa1100_gpio_resume(void *data) 284 { 285 sa1100_update_edge_regs(&sa1100_gpio_chip); 286 } 287 288 static const struct syscore_ops sa1100_gpio_syscore_ops = { 289 .suspend = sa1100_gpio_suspend, 290 .resume = sa1100_gpio_resume, 291 }; 292 293 static struct syscore sa1100_gpio_syscore = { 294 .ops = &sa1100_gpio_syscore_ops, 295 }; 296 297 static int __init sa1100_gpio_init_devicefs(void) 298 { 299 register_syscore(&sa1100_gpio_syscore); 300 return 0; 301 } 302 303 device_initcall(sa1100_gpio_init_devicefs); 304 305 static const int sa1100_gpio_irqs[] __initconst = { 306 /* Install handlers for GPIO 0-10 edge detect interrupts */ 307 IRQ_GPIO0_SC, 308 IRQ_GPIO1_SC, 309 IRQ_GPIO2_SC, 310 IRQ_GPIO3_SC, 311 IRQ_GPIO4_SC, 312 IRQ_GPIO5_SC, 313 IRQ_GPIO6_SC, 314 IRQ_GPIO7_SC, 315 IRQ_GPIO8_SC, 316 IRQ_GPIO9_SC, 317 IRQ_GPIO10_SC, 318 /* Install handler for GPIO 11-27 edge detect interrupts */ 319 IRQ_GPIO11_27, 320 }; 321 322 void __init sa1100_init_gpio(void) 323 { 324 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip; 325 struct gpio_chip *gc = &sgc->chip; 326 int i; 327 328 /* clear all GPIO edge detects */ 329 writel_relaxed(0, sgc->membase + R_GFER); 330 writel_relaxed(0, sgc->membase + R_GRER); 331 writel_relaxed(-1, sgc->membase + R_GEDR); 332 333 software_node_register(&sa1100_gpiochip_node); 334 gc->fwnode = software_node_fwnode(&sa1100_gpiochip_node); 335 gpiochip_add_data(gc, NULL); 336 337 sa1100_gpio_irqdomain = irq_domain_create_simple(NULL, 338 28, IRQ_GPIO0, 339 &sa1100_gpio_irqdomain_ops, sgc); 340 341 for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++) 342 irq_set_chained_handler_and_data(sa1100_gpio_irqs[i], 343 sa1100_gpio_handler, sgc); 344 } 345