1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include "../pinctrl/core.h" 27 #include "../pinctrl/pinctrl-rockchip.h" 28 29 /* 30 * Version ID Register 31 * Bits [31:24] - Major Version 32 * Bits [23:16] - Minor Version 33 * Bits [15:0] - Revision Number 34 */ 35 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 36 #define GPIO_TYPE_V2 (0x01000C2B) 37 #define GPIO_TYPE_V2_1 (0x0101157C) 38 #define GPIO_TYPE_V2_2 (0x010219C8) 39 40 static const struct rockchip_gpio_regs gpio_regs_v1 = { 41 .port_dr = 0x00, 42 .port_ddr = 0x04, 43 .int_en = 0x30, 44 .int_mask = 0x34, 45 .int_type = 0x38, 46 .int_polarity = 0x3c, 47 .int_status = 0x40, 48 .int_rawstatus = 0x44, 49 .debounce = 0x48, 50 .port_eoi = 0x4c, 51 .ext_port = 0x50, 52 }; 53 54 static const struct rockchip_gpio_regs gpio_regs_v2 = { 55 .port_dr = 0x00, 56 .port_ddr = 0x08, 57 .int_en = 0x10, 58 .int_mask = 0x18, 59 .int_type = 0x20, 60 .int_polarity = 0x28, 61 .int_bothedge = 0x30, 62 .int_status = 0x50, 63 .int_rawstatus = 0x58, 64 .debounce = 0x38, 65 .dbclk_div_en = 0x40, 66 .dbclk_div_con = 0x48, 67 .port_eoi = 0x60, 68 .ext_port = 0x70, 69 .version_id = 0x78, 70 }; 71 72 static inline void gpio_writel_v2(u32 val, void __iomem *reg) 73 { 74 writel((val & 0xffff) | 0xffff0000, reg); 75 writel((val >> 16) | 0xffff0000, reg + 0x4); 76 } 77 78 static inline u32 gpio_readl_v2(void __iomem *reg) 79 { 80 return readl(reg + 0x4) << 16 | readl(reg); 81 } 82 83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, 84 u32 value, unsigned int offset) 85 { 86 void __iomem *reg = bank->reg_base + offset; 87 88 if (bank->gpio_type == GPIO_TYPE_V2) 89 gpio_writel_v2(value, reg); 90 else 91 writel(value, reg); 92 } 93 94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, 95 unsigned int offset) 96 { 97 void __iomem *reg = bank->reg_base + offset; 98 u32 value; 99 100 if (bank->gpio_type == GPIO_TYPE_V2) 101 value = gpio_readl_v2(reg); 102 else 103 value = readl(reg); 104 105 return value; 106 } 107 108 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, 109 u32 bit, u32 value, 110 unsigned int offset) 111 { 112 void __iomem *reg = bank->reg_base + offset; 113 u32 data; 114 115 if (bank->gpio_type == GPIO_TYPE_V2) { 116 if (value) 117 data = BIT(bit % 16) | BIT(bit % 16 + 16); 118 else 119 data = BIT(bit % 16 + 16); 120 writel(data, bit >= 16 ? reg + 0x4 : reg); 121 } else { 122 data = readl(reg); 123 data &= ~BIT(bit); 124 if (value) 125 data |= BIT(bit); 126 writel(data, reg); 127 } 128 } 129 130 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, 131 u32 bit, unsigned int offset) 132 { 133 void __iomem *reg = bank->reg_base + offset; 134 u32 data; 135 136 if (bank->gpio_type == GPIO_TYPE_V2) { 137 data = readl(bit >= 16 ? reg + 0x4 : reg); 138 data >>= bit % 16; 139 } else { 140 data = readl(reg); 141 data >>= bit; 142 } 143 144 return data & (0x1); 145 } 146 147 static int rockchip_gpio_get_direction(struct gpio_chip *chip, 148 unsigned int offset) 149 { 150 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 151 u32 data; 152 153 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); 154 if (data) 155 return GPIO_LINE_DIRECTION_OUT; 156 157 return GPIO_LINE_DIRECTION_IN; 158 } 159 160 static int rockchip_gpio_set_direction(struct gpio_chip *chip, 161 unsigned int offset, bool input) 162 { 163 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 164 unsigned long flags; 165 u32 data = input ? 0 : 1; 166 167 168 if (input) 169 pinctrl_gpio_direction_input(chip, offset); 170 else 171 pinctrl_gpio_direction_output(chip, offset); 172 173 raw_spin_lock_irqsave(&bank->slock, flags); 174 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); 175 raw_spin_unlock_irqrestore(&bank->slock, flags); 176 177 return 0; 178 } 179 180 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, 181 int value) 182 { 183 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 184 unsigned long flags; 185 186 raw_spin_lock_irqsave(&bank->slock, flags); 187 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); 188 raw_spin_unlock_irqrestore(&bank->slock, flags); 189 } 190 191 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) 192 { 193 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 194 u32 data; 195 196 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 197 data >>= offset; 198 data &= 1; 199 200 return data; 201 } 202 203 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, 204 unsigned int offset, 205 unsigned int debounce) 206 { 207 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 208 const struct rockchip_gpio_regs *reg = bank->gpio_regs; 209 unsigned long flags, div_reg, freq, max_debounce; 210 bool div_debounce_support; 211 unsigned int cur_div_reg; 212 u64 div; 213 214 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { 215 div_debounce_support = true; 216 freq = clk_get_rate(bank->db_clk); 217 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; 218 if (debounce > max_debounce) 219 return -EINVAL; 220 221 div = debounce * freq; 222 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; 223 } else { 224 div_debounce_support = false; 225 } 226 227 raw_spin_lock_irqsave(&bank->slock, flags); 228 229 /* Only the v1 needs to configure div_en and div_con for dbclk */ 230 if (debounce) { 231 if (div_debounce_support) { 232 /* Configure the max debounce from consumers */ 233 cur_div_reg = readl(bank->reg_base + 234 reg->dbclk_div_con); 235 if (cur_div_reg < div_reg) 236 writel(div_reg, bank->reg_base + 237 reg->dbclk_div_con); 238 rockchip_gpio_writel_bit(bank, offset, 1, 239 reg->dbclk_div_en); 240 } 241 242 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); 243 } else { 244 if (div_debounce_support) 245 rockchip_gpio_writel_bit(bank, offset, 0, 246 reg->dbclk_div_en); 247 248 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); 249 } 250 251 raw_spin_unlock_irqrestore(&bank->slock, flags); 252 253 /* Enable or disable dbclk at last */ 254 if (div_debounce_support) { 255 if (debounce) 256 clk_prepare_enable(bank->db_clk); 257 else 258 clk_disable_unprepare(bank->db_clk); 259 } 260 261 return 0; 262 } 263 264 static int rockchip_gpio_direction_input(struct gpio_chip *gc, 265 unsigned int offset) 266 { 267 return rockchip_gpio_set_direction(gc, offset, true); 268 } 269 270 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 271 unsigned int offset, int value) 272 { 273 rockchip_gpio_set(gc, offset, value); 274 275 return rockchip_gpio_set_direction(gc, offset, false); 276 } 277 278 /* 279 * gpiolib set_config callback function. The setting of the pin 280 * mux function as 'gpio output' will be handled by the pinctrl subsystem 281 * interface. 282 */ 283 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 284 unsigned long config) 285 { 286 enum pin_config_param param = pinconf_to_config_param(config); 287 288 switch (param) { 289 case PIN_CONFIG_INPUT_DEBOUNCE: 290 rockchip_gpio_set_debounce(gc, offset, true); 291 /* 292 * Rockchip's gpio could only support up to one period 293 * of the debounce clock(pclk), which is far away from 294 * satisftying the requirement, as pclk is usually near 295 * 100MHz shared by all peripherals. So the fact is it 296 * has crippled debounce capability could only be useful 297 * to prevent any spurious glitches from waking up the system 298 * if the gpio is conguired as wakeup interrupt source. Let's 299 * still return -ENOTSUPP as before, to make sure the caller 300 * of gpiod_set_debounce won't change its behaviour. 301 */ 302 return -ENOTSUPP; 303 default: 304 return -ENOTSUPP; 305 } 306 } 307 308 /* 309 * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin 310 * and a virtual IRQ, if not already present. 311 */ 312 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 313 { 314 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 315 unsigned int virq; 316 317 if (!bank->domain) 318 return -ENXIO; 319 320 virq = irq_create_mapping(bank->domain, offset); 321 322 return (virq) ? : -ENXIO; 323 } 324 325 static const struct gpio_chip rockchip_gpiolib_chip = { 326 .request = gpiochip_generic_request, 327 .free = gpiochip_generic_free, 328 .set = rockchip_gpio_set, 329 .get = rockchip_gpio_get, 330 .get_direction = rockchip_gpio_get_direction, 331 .direction_input = rockchip_gpio_direction_input, 332 .direction_output = rockchip_gpio_direction_output, 333 .set_config = rockchip_gpio_set_config, 334 .to_irq = rockchip_gpio_to_irq, 335 .owner = THIS_MODULE, 336 }; 337 338 static void rockchip_irq_demux(struct irq_desc *desc) 339 { 340 struct irq_chip *chip = irq_desc_get_chip(desc); 341 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 342 unsigned long pending; 343 unsigned int irq; 344 345 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); 346 347 chained_irq_enter(chip, desc); 348 349 pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); 350 for_each_set_bit(irq, &pending, 32) { 351 dev_dbg(bank->dev, "handling irq %d\n", irq); 352 353 /* 354 * Triggering IRQ on both rising and falling edge 355 * needs manual intervention. 356 */ 357 if (bank->toggle_edge_mode & BIT(irq)) { 358 u32 data, data_old, polarity; 359 unsigned long flags; 360 361 data = readl_relaxed(bank->reg_base + 362 bank->gpio_regs->ext_port); 363 do { 364 raw_spin_lock_irqsave(&bank->slock, flags); 365 366 polarity = readl_relaxed(bank->reg_base + 367 bank->gpio_regs->int_polarity); 368 if (data & BIT(irq)) 369 polarity &= ~BIT(irq); 370 else 371 polarity |= BIT(irq); 372 writel(polarity, 373 bank->reg_base + 374 bank->gpio_regs->int_polarity); 375 376 raw_spin_unlock_irqrestore(&bank->slock, flags); 377 378 data_old = data; 379 data = readl_relaxed(bank->reg_base + 380 bank->gpio_regs->ext_port); 381 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 382 } 383 384 generic_handle_domain_irq(bank->domain, irq); 385 } 386 387 chained_irq_exit(chip, desc); 388 } 389 390 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 391 { 392 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 393 struct rockchip_pin_bank *bank = gc->private; 394 u32 mask = BIT(d->hwirq); 395 u32 polarity; 396 u32 level; 397 u32 data; 398 unsigned long flags; 399 int ret = 0; 400 401 raw_spin_lock_irqsave(&bank->slock, flags); 402 403 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 404 bank->gpio_regs->port_ddr); 405 406 raw_spin_unlock_irqrestore(&bank->slock, flags); 407 408 if (type & IRQ_TYPE_EDGE_BOTH) 409 irq_set_handler_locked(d, handle_edge_irq); 410 else 411 irq_set_handler_locked(d, handle_level_irq); 412 413 raw_spin_lock_irqsave(&bank->slock, flags); 414 415 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); 416 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); 417 418 if (type == IRQ_TYPE_EDGE_BOTH) { 419 if (bank->gpio_type == GPIO_TYPE_V2) { 420 rockchip_gpio_writel_bit(bank, d->hwirq, 1, 421 bank->gpio_regs->int_bothedge); 422 goto out; 423 } else { 424 bank->toggle_edge_mode |= mask; 425 level &= ~mask; 426 427 /* 428 * Determine gpio state. If 1 next interrupt should be 429 * low otherwise high. 430 */ 431 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 432 if (data & mask) 433 polarity &= ~mask; 434 else 435 polarity |= mask; 436 } 437 } else { 438 if (bank->gpio_type == GPIO_TYPE_V2) { 439 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 440 bank->gpio_regs->int_bothedge); 441 } else { 442 bank->toggle_edge_mode &= ~mask; 443 } 444 switch (type) { 445 case IRQ_TYPE_EDGE_RISING: 446 level |= mask; 447 polarity |= mask; 448 break; 449 case IRQ_TYPE_EDGE_FALLING: 450 level |= mask; 451 polarity &= ~mask; 452 break; 453 case IRQ_TYPE_LEVEL_HIGH: 454 level &= ~mask; 455 polarity |= mask; 456 break; 457 case IRQ_TYPE_LEVEL_LOW: 458 level &= ~mask; 459 polarity &= ~mask; 460 break; 461 default: 462 ret = -EINVAL; 463 goto out; 464 } 465 } 466 467 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); 468 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); 469 out: 470 raw_spin_unlock_irqrestore(&bank->slock, flags); 471 472 return ret; 473 } 474 475 static int rockchip_irq_reqres(struct irq_data *d) 476 { 477 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 478 struct rockchip_pin_bank *bank = gc->private; 479 480 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); 481 } 482 483 static void rockchip_irq_relres(struct irq_data *d) 484 { 485 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 486 struct rockchip_pin_bank *bank = gc->private; 487 488 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); 489 } 490 491 static void rockchip_irq_suspend(struct irq_data *d) 492 { 493 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 494 struct rockchip_pin_bank *bank = gc->private; 495 496 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); 497 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); 498 } 499 500 static void rockchip_irq_resume(struct irq_data *d) 501 { 502 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 503 struct rockchip_pin_bank *bank = gc->private; 504 505 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); 506 } 507 508 static void rockchip_irq_enable(struct irq_data *d) 509 { 510 irq_gc_mask_clr_bit(d); 511 } 512 513 static void rockchip_irq_disable(struct irq_data *d) 514 { 515 irq_gc_mask_set_bit(d); 516 } 517 518 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) 519 { 520 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 521 struct irq_chip_generic *gc; 522 int ret; 523 524 bank->domain = irq_domain_add_linear(bank->of_node, 32, 525 &irq_generic_chip_ops, NULL); 526 if (!bank->domain) { 527 dev_warn(bank->dev, "could not init irq domain for bank %s\n", 528 bank->name); 529 return -EINVAL; 530 } 531 532 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 533 "rockchip_gpio_irq", 534 handle_level_irq, 535 clr, 0, 0); 536 if (ret) { 537 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", 538 bank->name); 539 irq_domain_remove(bank->domain); 540 return -EINVAL; 541 } 542 543 gc = irq_get_domain_generic_chip(bank->domain, 0); 544 if (bank->gpio_type == GPIO_TYPE_V2) { 545 gc->reg_writel = gpio_writel_v2; 546 gc->reg_readl = gpio_readl_v2; 547 } 548 549 gc->reg_base = bank->reg_base; 550 gc->private = bank; 551 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; 552 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; 553 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 554 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 555 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 556 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 557 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 558 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 559 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 560 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 561 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 562 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; 563 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; 564 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 565 566 /* 567 * Linux assumes that all interrupts start out disabled/masked. 568 * Our driver only uses the concept of masked and always keeps 569 * things enabled, so for us that's all masked and all enabled. 570 */ 571 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); 572 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); 573 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); 574 gc->mask_cache = 0xffffffff; 575 576 irq_set_chained_handler_and_data(bank->irq, 577 rockchip_irq_demux, bank); 578 579 return 0; 580 } 581 582 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) 583 { 584 struct gpio_chip *gc; 585 int ret; 586 587 bank->gpio_chip = rockchip_gpiolib_chip; 588 589 gc = &bank->gpio_chip; 590 gc->base = bank->pin_base; 591 gc->ngpio = bank->nr_pins; 592 gc->label = bank->name; 593 gc->parent = bank->dev; 594 595 ret = gpiochip_add_data(gc, bank); 596 if (ret) { 597 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", 598 gc->label, ret); 599 return ret; 600 } 601 602 /* 603 * For DeviceTree-supported systems, the gpio core checks the 604 * pinctrl's device node for the "gpio-ranges" property. 605 * If it is present, it takes care of adding the pin ranges 606 * for the driver. In this case the driver can skip ahead. 607 * 608 * In order to remain compatible with older, existing DeviceTree 609 * files which don't set the "gpio-ranges" property or systems that 610 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 611 */ 612 if (!of_property_present(bank->of_node, "gpio-ranges")) { 613 struct device_node *pctlnp = of_get_parent(bank->of_node); 614 struct pinctrl_dev *pctldev = NULL; 615 616 if (!pctlnp) 617 return -ENODATA; 618 619 pctldev = of_pinctrl_get(pctlnp); 620 of_node_put(pctlnp); 621 if (!pctldev) 622 return -ENODEV; 623 624 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, 625 gc->base, gc->ngpio); 626 if (ret) { 627 dev_err(bank->dev, "Failed to add pin range\n"); 628 goto fail; 629 } 630 } 631 632 ret = rockchip_interrupts_register(bank); 633 if (ret) { 634 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); 635 goto fail; 636 } 637 638 return 0; 639 640 fail: 641 gpiochip_remove(&bank->gpio_chip); 642 643 return ret; 644 } 645 646 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) 647 { 648 struct resource res; 649 int id = 0; 650 651 if (of_address_to_resource(bank->of_node, 0, &res)) { 652 dev_err(bank->dev, "cannot find IO resource for bank\n"); 653 return -ENOENT; 654 } 655 656 bank->reg_base = devm_ioremap_resource(bank->dev, &res); 657 if (IS_ERR(bank->reg_base)) 658 return PTR_ERR(bank->reg_base); 659 660 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 661 if (!bank->irq) 662 return -EINVAL; 663 664 bank->clk = of_clk_get(bank->of_node, 0); 665 if (IS_ERR(bank->clk)) 666 return PTR_ERR(bank->clk); 667 668 clk_prepare_enable(bank->clk); 669 id = readl(bank->reg_base + gpio_regs_v2.version_id); 670 671 switch (id) { 672 case GPIO_TYPE_V2: 673 case GPIO_TYPE_V2_1: 674 case GPIO_TYPE_V2_2: 675 bank->gpio_regs = &gpio_regs_v2; 676 bank->gpio_type = GPIO_TYPE_V2; 677 bank->db_clk = of_clk_get(bank->of_node, 1); 678 if (IS_ERR(bank->db_clk)) { 679 dev_err(bank->dev, "cannot find debounce clk\n"); 680 clk_disable_unprepare(bank->clk); 681 return -EINVAL; 682 } 683 break; 684 case GPIO_TYPE_V1: 685 bank->gpio_regs = &gpio_regs_v1; 686 bank->gpio_type = GPIO_TYPE_V1; 687 break; 688 default: 689 dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id); 690 return -ENODEV; 691 } 692 693 return 0; 694 } 695 696 static struct rockchip_pin_bank * 697 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) 698 { 699 struct rockchip_pinctrl *info; 700 struct rockchip_pin_bank *bank; 701 int i, found = 0; 702 703 info = pinctrl_dev_get_drvdata(pctldev); 704 bank = info->ctrl->pin_banks; 705 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { 706 if (bank->bank_num == id) { 707 found = 1; 708 break; 709 } 710 } 711 712 return found ? bank : NULL; 713 } 714 715 static int rockchip_gpio_probe(struct platform_device *pdev) 716 { 717 struct device *dev = &pdev->dev; 718 struct device_node *np = dev->of_node; 719 struct device_node *pctlnp = of_get_parent(np); 720 struct pinctrl_dev *pctldev = NULL; 721 struct rockchip_pin_bank *bank = NULL; 722 struct rockchip_pin_deferred *cfg; 723 static int gpio; 724 int id, ret; 725 726 if (!np || !pctlnp) 727 return -ENODEV; 728 729 pctldev = of_pinctrl_get(pctlnp); 730 of_node_put(pctlnp); 731 if (!pctldev) 732 return -EPROBE_DEFER; 733 734 id = of_alias_get_id(np, "gpio"); 735 if (id < 0) 736 id = gpio++; 737 738 bank = rockchip_gpio_find_bank(pctldev, id); 739 if (!bank) 740 return -EINVAL; 741 742 bank->dev = dev; 743 bank->of_node = np; 744 745 raw_spin_lock_init(&bank->slock); 746 747 ret = rockchip_get_bank_data(bank); 748 if (ret) 749 return ret; 750 751 /* 752 * Prevent clashes with a deferred output setting 753 * being added right at this moment. 754 */ 755 mutex_lock(&bank->deferred_lock); 756 757 ret = rockchip_gpiolib_register(bank); 758 if (ret) { 759 clk_disable_unprepare(bank->clk); 760 mutex_unlock(&bank->deferred_lock); 761 return ret; 762 } 763 764 while (!list_empty(&bank->deferred_pins)) { 765 cfg = list_first_entry(&bank->deferred_pins, 766 struct rockchip_pin_deferred, head); 767 list_del(&cfg->head); 768 769 switch (cfg->param) { 770 case PIN_CONFIG_OUTPUT: 771 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); 772 if (ret) 773 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, 774 cfg->arg); 775 break; 776 case PIN_CONFIG_INPUT_ENABLE: 777 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); 778 if (ret) 779 dev_warn(dev, "setting input pin %u failed\n", cfg->pin); 780 break; 781 default: 782 dev_warn(dev, "unknown deferred config param %d\n", cfg->param); 783 break; 784 } 785 kfree(cfg); 786 } 787 788 mutex_unlock(&bank->deferred_lock); 789 790 platform_set_drvdata(pdev, bank); 791 dev_info(dev, "probed %pOF\n", np); 792 793 return 0; 794 } 795 796 static void rockchip_gpio_remove(struct platform_device *pdev) 797 { 798 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); 799 800 clk_disable_unprepare(bank->clk); 801 gpiochip_remove(&bank->gpio_chip); 802 } 803 804 static const struct of_device_id rockchip_gpio_match[] = { 805 { .compatible = "rockchip,gpio-bank", }, 806 { .compatible = "rockchip,rk3188-gpio-bank0" }, 807 { }, 808 }; 809 810 static struct platform_driver rockchip_gpio_driver = { 811 .probe = rockchip_gpio_probe, 812 .remove = rockchip_gpio_remove, 813 .driver = { 814 .name = "rockchip-gpio", 815 .of_match_table = rockchip_gpio_match, 816 }, 817 }; 818 819 static int __init rockchip_gpio_init(void) 820 { 821 return platform_driver_register(&rockchip_gpio_driver); 822 } 823 postcore_initcall(rockchip_gpio_init); 824 825 static void __exit rockchip_gpio_exit(void) 826 { 827 platform_driver_unregister(&rockchip_gpio_driver); 828 } 829 module_exit(rockchip_gpio_exit); 830 831 MODULE_DESCRIPTION("Rockchip gpio driver"); 832 MODULE_ALIAS("platform:rockchip-gpio"); 833 MODULE_LICENSE("GPL v2"); 834 MODULE_DEVICE_TABLE(of, rockchip_gpio_match); 835