1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 * 6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/pinctrl/pinconf-generic.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 26 #include "../pinctrl/core.h" 27 #include "../pinctrl/pinctrl-rockchip.h" 28 29 /* 30 * Version ID Register 31 * Bits [31:24] - Major Version 32 * Bits [23:16] - Minor Version 33 * Bits [15:0] - Revision Number 34 */ 35 #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ 36 #define GPIO_TYPE_V2 (0x01000C2B) 37 #define GPIO_TYPE_V2_1 (0x0101157C) 38 #define GPIO_TYPE_V2_2 (0x010219C8) 39 40 static const struct rockchip_gpio_regs gpio_regs_v1 = { 41 .port_dr = 0x00, 42 .port_ddr = 0x04, 43 .int_en = 0x30, 44 .int_mask = 0x34, 45 .int_type = 0x38, 46 .int_polarity = 0x3c, 47 .int_status = 0x40, 48 .int_rawstatus = 0x44, 49 .debounce = 0x48, 50 .port_eoi = 0x4c, 51 .ext_port = 0x50, 52 }; 53 54 static const struct rockchip_gpio_regs gpio_regs_v2 = { 55 .port_dr = 0x00, 56 .port_ddr = 0x08, 57 .int_en = 0x10, 58 .int_mask = 0x18, 59 .int_type = 0x20, 60 .int_polarity = 0x28, 61 .int_bothedge = 0x30, 62 .int_status = 0x50, 63 .int_rawstatus = 0x58, 64 .debounce = 0x38, 65 .dbclk_div_en = 0x40, 66 .dbclk_div_con = 0x48, 67 .port_eoi = 0x60, 68 .ext_port = 0x70, 69 .version_id = 0x78, 70 }; 71 72 static inline void gpio_writel_v2(u32 val, void __iomem *reg) 73 { 74 writel((val & 0xffff) | 0xffff0000, reg); 75 writel((val >> 16) | 0xffff0000, reg + 0x4); 76 } 77 78 static inline u32 gpio_readl_v2(void __iomem *reg) 79 { 80 return readl(reg + 0x4) << 16 | readl(reg); 81 } 82 83 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, 84 u32 value, unsigned int offset) 85 { 86 void __iomem *reg = bank->reg_base + offset; 87 88 if (bank->gpio_type == GPIO_TYPE_V2) 89 gpio_writel_v2(value, reg); 90 else 91 writel(value, reg); 92 } 93 94 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, 95 unsigned int offset) 96 { 97 void __iomem *reg = bank->reg_base + offset; 98 u32 value; 99 100 if (bank->gpio_type == GPIO_TYPE_V2) 101 value = gpio_readl_v2(reg); 102 else 103 value = readl(reg); 104 105 return value; 106 } 107 108 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, 109 u32 bit, u32 value, 110 unsigned int offset) 111 { 112 void __iomem *reg = bank->reg_base + offset; 113 u32 data; 114 115 if (bank->gpio_type == GPIO_TYPE_V2) { 116 if (value) 117 data = BIT(bit % 16) | BIT(bit % 16 + 16); 118 else 119 data = BIT(bit % 16 + 16); 120 writel(data, bit >= 16 ? reg + 0x4 : reg); 121 } else { 122 data = readl(reg); 123 data &= ~BIT(bit); 124 if (value) 125 data |= BIT(bit); 126 writel(data, reg); 127 } 128 } 129 130 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, 131 u32 bit, unsigned int offset) 132 { 133 void __iomem *reg = bank->reg_base + offset; 134 u32 data; 135 136 if (bank->gpio_type == GPIO_TYPE_V2) { 137 data = readl(bit >= 16 ? reg + 0x4 : reg); 138 data >>= bit % 16; 139 } else { 140 data = readl(reg); 141 data >>= bit; 142 } 143 144 return data & (0x1); 145 } 146 147 static int rockchip_gpio_get_direction(struct gpio_chip *chip, 148 unsigned int offset) 149 { 150 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 151 u32 data; 152 153 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); 154 if (data) 155 return GPIO_LINE_DIRECTION_OUT; 156 157 return GPIO_LINE_DIRECTION_IN; 158 } 159 160 static int rockchip_gpio_set_direction(struct gpio_chip *chip, 161 unsigned int offset, bool input) 162 { 163 struct rockchip_pin_bank *bank = gpiochip_get_data(chip); 164 unsigned long flags; 165 u32 data = input ? 0 : 1; 166 167 168 if (input) 169 pinctrl_gpio_direction_input(chip, offset); 170 else 171 pinctrl_gpio_direction_output(chip, offset); 172 173 raw_spin_lock_irqsave(&bank->slock, flags); 174 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); 175 raw_spin_unlock_irqrestore(&bank->slock, flags); 176 177 return 0; 178 } 179 180 static int rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, 181 int value) 182 { 183 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 184 unsigned long flags; 185 186 raw_spin_lock_irqsave(&bank->slock, flags); 187 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); 188 raw_spin_unlock_irqrestore(&bank->slock, flags); 189 190 return 0; 191 } 192 193 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) 194 { 195 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 196 u32 data; 197 198 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 199 data >>= offset; 200 data &= 1; 201 202 return data; 203 } 204 205 static int rockchip_gpio_set_debounce(struct gpio_chip *gc, 206 unsigned int offset, 207 unsigned int debounce) 208 { 209 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 210 const struct rockchip_gpio_regs *reg = bank->gpio_regs; 211 unsigned long flags, div_reg, freq, max_debounce; 212 bool div_debounce_support; 213 unsigned int cur_div_reg; 214 u64 div; 215 216 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { 217 div_debounce_support = true; 218 freq = clk_get_rate(bank->db_clk); 219 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; 220 if (debounce > max_debounce) 221 return -EINVAL; 222 223 div = debounce * freq; 224 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; 225 } else { 226 div_debounce_support = false; 227 } 228 229 raw_spin_lock_irqsave(&bank->slock, flags); 230 231 /* Only the v1 needs to configure div_en and div_con for dbclk */ 232 if (debounce) { 233 if (div_debounce_support) { 234 /* Configure the max debounce from consumers */ 235 cur_div_reg = readl(bank->reg_base + 236 reg->dbclk_div_con); 237 if (cur_div_reg < div_reg) 238 writel(div_reg, bank->reg_base + 239 reg->dbclk_div_con); 240 rockchip_gpio_writel_bit(bank, offset, 1, 241 reg->dbclk_div_en); 242 } 243 244 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); 245 } else { 246 if (div_debounce_support) 247 rockchip_gpio_writel_bit(bank, offset, 0, 248 reg->dbclk_div_en); 249 250 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); 251 } 252 253 raw_spin_unlock_irqrestore(&bank->slock, flags); 254 255 /* Enable or disable dbclk at last */ 256 if (div_debounce_support) { 257 if (debounce) 258 clk_prepare_enable(bank->db_clk); 259 else 260 clk_disable_unprepare(bank->db_clk); 261 } 262 263 return 0; 264 } 265 266 static int rockchip_gpio_direction_input(struct gpio_chip *gc, 267 unsigned int offset) 268 { 269 return rockchip_gpio_set_direction(gc, offset, true); 270 } 271 272 static int rockchip_gpio_direction_output(struct gpio_chip *gc, 273 unsigned int offset, int value) 274 { 275 rockchip_gpio_set(gc, offset, value); 276 277 return rockchip_gpio_set_direction(gc, offset, false); 278 } 279 280 /* 281 * gpiolib set_config callback function. The setting of the pin 282 * mux function as 'gpio output' will be handled by the pinctrl subsystem 283 * interface. 284 */ 285 static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 286 unsigned long config) 287 { 288 enum pin_config_param param = pinconf_to_config_param(config); 289 290 switch (param) { 291 case PIN_CONFIG_INPUT_DEBOUNCE: 292 rockchip_gpio_set_debounce(gc, offset, true); 293 /* 294 * Rockchip's gpio could only support up to one period 295 * of the debounce clock(pclk), which is far away from 296 * satisftying the requirement, as pclk is usually near 297 * 100MHz shared by all peripherals. So the fact is it 298 * has crippled debounce capability could only be useful 299 * to prevent any spurious glitches from waking up the system 300 * if the gpio is conguired as wakeup interrupt source. Let's 301 * still return -ENOTSUPP as before, to make sure the caller 302 * of gpiod_set_debounce won't change its behaviour. 303 */ 304 return -ENOTSUPP; 305 default: 306 return -ENOTSUPP; 307 } 308 } 309 310 /* 311 * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin 312 * and a virtual IRQ, if not already present. 313 */ 314 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 315 { 316 struct rockchip_pin_bank *bank = gpiochip_get_data(gc); 317 unsigned int virq; 318 319 if (!bank->domain) 320 return -ENXIO; 321 322 virq = irq_create_mapping(bank->domain, offset); 323 324 return (virq) ? : -ENXIO; 325 } 326 327 static const struct gpio_chip rockchip_gpiolib_chip = { 328 .request = gpiochip_generic_request, 329 .free = gpiochip_generic_free, 330 .set = rockchip_gpio_set, 331 .get = rockchip_gpio_get, 332 .get_direction = rockchip_gpio_get_direction, 333 .direction_input = rockchip_gpio_direction_input, 334 .direction_output = rockchip_gpio_direction_output, 335 .set_config = rockchip_gpio_set_config, 336 .to_irq = rockchip_gpio_to_irq, 337 .owner = THIS_MODULE, 338 }; 339 340 static void rockchip_irq_demux(struct irq_desc *desc) 341 { 342 struct irq_chip *chip = irq_desc_get_chip(desc); 343 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); 344 unsigned long pending; 345 unsigned int irq; 346 347 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); 348 349 chained_irq_enter(chip, desc); 350 351 pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); 352 for_each_set_bit(irq, &pending, 32) { 353 dev_dbg(bank->dev, "handling irq %d\n", irq); 354 355 /* 356 * Triggering IRQ on both rising and falling edge 357 * needs manual intervention. 358 */ 359 if (bank->toggle_edge_mode & BIT(irq)) { 360 u32 data, data_old, polarity; 361 unsigned long flags; 362 363 data = readl_relaxed(bank->reg_base + 364 bank->gpio_regs->ext_port); 365 do { 366 raw_spin_lock_irqsave(&bank->slock, flags); 367 368 polarity = readl_relaxed(bank->reg_base + 369 bank->gpio_regs->int_polarity); 370 if (data & BIT(irq)) 371 polarity &= ~BIT(irq); 372 else 373 polarity |= BIT(irq); 374 writel(polarity, 375 bank->reg_base + 376 bank->gpio_regs->int_polarity); 377 378 raw_spin_unlock_irqrestore(&bank->slock, flags); 379 380 data_old = data; 381 data = readl_relaxed(bank->reg_base + 382 bank->gpio_regs->ext_port); 383 } while ((data & BIT(irq)) != (data_old & BIT(irq))); 384 } 385 386 generic_handle_domain_irq(bank->domain, irq); 387 } 388 389 chained_irq_exit(chip, desc); 390 } 391 392 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) 393 { 394 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 395 struct rockchip_pin_bank *bank = gc->private; 396 u32 mask = BIT(d->hwirq); 397 u32 polarity; 398 u32 level; 399 u32 data; 400 unsigned long flags; 401 int ret = 0; 402 403 raw_spin_lock_irqsave(&bank->slock, flags); 404 405 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 406 bank->gpio_regs->port_ddr); 407 408 raw_spin_unlock_irqrestore(&bank->slock, flags); 409 410 if (type & IRQ_TYPE_EDGE_BOTH) 411 irq_set_handler_locked(d, handle_edge_irq); 412 else 413 irq_set_handler_locked(d, handle_level_irq); 414 415 raw_spin_lock_irqsave(&bank->slock, flags); 416 417 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); 418 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); 419 420 if (type == IRQ_TYPE_EDGE_BOTH) { 421 if (bank->gpio_type == GPIO_TYPE_V2) { 422 rockchip_gpio_writel_bit(bank, d->hwirq, 1, 423 bank->gpio_regs->int_bothedge); 424 goto out; 425 } else { 426 bank->toggle_edge_mode |= mask; 427 level &= ~mask; 428 429 /* 430 * Determine gpio state. If 1 next interrupt should be 431 * low otherwise high. 432 */ 433 data = readl(bank->reg_base + bank->gpio_regs->ext_port); 434 if (data & mask) 435 polarity &= ~mask; 436 else 437 polarity |= mask; 438 } 439 } else { 440 if (bank->gpio_type == GPIO_TYPE_V2) { 441 rockchip_gpio_writel_bit(bank, d->hwirq, 0, 442 bank->gpio_regs->int_bothedge); 443 } else { 444 bank->toggle_edge_mode &= ~mask; 445 } 446 switch (type) { 447 case IRQ_TYPE_EDGE_RISING: 448 level |= mask; 449 polarity |= mask; 450 break; 451 case IRQ_TYPE_EDGE_FALLING: 452 level |= mask; 453 polarity &= ~mask; 454 break; 455 case IRQ_TYPE_LEVEL_HIGH: 456 level &= ~mask; 457 polarity |= mask; 458 break; 459 case IRQ_TYPE_LEVEL_LOW: 460 level &= ~mask; 461 polarity &= ~mask; 462 break; 463 default: 464 ret = -EINVAL; 465 goto out; 466 } 467 } 468 469 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); 470 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); 471 out: 472 raw_spin_unlock_irqrestore(&bank->slock, flags); 473 474 return ret; 475 } 476 477 static int rockchip_irq_reqres(struct irq_data *d) 478 { 479 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 480 struct rockchip_pin_bank *bank = gc->private; 481 482 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); 483 } 484 485 static void rockchip_irq_relres(struct irq_data *d) 486 { 487 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 488 struct rockchip_pin_bank *bank = gc->private; 489 490 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); 491 } 492 493 static void rockchip_irq_suspend(struct irq_data *d) 494 { 495 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 496 struct rockchip_pin_bank *bank = gc->private; 497 498 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); 499 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); 500 } 501 502 static void rockchip_irq_resume(struct irq_data *d) 503 { 504 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 505 struct rockchip_pin_bank *bank = gc->private; 506 507 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); 508 } 509 510 static void rockchip_irq_enable(struct irq_data *d) 511 { 512 irq_gc_mask_clr_bit(d); 513 } 514 515 static void rockchip_irq_disable(struct irq_data *d) 516 { 517 irq_gc_mask_set_bit(d); 518 } 519 520 static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) 521 { 522 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 523 struct irq_chip_generic *gc; 524 int ret; 525 526 bank->domain = irq_domain_create_linear(dev_fwnode(bank->dev), 32, &irq_generic_chip_ops, 527 NULL); 528 if (!bank->domain) { 529 dev_warn(bank->dev, "could not init irq domain for bank %s\n", 530 bank->name); 531 return -EINVAL; 532 } 533 534 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, 535 "rockchip_gpio_irq", 536 handle_level_irq, 537 clr, 0, 0); 538 if (ret) { 539 dev_err(bank->dev, "could not alloc generic chips for bank %s\n", 540 bank->name); 541 irq_domain_remove(bank->domain); 542 return -EINVAL; 543 } 544 545 gc = irq_get_domain_generic_chip(bank->domain, 0); 546 if (bank->gpio_type == GPIO_TYPE_V2) { 547 gc->reg_writel = gpio_writel_v2; 548 gc->reg_readl = gpio_readl_v2; 549 } 550 551 gc->reg_base = bank->reg_base; 552 gc->private = bank; 553 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; 554 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; 555 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 556 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 557 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 558 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; 559 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; 560 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 561 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 562 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 563 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 564 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; 565 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; 566 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 567 568 /* 569 * Linux assumes that all interrupts start out disabled/masked. 570 * Our driver only uses the concept of masked and always keeps 571 * things enabled, so for us that's all masked and all enabled. 572 */ 573 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); 574 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); 575 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); 576 gc->mask_cache = 0xffffffff; 577 578 irq_set_chained_handler_and_data(bank->irq, 579 rockchip_irq_demux, bank); 580 581 return 0; 582 } 583 584 static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) 585 { 586 struct gpio_chip *gc; 587 int ret; 588 589 bank->gpio_chip = rockchip_gpiolib_chip; 590 591 gc = &bank->gpio_chip; 592 gc->base = bank->pin_base; 593 gc->ngpio = bank->nr_pins; 594 gc->label = bank->name; 595 gc->parent = bank->dev; 596 gc->can_sleep = true; 597 598 ret = gpiochip_add_data(gc, bank); 599 if (ret) { 600 dev_err(bank->dev, "failed to add gpiochip %s, %d\n", 601 gc->label, ret); 602 return ret; 603 } 604 605 /* 606 * For DeviceTree-supported systems, the gpio core checks the 607 * pinctrl's device node for the "gpio-ranges" property. 608 * If it is present, it takes care of adding the pin ranges 609 * for the driver. In this case the driver can skip ahead. 610 * 611 * In order to remain compatible with older, existing DeviceTree 612 * files which don't set the "gpio-ranges" property or systems that 613 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 614 */ 615 if (!of_property_present(bank->of_node, "gpio-ranges")) { 616 struct device_node *pctlnp = of_get_parent(bank->of_node); 617 struct pinctrl_dev *pctldev = NULL; 618 619 if (!pctlnp) 620 return -ENODATA; 621 622 pctldev = of_pinctrl_get(pctlnp); 623 of_node_put(pctlnp); 624 if (!pctldev) 625 return -ENODEV; 626 627 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, 628 gc->base, gc->ngpio); 629 if (ret) { 630 dev_err(bank->dev, "Failed to add pin range\n"); 631 goto fail; 632 } 633 } 634 635 ret = rockchip_interrupts_register(bank); 636 if (ret) { 637 dev_err(bank->dev, "failed to register interrupt, %d\n", ret); 638 goto fail; 639 } 640 641 return 0; 642 643 fail: 644 gpiochip_remove(&bank->gpio_chip); 645 646 return ret; 647 } 648 649 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) 650 { 651 struct resource res; 652 int id = 0; 653 654 if (of_address_to_resource(bank->of_node, 0, &res)) { 655 dev_err(bank->dev, "cannot find IO resource for bank\n"); 656 return -ENOENT; 657 } 658 659 bank->reg_base = devm_ioremap_resource(bank->dev, &res); 660 if (IS_ERR(bank->reg_base)) 661 return PTR_ERR(bank->reg_base); 662 663 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 664 if (!bank->irq) 665 return -EINVAL; 666 667 bank->clk = of_clk_get(bank->of_node, 0); 668 if (IS_ERR(bank->clk)) 669 return PTR_ERR(bank->clk); 670 671 clk_prepare_enable(bank->clk); 672 id = readl(bank->reg_base + gpio_regs_v2.version_id); 673 674 switch (id) { 675 case GPIO_TYPE_V2: 676 case GPIO_TYPE_V2_1: 677 case GPIO_TYPE_V2_2: 678 bank->gpio_regs = &gpio_regs_v2; 679 bank->gpio_type = GPIO_TYPE_V2; 680 bank->db_clk = of_clk_get(bank->of_node, 1); 681 if (IS_ERR(bank->db_clk)) { 682 dev_err(bank->dev, "cannot find debounce clk\n"); 683 clk_disable_unprepare(bank->clk); 684 return -EINVAL; 685 } 686 break; 687 case GPIO_TYPE_V1: 688 bank->gpio_regs = &gpio_regs_v1; 689 bank->gpio_type = GPIO_TYPE_V1; 690 break; 691 default: 692 dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id); 693 return -ENODEV; 694 } 695 696 return 0; 697 } 698 699 static struct rockchip_pin_bank * 700 rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) 701 { 702 struct rockchip_pinctrl *info; 703 struct rockchip_pin_bank *bank; 704 int i, found = 0; 705 706 info = pinctrl_dev_get_drvdata(pctldev); 707 bank = info->ctrl->pin_banks; 708 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { 709 if (bank->bank_num == id) { 710 found = 1; 711 break; 712 } 713 } 714 715 return found ? bank : NULL; 716 } 717 718 static int rockchip_gpio_probe(struct platform_device *pdev) 719 { 720 struct device *dev = &pdev->dev; 721 struct device_node *np = dev->of_node; 722 struct device_node *pctlnp = of_get_parent(np); 723 struct pinctrl_dev *pctldev = NULL; 724 struct rockchip_pin_bank *bank = NULL; 725 struct rockchip_pin_deferred *cfg; 726 static int gpio; 727 int id, ret; 728 729 if (!np || !pctlnp) 730 return -ENODEV; 731 732 pctldev = of_pinctrl_get(pctlnp); 733 of_node_put(pctlnp); 734 if (!pctldev) 735 return -EPROBE_DEFER; 736 737 id = of_alias_get_id(np, "gpio"); 738 if (id < 0) 739 id = gpio++; 740 741 bank = rockchip_gpio_find_bank(pctldev, id); 742 if (!bank) 743 return -EINVAL; 744 745 bank->dev = dev; 746 bank->of_node = np; 747 748 raw_spin_lock_init(&bank->slock); 749 750 ret = rockchip_get_bank_data(bank); 751 if (ret) 752 return ret; 753 754 /* 755 * Prevent clashes with a deferred output setting 756 * being added right at this moment. 757 */ 758 mutex_lock(&bank->deferred_lock); 759 760 ret = rockchip_gpiolib_register(bank); 761 if (ret) { 762 clk_disable_unprepare(bank->clk); 763 mutex_unlock(&bank->deferred_lock); 764 return ret; 765 } 766 767 while (!list_empty(&bank->deferred_pins)) { 768 cfg = list_first_entry(&bank->deferred_pins, 769 struct rockchip_pin_deferred, head); 770 list_del(&cfg->head); 771 772 switch (cfg->param) { 773 case PIN_CONFIG_LEVEL: 774 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); 775 if (ret) 776 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, 777 cfg->arg); 778 break; 779 case PIN_CONFIG_INPUT_ENABLE: 780 ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); 781 if (ret) 782 dev_warn(dev, "setting input pin %u failed\n", cfg->pin); 783 break; 784 default: 785 dev_warn(dev, "unknown deferred config param %d\n", cfg->param); 786 break; 787 } 788 kfree(cfg); 789 } 790 791 mutex_unlock(&bank->deferred_lock); 792 793 platform_set_drvdata(pdev, bank); 794 dev_info(dev, "probed %pOF\n", np); 795 796 return 0; 797 } 798 799 static void rockchip_gpio_remove(struct platform_device *pdev) 800 { 801 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); 802 803 clk_disable_unprepare(bank->clk); 804 gpiochip_remove(&bank->gpio_chip); 805 } 806 807 static const struct of_device_id rockchip_gpio_match[] = { 808 { .compatible = "rockchip,gpio-bank", }, 809 { .compatible = "rockchip,rk3188-gpio-bank0" }, 810 { }, 811 }; 812 813 static struct platform_driver rockchip_gpio_driver = { 814 .probe = rockchip_gpio_probe, 815 .remove = rockchip_gpio_remove, 816 .driver = { 817 .name = "rockchip-gpio", 818 .of_match_table = rockchip_gpio_match, 819 }, 820 }; 821 822 static int __init rockchip_gpio_init(void) 823 { 824 return platform_driver_register(&rockchip_gpio_driver); 825 } 826 postcore_initcall(rockchip_gpio_init); 827 828 static void __exit rockchip_gpio_exit(void) 829 { 830 platform_driver_unregister(&rockchip_gpio_driver); 831 } 832 module_exit(rockchip_gpio_exit); 833 834 MODULE_DESCRIPTION("Rockchip gpio driver"); 835 MODULE_ALIAS("platform:rockchip-gpio"); 836 MODULE_LICENSE("GPL v2"); 837 MODULE_DEVICE_TABLE(of, rockchip_gpio_match); 838