1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/cpumask.h> 4 #include <linux/gpio/driver.h> 5 #include <linux/gpio/generic.h> 6 #include <linux/irq.h> 7 #include <linux/minmax.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/property.h> 12 13 /* 14 * Total register block size is 0x1C for one bank of four ports (A, B, C, D). 15 * An optional second bank, with ports E, F, G, and H, may be present, starting 16 * at register offset 0x1C. 17 */ 18 19 /* 20 * Pin select: (0) "normal", (1) "dedicate peripheral" 21 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits 22 * in the peripheral registers. 23 */ 24 #define REALTEK_GPIO_REG_CNR 0x00 25 /* Clear bit (0) for input, set bit (1) for output */ 26 #define REALTEK_GPIO_REG_DIR 0x08 27 #define REALTEK_GPIO_REG_DATA 0x0C 28 /* Read bit for IRQ status, write 1 to clear IRQ */ 29 #define REALTEK_GPIO_REG_ISR 0x10 30 /* Two bits per GPIO in IMR registers */ 31 #define REALTEK_GPIO_REG_IMR 0x14 32 #define REALTEK_GPIO_REG_IMR_AB 0x14 33 #define REALTEK_GPIO_REG_IMR_CD 0x18 34 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0) 35 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1 36 #define REALTEK_GPIO_IRQ_EDGE_RISING 2 37 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3 38 39 #define REALTEK_GPIO_MAX 32 40 #define REALTEK_GPIO_PORTS_PER_BANK 4 41 42 /** 43 * struct realtek_gpio_ctrl - Realtek Otto GPIO driver data 44 * 45 * @chip: Associated gpio_generic_chip instance 46 * @base: Base address of the register block for a GPIO bank 47 * @cpumask_base: Base address of the per-CPU interrupt mask registers 48 * @cpu_irq_maskable: CPUs that can receive GPIO interrupts 49 * @lock: Lock for accessing the IRQ registers and values 50 * @intr_mask: Mask for interrupts lines 51 * @intr_type: Interrupt type selection 52 * @bank_read: Read a bank setting as a single 32-bit value 53 * @bank_write: Write a bank setting as a single 32-bit value 54 * @line_imr_pos: Bit shift of an IRQ line's IMR value. 55 * 56 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed 57 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign) 58 * a value from (to) these registers. The IMR register consists of four 16-bit 59 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the 60 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than 61 * 32 overflow into the second register. 62 * 63 * Because the interrupt mask register (IMR) combines the function of IRQ type 64 * selection and masking, two extra values are stored. @intr_mask is used to 65 * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store 66 * the selected interrupt types. The logical AND of these values is written to 67 * IMR on changes. 68 */ 69 struct realtek_gpio_ctrl { 70 struct gpio_generic_chip chip; 71 void __iomem *base; 72 void __iomem *cpumask_base; 73 struct cpumask cpu_irq_maskable; 74 raw_spinlock_t lock; 75 u8 intr_mask[REALTEK_GPIO_MAX]; 76 u8 intr_type[REALTEK_GPIO_MAX]; 77 u32 (*bank_read)(void __iomem *reg); 78 void (*bank_write)(void __iomem *reg, u32 value); 79 unsigned int (*line_imr_pos)(unsigned int line); 80 }; 81 82 /* Expand with more flags as devices with other quirks are added */ 83 enum realtek_gpio_flags { 84 /* 85 * Allow disabling interrupts, for cases where the port order is 86 * unknown. This may result in a port mismatch between ISR and IMR. 87 * An interrupt would appear to come from a different line than the 88 * line the IRQ handler was assigned to, causing uncaught interrupts. 89 */ 90 GPIO_INTERRUPTS_DISABLED = BIT(0), 91 /* 92 * Port order is reversed, meaning DCBA register layout for 1-bit 93 * fields, and [BA, DC] for 2-bit fields. 94 */ 95 GPIO_PORTS_REVERSED = BIT(1), 96 /* 97 * Interrupts can be enabled per cpu. This requires a secondary IO 98 * range, where the per-cpu enable masks are located. 99 */ 100 GPIO_INTERRUPTS_PER_CPU = BIT(2), 101 }; 102 103 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) 104 { 105 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 106 107 return container_of(to_gpio_generic_chip(gc), struct realtek_gpio_ctrl, chip); 108 } 109 110 /* 111 * Normal port order register access 112 * 113 * Port information is stored with the first port at offset 0, followed by the 114 * second, etc. Most registers store one bit per GPIO and use a u8 value per 115 * port. The two interrupt mask registers store two bits per GPIO, so use u16 116 * values. 117 */ 118 static u32 realtek_gpio_bank_read_swapped(void __iomem *reg) 119 { 120 return ioread32be(reg); 121 } 122 123 static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value) 124 { 125 iowrite32be(value, reg); 126 } 127 128 static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line) 129 { 130 unsigned int port_pin = line % 8; 131 unsigned int port = line / 8; 132 133 return 2 * (8 * (port ^ 1) + port_pin); 134 } 135 136 /* 137 * Reversed port order register access 138 * 139 * For registers with one bit per GPIO, all ports are stored as u8-s in one 140 * register in reversed order. The two interrupt mask registers store two bits 141 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the 142 * second ports 3 and 2. 143 */ 144 static u32 realtek_gpio_bank_read(void __iomem *reg) 145 { 146 return ioread32(reg); 147 } 148 149 static void realtek_gpio_bank_write(void __iomem *reg, u32 value) 150 { 151 iowrite32(value, reg); 152 } 153 154 static unsigned int realtek_gpio_line_imr_pos(unsigned int line) 155 { 156 return 2 * line; 157 } 158 159 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask) 160 { 161 ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask); 162 } 163 164 static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl) 165 { 166 return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR); 167 } 168 169 /* Set the rising and falling edge mask bits for a GPIO pin */ 170 static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line) 171 { 172 void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR; 173 unsigned int line_shift = ctrl->line_imr_pos(line); 174 unsigned int shift = line_shift % 32; 175 u32 irq_type = ctrl->intr_type[line]; 176 u32 irq_mask = ctrl->intr_mask[line]; 177 u32 reg_val; 178 179 reg += 4 * (line_shift / 32); 180 reg_val = ioread32(reg); 181 reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift); 182 reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift; 183 iowrite32(reg_val, reg); 184 } 185 186 static void realtek_gpio_irq_ack(struct irq_data *data) 187 { 188 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 189 irq_hw_number_t line = irqd_to_hwirq(data); 190 191 realtek_gpio_clear_isr(ctrl, BIT(line)); 192 } 193 194 static void realtek_gpio_irq_unmask(struct irq_data *data) 195 { 196 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 197 unsigned int line = irqd_to_hwirq(data); 198 unsigned long flags; 199 200 gpiochip_enable_irq(&ctrl->chip.gc, line); 201 202 raw_spin_lock_irqsave(&ctrl->lock, flags); 203 ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; 204 realtek_gpio_update_line_imr(ctrl, line); 205 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 206 } 207 208 static void realtek_gpio_irq_mask(struct irq_data *data) 209 { 210 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 211 unsigned int line = irqd_to_hwirq(data); 212 unsigned long flags; 213 214 raw_spin_lock_irqsave(&ctrl->lock, flags); 215 ctrl->intr_mask[line] = 0; 216 realtek_gpio_update_line_imr(ctrl, line); 217 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 218 219 gpiochip_disable_irq(&ctrl->chip.gc, line); 220 } 221 222 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) 223 { 224 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 225 unsigned int line = irqd_to_hwirq(data); 226 unsigned long flags; 227 u8 type; 228 229 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 230 case IRQ_TYPE_EDGE_FALLING: 231 type = REALTEK_GPIO_IRQ_EDGE_FALLING; 232 break; 233 case IRQ_TYPE_EDGE_RISING: 234 type = REALTEK_GPIO_IRQ_EDGE_RISING; 235 break; 236 case IRQ_TYPE_EDGE_BOTH: 237 type = REALTEK_GPIO_IRQ_EDGE_BOTH; 238 break; 239 default: 240 return -EINVAL; 241 } 242 243 irq_set_handler_locked(data, handle_edge_irq); 244 245 raw_spin_lock_irqsave(&ctrl->lock, flags); 246 ctrl->intr_type[line] = type; 247 realtek_gpio_update_line_imr(ctrl, line); 248 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 249 250 return 0; 251 } 252 253 static void realtek_gpio_irq_handler(struct irq_desc *desc) 254 { 255 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 256 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 257 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 258 unsigned long status; 259 int offset; 260 261 chained_irq_enter(irq_chip, desc); 262 263 status = realtek_gpio_read_isr(ctrl); 264 for_each_set_bit(offset, &status, gc->ngpio) 265 generic_handle_domain_irq(gc->irq.domain, offset); 266 267 chained_irq_exit(irq_chip, desc); 268 } 269 270 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu) 271 { 272 return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu; 273 } 274 275 static int realtek_gpio_irq_set_affinity(struct irq_data *data, 276 const struct cpumask *dest, bool force) 277 { 278 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 279 unsigned int line = irqd_to_hwirq(data); 280 void __iomem *irq_cpu_mask; 281 unsigned long flags; 282 int cpu; 283 u32 v; 284 285 if (!ctrl->cpumask_base) 286 return -ENXIO; 287 288 raw_spin_lock_irqsave(&ctrl->lock, flags); 289 290 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { 291 irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); 292 v = ctrl->bank_read(irq_cpu_mask); 293 294 if (cpumask_test_cpu(cpu, dest)) 295 v |= BIT(line); 296 else 297 v &= ~BIT(line); 298 299 ctrl->bank_write(irq_cpu_mask, v); 300 } 301 302 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 303 304 irq_data_update_effective_affinity(data, dest); 305 306 return 0; 307 } 308 309 static int realtek_gpio_irq_init(struct gpio_chip *gc) 310 { 311 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 312 u32 mask_all = GENMASK(gc->ngpio - 1, 0); 313 unsigned int line; 314 int cpu; 315 316 for (line = 0; line < gc->ngpio; line++) 317 realtek_gpio_update_line_imr(ctrl, line); 318 319 realtek_gpio_clear_isr(ctrl, mask_all); 320 321 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) 322 ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all); 323 324 return 0; 325 } 326 327 static const struct irq_chip realtek_gpio_irq_chip = { 328 .name = "realtek-otto-gpio", 329 .irq_ack = realtek_gpio_irq_ack, 330 .irq_mask = realtek_gpio_irq_mask, 331 .irq_unmask = realtek_gpio_irq_unmask, 332 .irq_set_type = realtek_gpio_irq_set_type, 333 .irq_set_affinity = realtek_gpio_irq_set_affinity, 334 .flags = IRQCHIP_IMMUTABLE, 335 GPIOCHIP_IRQ_RESOURCE_HELPERS, 336 }; 337 338 static const struct of_device_id realtek_gpio_of_match[] = { 339 { 340 .compatible = "realtek,otto-gpio", 341 .data = (void *)GPIO_INTERRUPTS_DISABLED, 342 }, 343 { 344 .compatible = "realtek,rtl8380-gpio", 345 }, 346 { 347 .compatible = "realtek,rtl8390-gpio", 348 }, 349 { 350 .compatible = "realtek,rtl9300-gpio", 351 .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) 352 }, 353 { 354 .compatible = "realtek,rtl9310-gpio", 355 }, 356 { 357 .compatible = "realtek,rtl9607-gpio", 358 .data = (void *)GPIO_PORTS_REVERSED, 359 }, 360 {} 361 }; 362 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); 363 364 static int realtek_gpio_probe(struct platform_device *pdev) 365 { 366 struct gpio_generic_chip_config config; 367 struct device *dev = &pdev->dev; 368 unsigned long gen_gc_flags, dev_flags; 369 struct gpio_irq_chip *girq; 370 struct realtek_gpio_ctrl *ctrl; 371 struct resource *res; 372 u32 ngpios; 373 unsigned int nr_cpus; 374 int cpu, err, irq; 375 376 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 377 if (!ctrl) 378 return -ENOMEM; 379 380 dev_flags = (uintptr_t)device_get_match_data(dev); 381 382 ngpios = REALTEK_GPIO_MAX; 383 device_property_read_u32(dev, "ngpios", &ngpios); 384 385 if (ngpios > REALTEK_GPIO_MAX) { 386 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n", 387 REALTEK_GPIO_MAX); 388 return -EINVAL; 389 } 390 391 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 392 if (IS_ERR(ctrl->base)) 393 return PTR_ERR(ctrl->base); 394 395 raw_spin_lock_init(&ctrl->lock); 396 397 if (dev_flags & GPIO_PORTS_REVERSED) { 398 gen_gc_flags = 0; 399 ctrl->bank_read = realtek_gpio_bank_read; 400 ctrl->bank_write = realtek_gpio_bank_write; 401 ctrl->line_imr_pos = realtek_gpio_line_imr_pos; 402 } else { 403 gen_gc_flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 404 ctrl->bank_read = realtek_gpio_bank_read_swapped; 405 ctrl->bank_write = realtek_gpio_bank_write_swapped; 406 ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; 407 } 408 409 config = (struct gpio_generic_chip_config) { 410 .dev = dev, 411 .sz = 4, 412 .dat = ctrl->base + REALTEK_GPIO_REG_DATA, 413 .dirout = ctrl->base + REALTEK_GPIO_REG_DIR, 414 .flags = gen_gc_flags, 415 }; 416 417 err = gpio_generic_chip_init(&ctrl->chip, &config); 418 if (err) { 419 dev_err(dev, "unable to init generic GPIO"); 420 return err; 421 } 422 423 ctrl->chip.gc.ngpio = ngpios; 424 ctrl->chip.gc.owner = THIS_MODULE; 425 426 irq = platform_get_irq_optional(pdev, 0); 427 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { 428 girq = &ctrl->chip.gc.irq; 429 gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip); 430 girq->default_type = IRQ_TYPE_NONE; 431 girq->handler = handle_bad_irq; 432 girq->parent_handler = realtek_gpio_irq_handler; 433 girq->num_parents = 1; 434 girq->parents = devm_kcalloc(dev, girq->num_parents, 435 sizeof(*girq->parents), GFP_KERNEL); 436 if (!girq->parents) 437 return -ENOMEM; 438 girq->parents[0] = irq; 439 girq->init_hw = realtek_gpio_irq_init; 440 } 441 442 cpumask_clear(&ctrl->cpu_irq_maskable); 443 444 if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) { 445 ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 446 if (IS_ERR(ctrl->cpumask_base)) 447 return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base), 448 "missing CPU IRQ mask registers"); 449 450 nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK; 451 nr_cpus = min(nr_cpus, num_present_cpus()); 452 453 for (cpu = 0; cpu < nr_cpus; cpu++) 454 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); 455 } 456 457 return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); 458 } 459 460 static struct platform_driver realtek_gpio_driver = { 461 .driver = { 462 .name = "realtek-otto-gpio", 463 .of_match_table = realtek_gpio_of_match, 464 }, 465 .probe = realtek_gpio_probe, 466 }; 467 module_platform_driver(realtek_gpio_driver); 468 469 MODULE_DESCRIPTION("Realtek Otto GPIO support"); 470 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>"); 471 MODULE_LICENSE("GPL v2"); 472