1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/gpio/driver.h> 4 #include <linux/irq.h> 5 #include <linux/minmax.h> 6 #include <linux/mod_devicetable.h> 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 #include <linux/property.h> 10 11 /* 12 * Total register block size is 0x1C for one bank of four ports (A, B, C, D). 13 * An optional second bank, with ports E, F, G, and H, may be present, starting 14 * at register offset 0x1C. 15 */ 16 17 /* 18 * Pin select: (0) "normal", (1) "dedicate peripheral" 19 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits 20 * in the peripheral registers. 21 */ 22 #define REALTEK_GPIO_REG_CNR 0x00 23 /* Clear bit (0) for input, set bit (1) for output */ 24 #define REALTEK_GPIO_REG_DIR 0x08 25 #define REALTEK_GPIO_REG_DATA 0x0C 26 /* Read bit for IRQ status, write 1 to clear IRQ */ 27 #define REALTEK_GPIO_REG_ISR 0x10 28 /* Two bits per GPIO in IMR registers */ 29 #define REALTEK_GPIO_REG_IMR 0x14 30 #define REALTEK_GPIO_REG_IMR_AB 0x14 31 #define REALTEK_GPIO_REG_IMR_CD 0x18 32 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0) 33 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1 34 #define REALTEK_GPIO_IRQ_EDGE_RISING 2 35 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3 36 37 #define REALTEK_GPIO_MAX 32 38 #define REALTEK_GPIO_PORTS_PER_BANK 4 39 40 /** 41 * realtek_gpio_ctrl - Realtek Otto GPIO driver data 42 * 43 * @gc: Associated gpio_chip instance 44 * @base: Base address of the register block for a GPIO bank 45 * @lock: Lock for accessing the IRQ registers and values 46 * @intr_mask: Mask for interrupts lines 47 * @intr_type: Interrupt type selection 48 * 49 * Because the interrupt mask register (IMR) combines the function of IRQ type 50 * selection and masking, two extra values are stored. @intr_mask is used to 51 * mask/unmask the interrupts for a GPIO port, and @intr_type is used to store 52 * the selected interrupt types. The logical AND of these values is written to 53 * IMR on changes. 54 */ 55 struct realtek_gpio_ctrl { 56 struct gpio_chip gc; 57 void __iomem *base; 58 raw_spinlock_t lock; 59 u16 intr_mask[REALTEK_GPIO_PORTS_PER_BANK]; 60 u16 intr_type[REALTEK_GPIO_PORTS_PER_BANK]; 61 }; 62 63 /* Expand with more flags as devices with other quirks are added */ 64 enum realtek_gpio_flags { 65 /* 66 * Allow disabling interrupts, for cases where the port order is 67 * unknown. This may result in a port mismatch between ISR and IMR. 68 * An interrupt would appear to come from a different line than the 69 * line the IRQ handler was assigned to, causing uncaught interrupts. 70 */ 71 GPIO_INTERRUPTS_DISABLED = BIT(0), 72 }; 73 74 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) 75 { 76 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 77 78 return container_of(gc, struct realtek_gpio_ctrl, gc); 79 } 80 81 /* 82 * Normal port order register access 83 * 84 * Port information is stored with the first port at offset 0, followed by the 85 * second, etc. Most registers store one bit per GPIO and use a u8 value per 86 * port. The two interrupt mask registers store two bits per GPIO, so use u16 87 * values. 88 */ 89 static void realtek_gpio_write_imr(struct realtek_gpio_ctrl *ctrl, 90 unsigned int port, u16 irq_type, u16 irq_mask) 91 { 92 iowrite16(irq_type & irq_mask, ctrl->base + REALTEK_GPIO_REG_IMR + 2 * port); 93 } 94 95 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, 96 unsigned int port, u8 mask) 97 { 98 iowrite8(mask, ctrl->base + REALTEK_GPIO_REG_ISR + port); 99 } 100 101 static u8 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl, unsigned int port) 102 { 103 return ioread8(ctrl->base + REALTEK_GPIO_REG_ISR + port); 104 } 105 106 /* Set the rising and falling edge mask bits for a GPIO port pin */ 107 static u16 realtek_gpio_imr_bits(unsigned int pin, u16 value) 108 { 109 return (value & REALTEK_GPIO_IMR_LINE_MASK) << 2 * pin; 110 } 111 112 static void realtek_gpio_irq_ack(struct irq_data *data) 113 { 114 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 115 irq_hw_number_t line = irqd_to_hwirq(data); 116 unsigned int port = line / 8; 117 unsigned int port_pin = line % 8; 118 119 realtek_gpio_clear_isr(ctrl, port, BIT(port_pin)); 120 } 121 122 static void realtek_gpio_irq_unmask(struct irq_data *data) 123 { 124 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 125 unsigned int line = irqd_to_hwirq(data); 126 unsigned int port = line / 8; 127 unsigned int port_pin = line % 8; 128 unsigned long flags; 129 u16 m; 130 131 raw_spin_lock_irqsave(&ctrl->lock, flags); 132 m = ctrl->intr_mask[port]; 133 m |= realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 134 ctrl->intr_mask[port] = m; 135 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 136 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 137 } 138 139 static void realtek_gpio_irq_mask(struct irq_data *data) 140 { 141 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 142 unsigned int line = irqd_to_hwirq(data); 143 unsigned int port = line / 8; 144 unsigned int port_pin = line % 8; 145 unsigned long flags; 146 u16 m; 147 148 raw_spin_lock_irqsave(&ctrl->lock, flags); 149 m = ctrl->intr_mask[port]; 150 m &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 151 ctrl->intr_mask[port] = m; 152 realtek_gpio_write_imr(ctrl, port, ctrl->intr_type[port], m); 153 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 154 } 155 156 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) 157 { 158 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 159 unsigned int line = irqd_to_hwirq(data); 160 unsigned int port = line / 8; 161 unsigned int port_pin = line % 8; 162 unsigned long flags; 163 u16 type, t; 164 165 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 166 case IRQ_TYPE_EDGE_FALLING: 167 type = REALTEK_GPIO_IRQ_EDGE_FALLING; 168 break; 169 case IRQ_TYPE_EDGE_RISING: 170 type = REALTEK_GPIO_IRQ_EDGE_RISING; 171 break; 172 case IRQ_TYPE_EDGE_BOTH: 173 type = REALTEK_GPIO_IRQ_EDGE_BOTH; 174 break; 175 default: 176 return -EINVAL; 177 } 178 179 irq_set_handler_locked(data, handle_edge_irq); 180 181 raw_spin_lock_irqsave(&ctrl->lock, flags); 182 t = ctrl->intr_type[port]; 183 t &= ~realtek_gpio_imr_bits(port_pin, REALTEK_GPIO_IMR_LINE_MASK); 184 t |= realtek_gpio_imr_bits(port_pin, type); 185 ctrl->intr_type[port] = t; 186 realtek_gpio_write_imr(ctrl, port, t, ctrl->intr_mask[port]); 187 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 188 189 return 0; 190 } 191 192 static void realtek_gpio_irq_handler(struct irq_desc *desc) 193 { 194 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 195 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 196 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 197 unsigned int lines_done; 198 unsigned int port_pin_count; 199 unsigned long status; 200 int offset; 201 202 chained_irq_enter(irq_chip, desc); 203 204 for (lines_done = 0; lines_done < gc->ngpio; lines_done += 8) { 205 status = realtek_gpio_read_isr(ctrl, lines_done / 8); 206 port_pin_count = min(gc->ngpio - lines_done, 8U); 207 for_each_set_bit(offset, &status, port_pin_count) 208 generic_handle_domain_irq(gc->irq.domain, offset + lines_done); 209 } 210 211 chained_irq_exit(irq_chip, desc); 212 } 213 214 static int realtek_gpio_irq_init(struct gpio_chip *gc) 215 { 216 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 217 unsigned int port; 218 219 for (port = 0; (port * 8) < gc->ngpio; port++) { 220 realtek_gpio_write_imr(ctrl, port, 0, 0); 221 realtek_gpio_clear_isr(ctrl, port, GENMASK(7, 0)); 222 } 223 224 return 0; 225 } 226 227 static struct irq_chip realtek_gpio_irq_chip = { 228 .name = "realtek-otto-gpio", 229 .irq_ack = realtek_gpio_irq_ack, 230 .irq_mask = realtek_gpio_irq_mask, 231 .irq_unmask = realtek_gpio_irq_unmask, 232 .irq_set_type = realtek_gpio_irq_set_type, 233 }; 234 235 static const struct of_device_id realtek_gpio_of_match[] = { 236 { 237 .compatible = "realtek,otto-gpio", 238 .data = (void *)GPIO_INTERRUPTS_DISABLED, 239 }, 240 { 241 .compatible = "realtek,rtl8380-gpio", 242 }, 243 { 244 .compatible = "realtek,rtl8390-gpio", 245 }, 246 {} 247 }; 248 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); 249 250 static int realtek_gpio_probe(struct platform_device *pdev) 251 { 252 struct device *dev = &pdev->dev; 253 unsigned int dev_flags; 254 struct gpio_irq_chip *girq; 255 struct realtek_gpio_ctrl *ctrl; 256 u32 ngpios; 257 int err, irq; 258 259 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 260 if (!ctrl) 261 return -ENOMEM; 262 263 dev_flags = (unsigned int) device_get_match_data(dev); 264 265 ngpios = REALTEK_GPIO_MAX; 266 device_property_read_u32(dev, "ngpios", &ngpios); 267 268 if (ngpios > REALTEK_GPIO_MAX) { 269 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n", 270 REALTEK_GPIO_MAX); 271 return -EINVAL; 272 } 273 274 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 275 if (IS_ERR(ctrl->base)) 276 return PTR_ERR(ctrl->base); 277 278 raw_spin_lock_init(&ctrl->lock); 279 280 err = bgpio_init(&ctrl->gc, dev, 4, 281 ctrl->base + REALTEK_GPIO_REG_DATA, NULL, NULL, 282 ctrl->base + REALTEK_GPIO_REG_DIR, NULL, 283 BGPIOF_BIG_ENDIAN_BYTE_ORDER); 284 if (err) { 285 dev_err(dev, "unable to init generic GPIO"); 286 return err; 287 } 288 289 ctrl->gc.ngpio = ngpios; 290 ctrl->gc.owner = THIS_MODULE; 291 292 irq = platform_get_irq_optional(pdev, 0); 293 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { 294 girq = &ctrl->gc.irq; 295 girq->chip = &realtek_gpio_irq_chip; 296 girq->default_type = IRQ_TYPE_NONE; 297 girq->handler = handle_bad_irq; 298 girq->parent_handler = realtek_gpio_irq_handler; 299 girq->num_parents = 1; 300 girq->parents = devm_kcalloc(dev, girq->num_parents, 301 sizeof(*girq->parents), GFP_KERNEL); 302 if (!girq->parents) 303 return -ENOMEM; 304 girq->parents[0] = irq; 305 girq->init_hw = realtek_gpio_irq_init; 306 } 307 308 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 309 } 310 311 static struct platform_driver realtek_gpio_driver = { 312 .driver = { 313 .name = "realtek-otto-gpio", 314 .of_match_table = realtek_gpio_of_match, 315 }, 316 .probe = realtek_gpio_probe, 317 }; 318 module_platform_driver(realtek_gpio_driver); 319 320 MODULE_DESCRIPTION("Realtek Otto GPIO support"); 321 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>"); 322 MODULE_LICENSE("GPL v2"); 323