1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/cpumask.h> 4 #include <linux/gpio/driver.h> 5 #include <linux/gpio/generic.h> 6 #include <linux/irq.h> 7 #include <linux/minmax.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/property.h> 12 13 /* 14 * Total register block size is 0x1C for one bank of four ports (A, B, C, D). 15 * An optional second bank, with ports E, F, G, and H, may be present, starting 16 * at register offset 0x1C. 17 */ 18 19 /* 20 * Pin select: (0) "normal", (1) "dedicate peripheral" 21 * Not used on RTL8380/RTL8390, peripheral selection is managed by control bits 22 * in the peripheral registers. 23 */ 24 #define REALTEK_GPIO_REG_CNR 0x00 25 /* Clear bit (0) for input, set bit (1) for output */ 26 #define REALTEK_GPIO_REG_DIR 0x08 27 #define REALTEK_GPIO_REG_DATA 0x0C 28 /* Read bit for IRQ status, write 1 to clear IRQ */ 29 #define REALTEK_GPIO_REG_ISR 0x10 30 /* Two bits per GPIO in IMR registers */ 31 #define REALTEK_GPIO_REG_IMR 0x14 32 #define REALTEK_GPIO_REG_IMR_AB 0x14 33 #define REALTEK_GPIO_REG_IMR_CD 0x18 34 #define REALTEK_GPIO_IMR_LINE_MASK GENMASK(1, 0) 35 #define REALTEK_GPIO_IRQ_EDGE_FALLING 1 36 #define REALTEK_GPIO_IRQ_EDGE_RISING 2 37 #define REALTEK_GPIO_IRQ_EDGE_BOTH 3 38 39 #define REALTEK_GPIO_MAX 32 40 #define REALTEK_GPIO_PORTS_PER_BANK 4 41 42 /** 43 * realtek_gpio_ctrl - Realtek Otto GPIO driver data 44 * 45 * @chip: Associated gpio_generic_chip instance 46 * @base: Base address of the register block for a GPIO bank 47 * @lock: Lock for accessing the IRQ registers and values 48 * @intr_mask: Mask for interrupts lines 49 * @intr_type: Interrupt type selection 50 * @bank_read: Read a bank setting as a single 32-bit value 51 * @bank_write: Write a bank setting as a single 32-bit value 52 * @imr_line_pos: Bit shift of an IRQ line's IMR value. 53 * 54 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed 55 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign) 56 * a value from (to) these registers. The IMR register consists of four 16-bit 57 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the 58 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than 59 * 32 overflow into the second register. 60 * 61 * Because the interrupt mask register (IMR) combines the function of IRQ type 62 * selection and masking, two extra values are stored. @intr_mask is used to 63 * mask/unmask the interrupts for a GPIO line, and @intr_type is used to store 64 * the selected interrupt types. The logical AND of these values is written to 65 * IMR on changes. 66 */ 67 struct realtek_gpio_ctrl { 68 struct gpio_generic_chip chip; 69 void __iomem *base; 70 void __iomem *cpumask_base; 71 struct cpumask cpu_irq_maskable; 72 raw_spinlock_t lock; 73 u8 intr_mask[REALTEK_GPIO_MAX]; 74 u8 intr_type[REALTEK_GPIO_MAX]; 75 u32 (*bank_read)(void __iomem *reg); 76 void (*bank_write)(void __iomem *reg, u32 value); 77 unsigned int (*line_imr_pos)(unsigned int line); 78 }; 79 80 /* Expand with more flags as devices with other quirks are added */ 81 enum realtek_gpio_flags { 82 /* 83 * Allow disabling interrupts, for cases where the port order is 84 * unknown. This may result in a port mismatch between ISR and IMR. 85 * An interrupt would appear to come from a different line than the 86 * line the IRQ handler was assigned to, causing uncaught interrupts. 87 */ 88 GPIO_INTERRUPTS_DISABLED = BIT(0), 89 /* 90 * Port order is reversed, meaning DCBA register layout for 1-bit 91 * fields, and [BA, DC] for 2-bit fields. 92 */ 93 GPIO_PORTS_REVERSED = BIT(1), 94 /* 95 * Interrupts can be enabled per cpu. This requires a secondary IO 96 * range, where the per-cpu enable masks are located. 97 */ 98 GPIO_INTERRUPTS_PER_CPU = BIT(2), 99 }; 100 101 static struct realtek_gpio_ctrl *irq_data_to_ctrl(struct irq_data *data) 102 { 103 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 104 105 return container_of(to_gpio_generic_chip(gc), struct realtek_gpio_ctrl, chip); 106 } 107 108 /* 109 * Normal port order register access 110 * 111 * Port information is stored with the first port at offset 0, followed by the 112 * second, etc. Most registers store one bit per GPIO and use a u8 value per 113 * port. The two interrupt mask registers store two bits per GPIO, so use u16 114 * values. 115 */ 116 static u32 realtek_gpio_bank_read_swapped(void __iomem *reg) 117 { 118 return ioread32be(reg); 119 } 120 121 static void realtek_gpio_bank_write_swapped(void __iomem *reg, u32 value) 122 { 123 iowrite32be(value, reg); 124 } 125 126 static unsigned int realtek_gpio_line_imr_pos_swapped(unsigned int line) 127 { 128 unsigned int port_pin = line % 8; 129 unsigned int port = line / 8; 130 131 return 2 * (8 * (port ^ 1) + port_pin); 132 } 133 134 /* 135 * Reversed port order register access 136 * 137 * For registers with one bit per GPIO, all ports are stored as u8-s in one 138 * register in reversed order. The two interrupt mask registers store two bits 139 * per GPIO, so use u16 values. The first register contains ports 1 and 0, the 140 * second ports 3 and 2. 141 */ 142 static u32 realtek_gpio_bank_read(void __iomem *reg) 143 { 144 return ioread32(reg); 145 } 146 147 static void realtek_gpio_bank_write(void __iomem *reg, u32 value) 148 { 149 iowrite32(value, reg); 150 } 151 152 static unsigned int realtek_gpio_line_imr_pos(unsigned int line) 153 { 154 return 2 * line; 155 } 156 157 static void realtek_gpio_clear_isr(struct realtek_gpio_ctrl *ctrl, u32 mask) 158 { 159 ctrl->bank_write(ctrl->base + REALTEK_GPIO_REG_ISR, mask); 160 } 161 162 static u32 realtek_gpio_read_isr(struct realtek_gpio_ctrl *ctrl) 163 { 164 return ctrl->bank_read(ctrl->base + REALTEK_GPIO_REG_ISR); 165 } 166 167 /* Set the rising and falling edge mask bits for a GPIO pin */ 168 static void realtek_gpio_update_line_imr(struct realtek_gpio_ctrl *ctrl, unsigned int line) 169 { 170 void __iomem *reg = ctrl->base + REALTEK_GPIO_REG_IMR; 171 unsigned int line_shift = ctrl->line_imr_pos(line); 172 unsigned int shift = line_shift % 32; 173 u32 irq_type = ctrl->intr_type[line]; 174 u32 irq_mask = ctrl->intr_mask[line]; 175 u32 reg_val; 176 177 reg += 4 * (line_shift / 32); 178 reg_val = ioread32(reg); 179 reg_val &= ~(REALTEK_GPIO_IMR_LINE_MASK << shift); 180 reg_val |= (irq_type & irq_mask & REALTEK_GPIO_IMR_LINE_MASK) << shift; 181 iowrite32(reg_val, reg); 182 } 183 184 static void realtek_gpio_irq_ack(struct irq_data *data) 185 { 186 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 187 irq_hw_number_t line = irqd_to_hwirq(data); 188 189 realtek_gpio_clear_isr(ctrl, BIT(line)); 190 } 191 192 static void realtek_gpio_irq_unmask(struct irq_data *data) 193 { 194 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 195 unsigned int line = irqd_to_hwirq(data); 196 unsigned long flags; 197 198 gpiochip_enable_irq(&ctrl->chip.gc, line); 199 200 raw_spin_lock_irqsave(&ctrl->lock, flags); 201 ctrl->intr_mask[line] = REALTEK_GPIO_IMR_LINE_MASK; 202 realtek_gpio_update_line_imr(ctrl, line); 203 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 204 } 205 206 static void realtek_gpio_irq_mask(struct irq_data *data) 207 { 208 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 209 unsigned int line = irqd_to_hwirq(data); 210 unsigned long flags; 211 212 raw_spin_lock_irqsave(&ctrl->lock, flags); 213 ctrl->intr_mask[line] = 0; 214 realtek_gpio_update_line_imr(ctrl, line); 215 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 216 217 gpiochip_disable_irq(&ctrl->chip.gc, line); 218 } 219 220 static int realtek_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) 221 { 222 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 223 unsigned int line = irqd_to_hwirq(data); 224 unsigned long flags; 225 u8 type; 226 227 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 228 case IRQ_TYPE_EDGE_FALLING: 229 type = REALTEK_GPIO_IRQ_EDGE_FALLING; 230 break; 231 case IRQ_TYPE_EDGE_RISING: 232 type = REALTEK_GPIO_IRQ_EDGE_RISING; 233 break; 234 case IRQ_TYPE_EDGE_BOTH: 235 type = REALTEK_GPIO_IRQ_EDGE_BOTH; 236 break; 237 default: 238 return -EINVAL; 239 } 240 241 irq_set_handler_locked(data, handle_edge_irq); 242 243 raw_spin_lock_irqsave(&ctrl->lock, flags); 244 ctrl->intr_type[line] = type; 245 realtek_gpio_update_line_imr(ctrl, line); 246 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 247 248 return 0; 249 } 250 251 static void realtek_gpio_irq_handler(struct irq_desc *desc) 252 { 253 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 254 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 255 struct irq_chip *irq_chip = irq_desc_get_chip(desc); 256 unsigned long status; 257 int offset; 258 259 chained_irq_enter(irq_chip, desc); 260 261 status = realtek_gpio_read_isr(ctrl); 262 for_each_set_bit(offset, &status, gc->ngpio) 263 generic_handle_domain_irq(gc->irq.domain, offset); 264 265 chained_irq_exit(irq_chip, desc); 266 } 267 268 static inline void __iomem *realtek_gpio_irq_cpu_mask(struct realtek_gpio_ctrl *ctrl, int cpu) 269 { 270 return ctrl->cpumask_base + REALTEK_GPIO_PORTS_PER_BANK * cpu; 271 } 272 273 static int realtek_gpio_irq_set_affinity(struct irq_data *data, 274 const struct cpumask *dest, bool force) 275 { 276 struct realtek_gpio_ctrl *ctrl = irq_data_to_ctrl(data); 277 unsigned int line = irqd_to_hwirq(data); 278 void __iomem *irq_cpu_mask; 279 unsigned long flags; 280 int cpu; 281 u32 v; 282 283 if (!ctrl->cpumask_base) 284 return -ENXIO; 285 286 raw_spin_lock_irqsave(&ctrl->lock, flags); 287 288 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) { 289 irq_cpu_mask = realtek_gpio_irq_cpu_mask(ctrl, cpu); 290 v = ctrl->bank_read(irq_cpu_mask); 291 292 if (cpumask_test_cpu(cpu, dest)) 293 v |= BIT(line); 294 else 295 v &= ~BIT(line); 296 297 ctrl->bank_write(irq_cpu_mask, v); 298 } 299 300 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 301 302 irq_data_update_effective_affinity(data, dest); 303 304 return 0; 305 } 306 307 static int realtek_gpio_irq_init(struct gpio_chip *gc) 308 { 309 struct realtek_gpio_ctrl *ctrl = gpiochip_get_data(gc); 310 u32 mask_all = GENMASK(gc->ngpio - 1, 0); 311 unsigned int line; 312 int cpu; 313 314 for (line = 0; line < gc->ngpio; line++) 315 realtek_gpio_update_line_imr(ctrl, line); 316 317 realtek_gpio_clear_isr(ctrl, mask_all); 318 319 for_each_cpu(cpu, &ctrl->cpu_irq_maskable) 320 ctrl->bank_write(realtek_gpio_irq_cpu_mask(ctrl, cpu), mask_all); 321 322 return 0; 323 } 324 325 static const struct irq_chip realtek_gpio_irq_chip = { 326 .name = "realtek-otto-gpio", 327 .irq_ack = realtek_gpio_irq_ack, 328 .irq_mask = realtek_gpio_irq_mask, 329 .irq_unmask = realtek_gpio_irq_unmask, 330 .irq_set_type = realtek_gpio_irq_set_type, 331 .irq_set_affinity = realtek_gpio_irq_set_affinity, 332 .flags = IRQCHIP_IMMUTABLE, 333 GPIOCHIP_IRQ_RESOURCE_HELPERS, 334 }; 335 336 static const struct of_device_id realtek_gpio_of_match[] = { 337 { 338 .compatible = "realtek,otto-gpio", 339 .data = (void *)GPIO_INTERRUPTS_DISABLED, 340 }, 341 { 342 .compatible = "realtek,rtl8380-gpio", 343 }, 344 { 345 .compatible = "realtek,rtl8390-gpio", 346 }, 347 { 348 .compatible = "realtek,rtl9300-gpio", 349 .data = (void *)(GPIO_PORTS_REVERSED | GPIO_INTERRUPTS_PER_CPU) 350 }, 351 { 352 .compatible = "realtek,rtl9310-gpio", 353 }, 354 {} 355 }; 356 MODULE_DEVICE_TABLE(of, realtek_gpio_of_match); 357 358 static int realtek_gpio_probe(struct platform_device *pdev) 359 { 360 struct gpio_generic_chip_config config; 361 struct device *dev = &pdev->dev; 362 unsigned long gen_gc_flags; 363 unsigned int dev_flags; 364 struct gpio_irq_chip *girq; 365 struct realtek_gpio_ctrl *ctrl; 366 struct resource *res; 367 u32 ngpios; 368 unsigned int nr_cpus; 369 int cpu, err, irq; 370 371 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 372 if (!ctrl) 373 return -ENOMEM; 374 375 dev_flags = (unsigned int) device_get_match_data(dev); 376 377 ngpios = REALTEK_GPIO_MAX; 378 device_property_read_u32(dev, "ngpios", &ngpios); 379 380 if (ngpios > REALTEK_GPIO_MAX) { 381 dev_err(&pdev->dev, "invalid ngpios (max. %d)\n", 382 REALTEK_GPIO_MAX); 383 return -EINVAL; 384 } 385 386 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 387 if (IS_ERR(ctrl->base)) 388 return PTR_ERR(ctrl->base); 389 390 raw_spin_lock_init(&ctrl->lock); 391 392 if (dev_flags & GPIO_PORTS_REVERSED) { 393 gen_gc_flags = 0; 394 ctrl->bank_read = realtek_gpio_bank_read; 395 ctrl->bank_write = realtek_gpio_bank_write; 396 ctrl->line_imr_pos = realtek_gpio_line_imr_pos; 397 } else { 398 gen_gc_flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 399 ctrl->bank_read = realtek_gpio_bank_read_swapped; 400 ctrl->bank_write = realtek_gpio_bank_write_swapped; 401 ctrl->line_imr_pos = realtek_gpio_line_imr_pos_swapped; 402 } 403 404 config = (struct gpio_generic_chip_config) { 405 .dev = dev, 406 .sz = 4, 407 .dat = ctrl->base + REALTEK_GPIO_REG_DATA, 408 .dirout = ctrl->base + REALTEK_GPIO_REG_DIR, 409 .flags = gen_gc_flags, 410 }; 411 412 err = gpio_generic_chip_init(&ctrl->chip, &config); 413 if (err) { 414 dev_err(dev, "unable to init generic GPIO"); 415 return err; 416 } 417 418 ctrl->chip.gc.ngpio = ngpios; 419 ctrl->chip.gc.owner = THIS_MODULE; 420 421 irq = platform_get_irq_optional(pdev, 0); 422 if (!(dev_flags & GPIO_INTERRUPTS_DISABLED) && irq > 0) { 423 girq = &ctrl->chip.gc.irq; 424 gpio_irq_chip_set_chip(girq, &realtek_gpio_irq_chip); 425 girq->default_type = IRQ_TYPE_NONE; 426 girq->handler = handle_bad_irq; 427 girq->parent_handler = realtek_gpio_irq_handler; 428 girq->num_parents = 1; 429 girq->parents = devm_kcalloc(dev, girq->num_parents, 430 sizeof(*girq->parents), GFP_KERNEL); 431 if (!girq->parents) 432 return -ENOMEM; 433 girq->parents[0] = irq; 434 girq->init_hw = realtek_gpio_irq_init; 435 } 436 437 cpumask_clear(&ctrl->cpu_irq_maskable); 438 439 if ((dev_flags & GPIO_INTERRUPTS_PER_CPU) && irq > 0) { 440 ctrl->cpumask_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res); 441 if (IS_ERR(ctrl->cpumask_base)) 442 return dev_err_probe(dev, PTR_ERR(ctrl->cpumask_base), 443 "missing CPU IRQ mask registers"); 444 445 nr_cpus = resource_size(res) / REALTEK_GPIO_PORTS_PER_BANK; 446 nr_cpus = min(nr_cpus, num_present_cpus()); 447 448 for (cpu = 0; cpu < nr_cpus; cpu++) 449 cpumask_set_cpu(cpu, &ctrl->cpu_irq_maskable); 450 } 451 452 return devm_gpiochip_add_data(dev, &ctrl->chip.gc, ctrl); 453 } 454 455 static struct platform_driver realtek_gpio_driver = { 456 .driver = { 457 .name = "realtek-otto-gpio", 458 .of_match_table = realtek_gpio_of_match, 459 }, 460 .probe = realtek_gpio_probe, 461 }; 462 module_platform_driver(realtek_gpio_driver); 463 464 MODULE_DESCRIPTION("Realtek Otto GPIO support"); 465 MODULE_AUTHOR("Sander Vanheule <sander@svanheule.net>"); 466 MODULE_LICENSE("GPL v2"); 467