xref: /linux/drivers/gpio/gpio-rcar.c (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  * Renesas R-Car GPIO Support
3  *
4  *  Copyright (C) 2014 Renesas Electronics Corporation
5  *  Copyright (C) 2013 Magnus Damm
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
32 
33 struct gpio_rcar_priv {
34 	void __iomem *base;
35 	spinlock_t lock;
36 	struct platform_device *pdev;
37 	struct gpio_chip gpio_chip;
38 	struct irq_chip irq_chip;
39 	struct clk *clk;
40 	unsigned int irq_parent;
41 	bool has_both_edge_trigger;
42 	bool needs_clk;
43 };
44 
45 #define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04	/* General Input/Output Switching Register */
47 #define OUTDT 0x08	/* General Output Register */
48 #define INDT 0x0c	/* General Input Register */
49 #define INTDT 0x10	/* Interrupt Display Register */
50 #define INTCLR 0x14	/* Interrupt Clear Register */
51 #define INTMSK 0x18	/* Interrupt Mask Register */
52 #define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
53 #define POSNEG 0x20	/* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24	/* Edge/level Select Register */
55 #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
57 
58 #define RCAR_MAX_GPIO_PER_BANK		32
59 
60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61 {
62 	return ioread32(p->base + offs);
63 }
64 
65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 				   u32 value)
67 {
68 	iowrite32(value, p->base + offs);
69 }
70 
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 				 int bit, bool value)
73 {
74 	u32 tmp = gpio_rcar_read(p, offs);
75 
76 	if (value)
77 		tmp |= BIT(bit);
78 	else
79 		tmp &= ~BIT(bit);
80 
81 	gpio_rcar_write(p, offs, tmp);
82 }
83 
84 static void gpio_rcar_irq_disable(struct irq_data *d)
85 {
86 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88 
89 	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90 }
91 
92 static void gpio_rcar_irq_enable(struct irq_data *d)
93 {
94 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96 
97 	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98 }
99 
100 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 						  unsigned int hwirq,
102 						  bool active_high_rising_edge,
103 						  bool level_trigger,
104 						  bool both)
105 {
106 	unsigned long flags;
107 
108 	/* follow steps in the GPIO documentation for
109 	 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 	 * "Setting Level-Sensitive Interrupt Input Mode"
111 	 */
112 
113 	spin_lock_irqsave(&p->lock, flags);
114 
115 	/* Configure postive or negative logic in POSNEG */
116 	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117 
118 	/* Configure edge or level trigger in EDGLEVEL */
119 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120 
121 	/* Select one edge or both edges in BOTHEDGE */
122 	if (p->has_both_edge_trigger)
123 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124 
125 	/* Select "Interrupt Input Mode" in IOINTSEL */
126 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127 
128 	/* Write INTCLR in case of edge trigger */
129 	if (!level_trigger)
130 		gpio_rcar_write(p, INTCLR, BIT(hwirq));
131 
132 	spin_unlock_irqrestore(&p->lock, flags);
133 }
134 
135 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136 {
137 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
139 	unsigned int hwirq = irqd_to_hwirq(d);
140 
141 	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142 
143 	switch (type & IRQ_TYPE_SENSE_MASK) {
144 	case IRQ_TYPE_LEVEL_HIGH:
145 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 						      false);
147 		break;
148 	case IRQ_TYPE_LEVEL_LOW:
149 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 						      false);
151 		break;
152 	case IRQ_TYPE_EDGE_RISING:
153 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 						      false);
155 		break;
156 	case IRQ_TYPE_EDGE_FALLING:
157 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 						      false);
159 		break;
160 	case IRQ_TYPE_EDGE_BOTH:
161 		if (!p->has_both_edge_trigger)
162 			return -EINVAL;
163 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 						      true);
165 		break;
166 	default:
167 		return -EINVAL;
168 	}
169 	return 0;
170 }
171 
172 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173 {
174 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
176 	int error;
177 
178 	if (p->irq_parent) {
179 		error = irq_set_irq_wake(p->irq_parent, on);
180 		if (error) {
181 			dev_dbg(&p->pdev->dev,
182 				"irq %u doesn't support irq_set_wake\n",
183 				p->irq_parent);
184 			p->irq_parent = 0;
185 		}
186 	}
187 
188 	if (!p->clk)
189 		return 0;
190 
191 	if (on)
192 		clk_enable(p->clk);
193 	else
194 		clk_disable(p->clk);
195 
196 	return 0;
197 }
198 
199 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200 {
201 	struct gpio_rcar_priv *p = dev_id;
202 	u32 pending;
203 	unsigned int offset, irqs_handled = 0;
204 
205 	while ((pending = gpio_rcar_read(p, INTDT) &
206 			  gpio_rcar_read(p, INTMSK))) {
207 		offset = __ffs(pending);
208 		gpio_rcar_write(p, INTCLR, BIT(offset));
209 		generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
210 						    offset));
211 		irqs_handled++;
212 	}
213 
214 	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215 }
216 
217 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 						       unsigned int gpio,
219 						       bool output)
220 {
221 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 	unsigned long flags;
223 
224 	/* follow steps in the GPIO documentation for
225 	 * "Setting General Output Mode" and
226 	 * "Setting General Input Mode"
227 	 */
228 
229 	spin_lock_irqsave(&p->lock, flags);
230 
231 	/* Configure postive logic in POSNEG */
232 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233 
234 	/* Select "General Input/Output Mode" in IOINTSEL */
235 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236 
237 	/* Select Input Mode or Output Mode in INOUTSEL */
238 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239 
240 	spin_unlock_irqrestore(&p->lock, flags);
241 }
242 
243 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
244 {
245 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
246 	int error;
247 
248 	error = pm_runtime_get_sync(&p->pdev->dev);
249 	if (error < 0)
250 		return error;
251 
252 	error = pinctrl_request_gpio(chip->base + offset);
253 	if (error)
254 		pm_runtime_put(&p->pdev->dev);
255 
256 	return error;
257 }
258 
259 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
260 {
261 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
262 
263 	pinctrl_free_gpio(chip->base + offset);
264 
265 	/*
266 	 * Set the GPIO as an input to ensure that the next GPIO request won't
267 	 * drive the GPIO pin as an output.
268 	 */
269 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
270 
271 	pm_runtime_put(&p->pdev->dev);
272 }
273 
274 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
275 {
276 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
277 	return 0;
278 }
279 
280 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
281 {
282 	u32 bit = BIT(offset);
283 
284 	/* testing on r8a7790 shows that INDT does not show correct pin state
285 	 * when configured as output, so use OUTDT in case of output pins */
286 	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
287 		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
288 	else
289 		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
290 }
291 
292 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
293 {
294 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
295 	unsigned long flags;
296 
297 	spin_lock_irqsave(&p->lock, flags);
298 	gpio_rcar_modify_bit(p, OUTDT, offset, value);
299 	spin_unlock_irqrestore(&p->lock, flags);
300 }
301 
302 static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
303 				   unsigned long *bits)
304 {
305 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
306 	unsigned long flags;
307 	u32 val, bankmask;
308 
309 	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
310 	if (!bankmask)
311 		return;
312 
313 	spin_lock_irqsave(&p->lock, flags);
314 	val = gpio_rcar_read(p, OUTDT);
315 	val &= ~bankmask;
316 	val |= (bankmask & bits[0]);
317 	gpio_rcar_write(p, OUTDT, val);
318 	spin_unlock_irqrestore(&p->lock, flags);
319 }
320 
321 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
322 				      int value)
323 {
324 	/* write GPIO value to output before selecting output mode of pin */
325 	gpio_rcar_set(chip, offset, value);
326 	gpio_rcar_config_general_input_output_mode(chip, offset, true);
327 	return 0;
328 }
329 
330 struct gpio_rcar_info {
331 	bool has_both_edge_trigger;
332 	bool needs_clk;
333 };
334 
335 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
336 	.has_both_edge_trigger = false,
337 	.needs_clk = false,
338 };
339 
340 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
341 	.has_both_edge_trigger = true,
342 	.needs_clk = true,
343 };
344 
345 static const struct of_device_id gpio_rcar_of_table[] = {
346 	{
347 		.compatible = "renesas,gpio-r8a7790",
348 		.data = &gpio_rcar_info_gen2,
349 	}, {
350 		.compatible = "renesas,gpio-r8a7791",
351 		.data = &gpio_rcar_info_gen2,
352 	}, {
353 		.compatible = "renesas,gpio-r8a7792",
354 		.data = &gpio_rcar_info_gen2,
355 	}, {
356 		.compatible = "renesas,gpio-r8a7793",
357 		.data = &gpio_rcar_info_gen2,
358 	}, {
359 		.compatible = "renesas,gpio-r8a7794",
360 		.data = &gpio_rcar_info_gen2,
361 	}, {
362 		.compatible = "renesas,gpio-r8a7795",
363 		/* Gen3 GPIO is identical to Gen2. */
364 		.data = &gpio_rcar_info_gen2,
365 	}, {
366 		.compatible = "renesas,gpio-r8a7796",
367 		/* Gen3 GPIO is identical to Gen2. */
368 		.data = &gpio_rcar_info_gen2,
369 	}, {
370 		.compatible = "renesas,gpio-rcar",
371 		.data = &gpio_rcar_info_gen1,
372 	}, {
373 		/* Terminator */
374 	},
375 };
376 
377 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
378 
379 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
380 {
381 	struct device_node *np = p->pdev->dev.of_node;
382 	const struct of_device_id *match;
383 	const struct gpio_rcar_info *info;
384 	struct of_phandle_args args;
385 	int ret;
386 
387 	match = of_match_node(gpio_rcar_of_table, np);
388 	if (!match)
389 		return -EINVAL;
390 
391 	info = match->data;
392 
393 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
394 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
395 	p->has_both_edge_trigger = info->has_both_edge_trigger;
396 	p->needs_clk = info->needs_clk;
397 
398 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
399 		dev_warn(&p->pdev->dev,
400 			 "Invalid number of gpio lines %u, using %u\n", *npins,
401 			 RCAR_MAX_GPIO_PER_BANK);
402 		*npins = RCAR_MAX_GPIO_PER_BANK;
403 	}
404 
405 	return 0;
406 }
407 
408 static int gpio_rcar_probe(struct platform_device *pdev)
409 {
410 	struct gpio_rcar_priv *p;
411 	struct resource *io, *irq;
412 	struct gpio_chip *gpio_chip;
413 	struct irq_chip *irq_chip;
414 	struct device *dev = &pdev->dev;
415 	const char *name = dev_name(dev);
416 	unsigned int npins;
417 	int ret;
418 
419 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
420 	if (!p)
421 		return -ENOMEM;
422 
423 	p->pdev = pdev;
424 	spin_lock_init(&p->lock);
425 
426 	/* Get device configuration from DT node */
427 	ret = gpio_rcar_parse_dt(p, &npins);
428 	if (ret < 0)
429 		return ret;
430 
431 	platform_set_drvdata(pdev, p);
432 
433 	p->clk = devm_clk_get(dev, NULL);
434 	if (IS_ERR(p->clk)) {
435 		if (p->needs_clk) {
436 			dev_err(dev, "unable to get clock\n");
437 			ret = PTR_ERR(p->clk);
438 			goto err0;
439 		}
440 		p->clk = NULL;
441 	}
442 
443 	pm_runtime_enable(dev);
444 
445 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
446 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
447 
448 	if (!io || !irq) {
449 		dev_err(dev, "missing IRQ or IOMEM\n");
450 		ret = -EINVAL;
451 		goto err0;
452 	}
453 
454 	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
455 	if (!p->base) {
456 		dev_err(dev, "failed to remap I/O memory\n");
457 		ret = -ENXIO;
458 		goto err0;
459 	}
460 
461 	gpio_chip = &p->gpio_chip;
462 	gpio_chip->request = gpio_rcar_request;
463 	gpio_chip->free = gpio_rcar_free;
464 	gpio_chip->direction_input = gpio_rcar_direction_input;
465 	gpio_chip->get = gpio_rcar_get;
466 	gpio_chip->direction_output = gpio_rcar_direction_output;
467 	gpio_chip->set = gpio_rcar_set;
468 	gpio_chip->set_multiple = gpio_rcar_set_multiple;
469 	gpio_chip->label = name;
470 	gpio_chip->parent = dev;
471 	gpio_chip->owner = THIS_MODULE;
472 	gpio_chip->base = -1;
473 	gpio_chip->ngpio = npins;
474 
475 	irq_chip = &p->irq_chip;
476 	irq_chip->name = name;
477 	irq_chip->parent_device = dev;
478 	irq_chip->irq_mask = gpio_rcar_irq_disable;
479 	irq_chip->irq_unmask = gpio_rcar_irq_enable;
480 	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
481 	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
482 	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
483 
484 	ret = gpiochip_add_data(gpio_chip, p);
485 	if (ret) {
486 		dev_err(dev, "failed to add GPIO controller\n");
487 		goto err0;
488 	}
489 
490 	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
491 				   IRQ_TYPE_NONE);
492 	if (ret) {
493 		dev_err(dev, "cannot add irqchip\n");
494 		goto err1;
495 	}
496 
497 	p->irq_parent = irq->start;
498 	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
499 			     IRQF_SHARED, name, p)) {
500 		dev_err(dev, "failed to request IRQ\n");
501 		ret = -ENOENT;
502 		goto err1;
503 	}
504 
505 	dev_info(dev, "driving %d GPIOs\n", npins);
506 
507 	return 0;
508 
509 err1:
510 	gpiochip_remove(gpio_chip);
511 err0:
512 	pm_runtime_disable(dev);
513 	return ret;
514 }
515 
516 static int gpio_rcar_remove(struct platform_device *pdev)
517 {
518 	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
519 
520 	gpiochip_remove(&p->gpio_chip);
521 
522 	pm_runtime_disable(&pdev->dev);
523 	return 0;
524 }
525 
526 static struct platform_driver gpio_rcar_device_driver = {
527 	.probe		= gpio_rcar_probe,
528 	.remove		= gpio_rcar_remove,
529 	.driver		= {
530 		.name	= "gpio_rcar",
531 		.of_match_table = of_match_ptr(gpio_rcar_of_table),
532 	}
533 };
534 
535 module_platform_driver(gpio_rcar_device_driver);
536 
537 MODULE_AUTHOR("Magnus Damm");
538 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
539 MODULE_LICENSE("GPL v2");
540