1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas R-Car GPIO Support 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2013 Magnus Damm 7 */ 8 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/spinlock.h> 22 #include <linux/slab.h> 23 24 struct gpio_rcar_bank_info { 25 u32 iointsel; 26 u32 inoutsel; 27 u32 outdt; 28 u32 posneg; 29 u32 edglevel; 30 u32 bothedge; 31 u32 intmsk; 32 }; 33 34 struct gpio_rcar_info { 35 bool has_outdtsel; 36 bool has_both_edge_trigger; 37 bool has_always_in; 38 bool has_inen; 39 }; 40 41 struct gpio_rcar_priv { 42 void __iomem *base; 43 raw_spinlock_t lock; 44 struct device *dev; 45 struct gpio_chip gpio_chip; 46 unsigned int irq_parent; 47 atomic_t wakeup_path; 48 struct gpio_rcar_info info; 49 struct gpio_rcar_bank_info bank_info; 50 }; 51 52 #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ 53 #define INOUTSEL 0x04 /* General Input/Output Switching Register */ 54 #define OUTDT 0x08 /* General Output Register */ 55 #define INDT 0x0c /* General Input Register */ 56 #define INTDT 0x10 /* Interrupt Display Register */ 57 #define INTCLR 0x14 /* Interrupt Clear Register */ 58 #define INTMSK 0x18 /* Interrupt Mask Register */ 59 #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ 60 #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ 61 #define EDGLEVEL 0x24 /* Edge/level Select Register */ 62 #define OUTDTSEL 0x40 /* Output Data Select Register */ 63 #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ 64 #define INEN 0x50 /* General Input Enable Register */ 65 66 #define RCAR_MAX_GPIO_PER_BANK 32 67 68 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) 69 { 70 return ioread32(p->base + offs); 71 } 72 73 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, 74 u32 value) 75 { 76 iowrite32(value, p->base + offs); 77 } 78 79 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, 80 int bit, bool value) 81 { 82 u32 tmp = gpio_rcar_read(p, offs); 83 84 if (value) 85 tmp |= BIT(bit); 86 else 87 tmp &= ~BIT(bit); 88 89 gpio_rcar_write(p, offs, tmp); 90 } 91 92 static void gpio_rcar_irq_disable(struct irq_data *d) 93 { 94 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 95 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 96 irq_hw_number_t hwirq = irqd_to_hwirq(d); 97 98 gpio_rcar_write(p, INTMSK, ~BIT(hwirq)); 99 gpiochip_disable_irq(gc, hwirq); 100 } 101 102 static void gpio_rcar_irq_enable(struct irq_data *d) 103 { 104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 105 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 106 irq_hw_number_t hwirq = irqd_to_hwirq(d); 107 108 gpiochip_enable_irq(gc, hwirq); 109 gpio_rcar_write(p, MSKCLR, BIT(hwirq)); 110 } 111 112 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 113 unsigned int hwirq, 114 bool active_high_rising_edge, 115 bool level_trigger, 116 bool both) 117 { 118 unsigned long flags; 119 120 /* follow steps in the GPIO documentation for 121 * "Setting Edge-Sensitive Interrupt Input Mode" and 122 * "Setting Level-Sensitive Interrupt Input Mode" 123 */ 124 125 raw_spin_lock_irqsave(&p->lock, flags); 126 127 /* Configure positive or negative logic in POSNEG */ 128 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 129 130 /* Configure edge or level trigger in EDGLEVEL */ 131 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 132 133 /* Select one edge or both edges in BOTHEDGE */ 134 if (p->info.has_both_edge_trigger) 135 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 136 137 /* Select "Interrupt Input Mode" in IOINTSEL */ 138 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 139 140 /* Write INTCLR in case of edge trigger */ 141 if (!level_trigger) 142 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 143 144 raw_spin_unlock_irqrestore(&p->lock, flags); 145 } 146 147 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 148 { 149 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 150 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 151 unsigned int hwirq = irqd_to_hwirq(d); 152 153 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type); 154 155 switch (type & IRQ_TYPE_SENSE_MASK) { 156 case IRQ_TYPE_LEVEL_HIGH: 157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 158 false); 159 break; 160 case IRQ_TYPE_LEVEL_LOW: 161 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 162 false); 163 break; 164 case IRQ_TYPE_EDGE_RISING: 165 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 166 false); 167 break; 168 case IRQ_TYPE_EDGE_FALLING: 169 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 170 false); 171 break; 172 case IRQ_TYPE_EDGE_BOTH: 173 if (!p->info.has_both_edge_trigger) 174 return -EINVAL; 175 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 176 true); 177 break; 178 default: 179 return -EINVAL; 180 } 181 return 0; 182 } 183 184 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) 185 { 186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 187 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 188 int error; 189 190 if (p->irq_parent) { 191 error = irq_set_irq_wake(p->irq_parent, on); 192 if (error) { 193 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n", 194 p->irq_parent); 195 p->irq_parent = 0; 196 } 197 } 198 199 if (on) 200 atomic_inc(&p->wakeup_path); 201 else 202 atomic_dec(&p->wakeup_path); 203 204 return 0; 205 } 206 207 static const struct irq_chip gpio_rcar_irq_chip = { 208 .name = "gpio-rcar", 209 .irq_mask = gpio_rcar_irq_disable, 210 .irq_unmask = gpio_rcar_irq_enable, 211 .irq_set_type = gpio_rcar_irq_set_type, 212 .irq_set_wake = gpio_rcar_irq_set_wake, 213 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | 214 IRQCHIP_MASK_ON_SUSPEND, 215 GPIOCHIP_IRQ_RESOURCE_HELPERS, 216 }; 217 218 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 219 { 220 struct gpio_rcar_priv *p = dev_id; 221 u32 pending; 222 unsigned int offset, irqs_handled = 0; 223 224 while ((pending = gpio_rcar_read(p, INTDT) & 225 gpio_rcar_read(p, INTMSK))) { 226 offset = __ffs(pending); 227 gpio_rcar_write(p, INTCLR, BIT(offset)); 228 generic_handle_domain_irq(p->gpio_chip.irq.domain, 229 offset); 230 irqs_handled++; 231 } 232 233 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 234 } 235 236 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 237 unsigned int gpio, 238 bool output) 239 { 240 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 241 unsigned long flags; 242 243 /* follow steps in the GPIO documentation for 244 * "Setting General Output Mode" and 245 * "Setting General Input Mode" 246 */ 247 248 raw_spin_lock_irqsave(&p->lock, flags); 249 250 /* Configure positive logic in POSNEG */ 251 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 252 253 /* Select "General Input/Output Mode" in IOINTSEL */ 254 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 255 256 /* Select Input Mode or Output Mode in INOUTSEL */ 257 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 258 259 /* Select General Output Register to output data in OUTDTSEL */ 260 if (p->info.has_outdtsel && output) 261 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false); 262 263 raw_spin_unlock_irqrestore(&p->lock, flags); 264 } 265 266 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 267 { 268 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 269 int error; 270 271 error = pm_runtime_get_sync(p->dev); 272 if (error < 0) { 273 pm_runtime_put(p->dev); 274 return error; 275 } 276 277 error = pinctrl_gpio_request(chip, offset); 278 if (error) 279 pm_runtime_put(p->dev); 280 281 return error; 282 } 283 284 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 285 { 286 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 287 288 pinctrl_gpio_free(chip, offset); 289 290 /* 291 * Set the GPIO as an input to ensure that the next GPIO request won't 292 * drive the GPIO pin as an output. 293 */ 294 gpio_rcar_config_general_input_output_mode(chip, offset, false); 295 296 pm_runtime_put(p->dev); 297 } 298 299 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset) 300 { 301 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 302 303 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset)) 304 return GPIO_LINE_DIRECTION_OUT; 305 306 return GPIO_LINE_DIRECTION_IN; 307 } 308 309 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 310 { 311 gpio_rcar_config_general_input_output_mode(chip, offset, false); 312 return 0; 313 } 314 315 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 316 { 317 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 318 u32 bit = BIT(offset); 319 320 /* 321 * Before R-Car Gen3, INDT does not show correct pin state when 322 * configured as output, so use OUTDT in case of output pins 323 */ 324 if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit)) 325 return !!(gpio_rcar_read(p, OUTDT) & bit); 326 else 327 return !!(gpio_rcar_read(p, INDT) & bit); 328 } 329 330 static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask, 331 unsigned long *bits) 332 { 333 u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 334 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 335 u32 outputs, m, val = 0; 336 unsigned long flags; 337 338 if (p->info.has_always_in) { 339 bits[0] = gpio_rcar_read(p, INDT) & bankmask; 340 return 0; 341 } 342 343 raw_spin_lock_irqsave(&p->lock, flags); 344 outputs = gpio_rcar_read(p, INOUTSEL); 345 m = outputs & bankmask; 346 if (m) 347 val |= gpio_rcar_read(p, OUTDT) & m; 348 349 m = ~outputs & bankmask; 350 if (m) 351 val |= gpio_rcar_read(p, INDT) & m; 352 raw_spin_unlock_irqrestore(&p->lock, flags); 353 354 bits[0] = val; 355 return 0; 356 } 357 358 static int gpio_rcar_set(struct gpio_chip *chip, unsigned int offset, int value) 359 { 360 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 361 unsigned long flags; 362 363 raw_spin_lock_irqsave(&p->lock, flags); 364 gpio_rcar_modify_bit(p, OUTDT, offset, value); 365 raw_spin_unlock_irqrestore(&p->lock, flags); 366 367 return 0; 368 } 369 370 static int gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, 371 unsigned long *bits) 372 { 373 u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 374 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 375 unsigned long flags; 376 u32 val; 377 378 raw_spin_lock_irqsave(&p->lock, flags); 379 val = gpio_rcar_read(p, OUTDT); 380 val &= ~bankmask; 381 val |= (bankmask & bits[0]); 382 gpio_rcar_write(p, OUTDT, val); 383 raw_spin_unlock_irqrestore(&p->lock, flags); 384 385 return 0; 386 } 387 388 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 389 int value) 390 { 391 /* write GPIO value to output before selecting output mode of pin */ 392 gpio_rcar_set(chip, offset, value); 393 gpio_rcar_config_general_input_output_mode(chip, offset, true); 394 return 0; 395 } 396 397 static const struct gpio_rcar_info gpio_rcar_info_gen1 = { 398 .has_outdtsel = false, 399 .has_both_edge_trigger = false, 400 .has_always_in = false, 401 .has_inen = false, 402 }; 403 404 static const struct gpio_rcar_info gpio_rcar_info_gen2 = { 405 .has_outdtsel = true, 406 .has_both_edge_trigger = true, 407 .has_always_in = false, 408 .has_inen = false, 409 }; 410 411 static const struct gpio_rcar_info gpio_rcar_info_gen3 = { 412 .has_outdtsel = true, 413 .has_both_edge_trigger = true, 414 .has_always_in = true, 415 .has_inen = false, 416 }; 417 418 static const struct gpio_rcar_info gpio_rcar_info_gen4 = { 419 .has_outdtsel = true, 420 .has_both_edge_trigger = true, 421 .has_always_in = true, 422 .has_inen = true, 423 }; 424 425 static const struct of_device_id gpio_rcar_of_table[] = { 426 { 427 .compatible = "renesas,gpio-r8a779a0", 428 .data = &gpio_rcar_info_gen4, 429 }, { 430 .compatible = "renesas,rcar-gen1-gpio", 431 .data = &gpio_rcar_info_gen1, 432 }, { 433 .compatible = "renesas,rcar-gen2-gpio", 434 .data = &gpio_rcar_info_gen2, 435 }, { 436 .compatible = "renesas,rcar-gen3-gpio", 437 .data = &gpio_rcar_info_gen3, 438 }, { 439 .compatible = "renesas,rcar-gen4-gpio", 440 .data = &gpio_rcar_info_gen4, 441 }, { 442 .compatible = "renesas,gpio-rcar", 443 .data = &gpio_rcar_info_gen1, 444 }, { 445 /* Terminator */ 446 }, 447 }; 448 449 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 450 451 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) 452 { 453 struct device_node *np = p->dev->of_node; 454 const struct gpio_rcar_info *info; 455 struct of_phandle_args args; 456 int ret; 457 458 info = of_device_get_match_data(p->dev); 459 p->info = *info; 460 461 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); 462 if (ret) { 463 *npins = RCAR_MAX_GPIO_PER_BANK; 464 } else { 465 *npins = args.args[2]; 466 of_node_put(args.np); 467 } 468 469 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { 470 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n", 471 *npins, RCAR_MAX_GPIO_PER_BANK); 472 *npins = RCAR_MAX_GPIO_PER_BANK; 473 } 474 475 return 0; 476 } 477 478 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) 479 { 480 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0); 481 const unsigned long *valid_mask; 482 483 valid_mask = gpiochip_query_valid_mask(&p->gpio_chip); 484 485 /* Select "Input Enable" in INEN */ 486 if (valid_mask) 487 mask &= valid_mask[0]; 488 if (mask) 489 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask); 490 } 491 492 static int gpio_rcar_probe(struct platform_device *pdev) 493 { 494 struct gpio_rcar_priv *p; 495 struct gpio_chip *gpio_chip; 496 struct gpio_irq_chip *girq; 497 struct device *dev = &pdev->dev; 498 const char *name = dev_name(dev); 499 unsigned int npins; 500 int ret; 501 502 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 503 if (!p) 504 return -ENOMEM; 505 506 p->dev = dev; 507 raw_spin_lock_init(&p->lock); 508 509 /* Get device configuration from DT node */ 510 ret = gpio_rcar_parse_dt(p, &npins); 511 if (ret < 0) 512 return ret; 513 514 platform_set_drvdata(pdev, p); 515 516 pm_runtime_enable(dev); 517 518 ret = platform_get_irq(pdev, 0); 519 if (ret < 0) 520 goto err0; 521 p->irq_parent = ret; 522 523 p->base = devm_platform_ioremap_resource(pdev, 0); 524 if (IS_ERR(p->base)) { 525 ret = PTR_ERR(p->base); 526 goto err0; 527 } 528 529 gpio_chip = &p->gpio_chip; 530 gpio_chip->request = gpio_rcar_request; 531 gpio_chip->free = gpio_rcar_free; 532 gpio_chip->get_direction = gpio_rcar_get_direction; 533 gpio_chip->direction_input = gpio_rcar_direction_input; 534 gpio_chip->get = gpio_rcar_get; 535 gpio_chip->get_multiple = gpio_rcar_get_multiple; 536 gpio_chip->direction_output = gpio_rcar_direction_output; 537 gpio_chip->set = gpio_rcar_set; 538 gpio_chip->set_multiple = gpio_rcar_set_multiple; 539 gpio_chip->label = name; 540 gpio_chip->parent = dev; 541 gpio_chip->owner = THIS_MODULE; 542 gpio_chip->base = -1; 543 gpio_chip->ngpio = npins; 544 545 girq = &gpio_chip->irq; 546 gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip); 547 /* This will let us handle the parent IRQ in the driver */ 548 girq->parent_handler = NULL; 549 girq->num_parents = 0; 550 girq->parents = NULL; 551 girq->default_type = IRQ_TYPE_NONE; 552 girq->handler = handle_level_irq; 553 554 ret = gpiochip_add_data(gpio_chip, p); 555 if (ret) { 556 dev_err(dev, "failed to add GPIO controller\n"); 557 goto err0; 558 } 559 560 irq_domain_set_pm_device(gpio_chip->irq.domain, dev); 561 ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler, 562 IRQF_SHARED, name, p); 563 if (ret) { 564 dev_err(dev, "failed to request IRQ\n"); 565 goto err1; 566 } 567 568 if (p->info.has_inen) { 569 pm_runtime_get_sync(dev); 570 gpio_rcar_enable_inputs(p); 571 pm_runtime_put(dev); 572 } 573 574 dev_info(dev, "driving %d GPIOs\n", npins); 575 576 return 0; 577 578 err1: 579 gpiochip_remove(gpio_chip); 580 err0: 581 pm_runtime_disable(dev); 582 return ret; 583 } 584 585 static void gpio_rcar_remove(struct platform_device *pdev) 586 { 587 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 588 589 gpiochip_remove(&p->gpio_chip); 590 591 pm_runtime_disable(&pdev->dev); 592 } 593 594 static int gpio_rcar_suspend(struct device *dev) 595 { 596 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 597 598 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL); 599 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL); 600 p->bank_info.outdt = gpio_rcar_read(p, OUTDT); 601 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK); 602 p->bank_info.posneg = gpio_rcar_read(p, POSNEG); 603 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL); 604 if (p->info.has_both_edge_trigger) 605 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE); 606 607 if (atomic_read(&p->wakeup_path)) 608 device_set_wakeup_path(dev); 609 610 return 0; 611 } 612 613 static int gpio_rcar_resume(struct device *dev) 614 { 615 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 616 unsigned int offset; 617 u32 mask; 618 619 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { 620 if (!gpiochip_line_is_valid(&p->gpio_chip, offset)) 621 continue; 622 623 mask = BIT(offset); 624 /* I/O pin */ 625 if (!(p->bank_info.iointsel & mask)) { 626 if (p->bank_info.inoutsel & mask) 627 gpio_rcar_direction_output( 628 &p->gpio_chip, offset, 629 !!(p->bank_info.outdt & mask)); 630 else 631 gpio_rcar_direction_input(&p->gpio_chip, 632 offset); 633 } else { 634 /* Interrupt pin */ 635 gpio_rcar_config_interrupt_input_mode( 636 p, 637 offset, 638 !(p->bank_info.posneg & mask), 639 !(p->bank_info.edglevel & mask), 640 !!(p->bank_info.bothedge & mask)); 641 642 if (p->bank_info.intmsk & mask) 643 gpio_rcar_write(p, MSKCLR, mask); 644 } 645 } 646 647 if (p->info.has_inen) 648 gpio_rcar_enable_inputs(p); 649 650 return 0; 651 } 652 653 static DEFINE_SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, 654 gpio_rcar_resume); 655 656 static struct platform_driver gpio_rcar_device_driver = { 657 .probe = gpio_rcar_probe, 658 .remove = gpio_rcar_remove, 659 .driver = { 660 .name = "gpio_rcar", 661 .pm = pm_sleep_ptr(&gpio_rcar_pm_ops), 662 .of_match_table = gpio_rcar_of_table, 663 } 664 }; 665 666 module_platform_driver(gpio_rcar_device_driver); 667 668 MODULE_AUTHOR("Magnus Damm"); 669 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 670 MODULE_LICENSE("GPL v2"); 671