1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas R-Car GPIO Support 4 * 5 * Copyright (C) 2014 Renesas Electronics Corporation 6 * Copyright (C) 2013 Magnus Damm 7 */ 8 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/spinlock.h> 22 #include <linux/slab.h> 23 24 struct gpio_rcar_bank_info { 25 u32 iointsel; 26 u32 inoutsel; 27 u32 outdt; 28 u32 posneg; 29 u32 edglevel; 30 u32 bothedge; 31 u32 intmsk; 32 }; 33 34 struct gpio_rcar_info { 35 bool has_outdtsel; 36 bool has_both_edge_trigger; 37 bool has_always_in; 38 bool has_inen; 39 const u8 *offsetmap; 40 }; 41 42 struct gpio_rcar_priv { 43 void __iomem *base; 44 raw_spinlock_t lock; 45 struct device *dev; 46 struct gpio_chip gpio_chip; 47 unsigned int irq_parent; 48 atomic_t wakeup_path; 49 struct gpio_rcar_info info; 50 struct gpio_rcar_bank_info bank_info; 51 }; 52 53 enum gpio_rcar_reg { 54 IOINTSEL, /* General IO/Interrupt Switching Register */ 55 INOUTSEL, /* General Input/Output Switching Register */ 56 OUTDT, /* General Output Register */ 57 INDT, /* General Input Register */ 58 INTDT, /* Interrupt Display Register */ 59 INTCLR, /* Interrupt Clear Register */ 60 INTMSK, /* Interrupt Mask Register */ 61 MSKCLR, /* Interrupt Mask Clear Register */ 62 POSNEG, /* Positive/Negative Logic Select Register */ 63 EDGLEVEL, /* Edge/level Select Register */ 64 OUTDTSEL, /* Output Data Select Register */ 65 BOTHEDGE, /* One Edge/Both Edge Select Register */ 66 INEN, /* General Input Enable Register */ 67 }; 68 69 static const u8 gpio_rcar_offsetmap_gen1[] = { 70 [IOINTSEL] = 0x00, 71 [INOUTSEL] = 0x04, 72 [OUTDT] = 0x08, 73 [INDT] = 0x0c, 74 [INTDT] = 0x10, 75 [INTCLR] = 0x14, 76 [INTMSK] = 0x18, 77 [MSKCLR] = 0x1c, 78 [POSNEG] = 0x20, 79 [EDGLEVEL] = 0x24, 80 [OUTDTSEL] = 0x40, 81 [BOTHEDGE] = 0x4c, 82 [INEN] = 0x50, 83 }; 84 85 static const u8 gpio_rcar_offsetmap_gen5[] = { 86 [IOINTSEL] = 0x00, 87 [INOUTSEL] = 0x04, 88 [OUTDT] = 0x08, 89 [INDT] = 0x1c, 90 [INTDT] = 0x80, 91 [INTCLR] = 0x84, 92 [INTMSK] = 0x88, 93 [MSKCLR] = 0x8c, 94 [POSNEG] = 0x90, 95 [EDGLEVEL] = 0x94, 96 [OUTDTSEL] = 0x0c, 97 [BOTHEDGE] = 0xbc, 98 [INEN] = 0x18, 99 }; 100 101 #define RCAR_MAX_GPIO_PER_BANK 32 102 103 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, enum gpio_rcar_reg offs) 104 { 105 return ioread32(p->base + p->info.offsetmap[offs]); 106 } 107 108 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, enum gpio_rcar_reg offs, 109 u32 value) 110 { 111 iowrite32(value, p->base + p->info.offsetmap[offs]); 112 } 113 114 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, enum gpio_rcar_reg offs, 115 int bit, bool value) 116 { 117 u32 tmp = gpio_rcar_read(p, offs); 118 119 if (value) 120 tmp |= BIT(bit); 121 else 122 tmp &= ~BIT(bit); 123 124 gpio_rcar_write(p, offs, tmp); 125 } 126 127 static void gpio_rcar_irq_disable(struct irq_data *d) 128 { 129 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 130 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 131 irq_hw_number_t hwirq = irqd_to_hwirq(d); 132 133 gpio_rcar_write(p, INTMSK, ~BIT(hwirq)); 134 gpiochip_disable_irq(gc, hwirq); 135 } 136 137 static void gpio_rcar_irq_enable(struct irq_data *d) 138 { 139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 140 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 141 irq_hw_number_t hwirq = irqd_to_hwirq(d); 142 143 gpiochip_enable_irq(gc, hwirq); 144 gpio_rcar_write(p, MSKCLR, BIT(hwirq)); 145 } 146 147 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, 148 unsigned int hwirq, 149 bool active_high_rising_edge, 150 bool level_trigger, 151 bool both) 152 { 153 unsigned long flags; 154 155 /* follow steps in the GPIO documentation for 156 * "Setting Edge-Sensitive Interrupt Input Mode" and 157 * "Setting Level-Sensitive Interrupt Input Mode" 158 */ 159 160 raw_spin_lock_irqsave(&p->lock, flags); 161 162 /* Configure positive or negative logic in POSNEG */ 163 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); 164 165 /* Configure edge or level trigger in EDGLEVEL */ 166 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); 167 168 /* Select one edge or both edges in BOTHEDGE */ 169 if (p->info.has_both_edge_trigger) 170 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); 171 172 /* Select "Interrupt Input Mode" in IOINTSEL */ 173 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); 174 175 /* Write INTCLR in case of edge trigger */ 176 if (!level_trigger) 177 gpio_rcar_write(p, INTCLR, BIT(hwirq)); 178 179 raw_spin_unlock_irqrestore(&p->lock, flags); 180 } 181 182 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) 183 { 184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 185 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 186 unsigned int hwirq = irqd_to_hwirq(d); 187 188 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type); 189 190 switch (type & IRQ_TYPE_SENSE_MASK) { 191 case IRQ_TYPE_LEVEL_HIGH: 192 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, 193 false); 194 break; 195 case IRQ_TYPE_LEVEL_LOW: 196 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, 197 false); 198 break; 199 case IRQ_TYPE_EDGE_RISING: 200 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 201 false); 202 break; 203 case IRQ_TYPE_EDGE_FALLING: 204 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, 205 false); 206 break; 207 case IRQ_TYPE_EDGE_BOTH: 208 if (!p->info.has_both_edge_trigger) 209 return -EINVAL; 210 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, 211 true); 212 break; 213 default: 214 return -EINVAL; 215 } 216 return 0; 217 } 218 219 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) 220 { 221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 222 struct gpio_rcar_priv *p = gpiochip_get_data(gc); 223 int error; 224 225 if (p->irq_parent) { 226 error = irq_set_irq_wake(p->irq_parent, on); 227 if (error) { 228 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n", 229 p->irq_parent); 230 p->irq_parent = 0; 231 } 232 } 233 234 if (on) 235 atomic_inc(&p->wakeup_path); 236 else 237 atomic_dec(&p->wakeup_path); 238 239 return 0; 240 } 241 242 static const struct irq_chip gpio_rcar_irq_chip = { 243 .name = "gpio-rcar", 244 .irq_mask = gpio_rcar_irq_disable, 245 .irq_unmask = gpio_rcar_irq_enable, 246 .irq_set_type = gpio_rcar_irq_set_type, 247 .irq_set_wake = gpio_rcar_irq_set_wake, 248 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED | 249 IRQCHIP_MASK_ON_SUSPEND, 250 GPIOCHIP_IRQ_RESOURCE_HELPERS, 251 }; 252 253 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) 254 { 255 struct gpio_rcar_priv *p = dev_id; 256 u32 pending; 257 unsigned int offset, irqs_handled = 0; 258 259 while ((pending = gpio_rcar_read(p, INTDT) & 260 gpio_rcar_read(p, INTMSK))) { 261 offset = __ffs(pending); 262 gpio_rcar_write(p, INTCLR, BIT(offset)); 263 generic_handle_domain_irq(p->gpio_chip.irq.domain, 264 offset); 265 irqs_handled++; 266 } 267 268 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 269 } 270 271 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, 272 unsigned int gpio, 273 bool output) 274 { 275 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 276 unsigned long flags; 277 278 /* follow steps in the GPIO documentation for 279 * "Setting General Output Mode" and 280 * "Setting General Input Mode" 281 */ 282 283 raw_spin_lock_irqsave(&p->lock, flags); 284 285 /* Configure positive logic in POSNEG */ 286 gpio_rcar_modify_bit(p, POSNEG, gpio, false); 287 288 /* Select "General Input/Output Mode" in IOINTSEL */ 289 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); 290 291 /* Select Input Mode or Output Mode in INOUTSEL */ 292 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); 293 294 /* Select General Output Register to output data in OUTDTSEL */ 295 if (p->info.has_outdtsel && output) 296 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false); 297 298 raw_spin_unlock_irqrestore(&p->lock, flags); 299 } 300 301 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) 302 { 303 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 304 int error; 305 306 error = pm_runtime_get_sync(p->dev); 307 if (error < 0) { 308 pm_runtime_put(p->dev); 309 return error; 310 } 311 312 error = pinctrl_gpio_request(chip, offset); 313 if (error) 314 pm_runtime_put(p->dev); 315 316 return error; 317 } 318 319 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) 320 { 321 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 322 323 pinctrl_gpio_free(chip, offset); 324 325 /* 326 * Set the GPIO as an input to ensure that the next GPIO request won't 327 * drive the GPIO pin as an output. 328 */ 329 gpio_rcar_config_general_input_output_mode(chip, offset, false); 330 331 pm_runtime_put(p->dev); 332 } 333 334 static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset) 335 { 336 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 337 338 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset)) 339 return GPIO_LINE_DIRECTION_OUT; 340 341 return GPIO_LINE_DIRECTION_IN; 342 } 343 344 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) 345 { 346 gpio_rcar_config_general_input_output_mode(chip, offset, false); 347 return 0; 348 } 349 350 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) 351 { 352 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 353 u32 bit = BIT(offset); 354 355 /* 356 * Before R-Car Gen3, INDT does not show correct pin state when 357 * configured as output, so use OUTDT in case of output pins 358 */ 359 if (!p->info.has_always_in && (gpio_rcar_read(p, INOUTSEL) & bit)) 360 return !!(gpio_rcar_read(p, OUTDT) & bit); 361 else 362 return !!(gpio_rcar_read(p, INDT) & bit); 363 } 364 365 static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask, 366 unsigned long *bits) 367 { 368 u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 369 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 370 u32 outputs, m, val = 0; 371 unsigned long flags; 372 373 if (p->info.has_always_in) { 374 bits[0] = gpio_rcar_read(p, INDT) & bankmask; 375 return 0; 376 } 377 378 raw_spin_lock_irqsave(&p->lock, flags); 379 outputs = gpio_rcar_read(p, INOUTSEL); 380 m = outputs & bankmask; 381 if (m) 382 val |= gpio_rcar_read(p, OUTDT) & m; 383 384 m = ~outputs & bankmask; 385 if (m) 386 val |= gpio_rcar_read(p, INDT) & m; 387 raw_spin_unlock_irqrestore(&p->lock, flags); 388 389 bits[0] = val; 390 return 0; 391 } 392 393 static int gpio_rcar_set(struct gpio_chip *chip, unsigned int offset, int value) 394 { 395 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 396 unsigned long flags; 397 398 raw_spin_lock_irqsave(&p->lock, flags); 399 gpio_rcar_modify_bit(p, OUTDT, offset, value); 400 raw_spin_unlock_irqrestore(&p->lock, flags); 401 402 return 0; 403 } 404 405 static int gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, 406 unsigned long *bits) 407 { 408 u32 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); 409 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 410 unsigned long flags; 411 u32 val; 412 413 raw_spin_lock_irqsave(&p->lock, flags); 414 val = gpio_rcar_read(p, OUTDT); 415 val &= ~bankmask; 416 val |= (bankmask & bits[0]); 417 gpio_rcar_write(p, OUTDT, val); 418 raw_spin_unlock_irqrestore(&p->lock, flags); 419 420 return 0; 421 } 422 423 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, 424 int value) 425 { 426 /* write GPIO value to output before selecting output mode of pin */ 427 gpio_rcar_set(chip, offset, value); 428 gpio_rcar_config_general_input_output_mode(chip, offset, true); 429 return 0; 430 } 431 432 static const struct gpio_rcar_info gpio_rcar_info_gen1 = { 433 .has_outdtsel = false, 434 .has_both_edge_trigger = false, 435 .has_always_in = false, 436 .has_inen = false, 437 .offsetmap = gpio_rcar_offsetmap_gen1, 438 }; 439 440 static const struct gpio_rcar_info gpio_rcar_info_gen2 = { 441 .has_outdtsel = true, 442 .has_both_edge_trigger = true, 443 .has_always_in = false, 444 .has_inen = false, 445 .offsetmap = gpio_rcar_offsetmap_gen1, 446 }; 447 448 static const struct gpio_rcar_info gpio_rcar_info_gen3 = { 449 .has_outdtsel = true, 450 .has_both_edge_trigger = true, 451 .has_always_in = true, 452 .has_inen = false, 453 .offsetmap = gpio_rcar_offsetmap_gen1, 454 }; 455 456 static const struct gpio_rcar_info gpio_rcar_info_gen4 = { 457 .has_outdtsel = true, 458 .has_both_edge_trigger = true, 459 .has_always_in = true, 460 .has_inen = true, 461 .offsetmap = gpio_rcar_offsetmap_gen1, 462 }; 463 464 static const struct gpio_rcar_info gpio_rcar_info_gen5 = { 465 .has_outdtsel = true, 466 .has_both_edge_trigger = true, 467 .has_always_in = true, 468 .has_inen = true, 469 .offsetmap = gpio_rcar_offsetmap_gen5, 470 }; 471 472 static const struct of_device_id gpio_rcar_of_table[] = { 473 { 474 .compatible = "renesas,gpio-r8a779a0", 475 .data = &gpio_rcar_info_gen4, 476 }, { 477 .compatible = "renesas,rcar-gen1-gpio", 478 .data = &gpio_rcar_info_gen1, 479 }, { 480 .compatible = "renesas,rcar-gen2-gpio", 481 .data = &gpio_rcar_info_gen2, 482 }, { 483 .compatible = "renesas,rcar-gen3-gpio", 484 .data = &gpio_rcar_info_gen3, 485 }, { 486 .compatible = "renesas,rcar-gen4-gpio", 487 .data = &gpio_rcar_info_gen4, 488 }, { 489 .compatible = "renesas,rcar-gen5-gpio", 490 .data = &gpio_rcar_info_gen5, 491 }, { 492 .compatible = "renesas,gpio-rcar", 493 .data = &gpio_rcar_info_gen1, 494 }, { 495 /* Terminator */ 496 }, 497 }; 498 499 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); 500 501 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) 502 { 503 struct device_node *np = p->dev->of_node; 504 const struct gpio_rcar_info *info; 505 struct of_phandle_args args; 506 int ret; 507 508 info = of_device_get_match_data(p->dev); 509 p->info = *info; 510 511 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); 512 if (ret) { 513 *npins = RCAR_MAX_GPIO_PER_BANK; 514 } else { 515 *npins = args.args[2]; 516 of_node_put(args.np); 517 } 518 519 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { 520 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n", 521 *npins, RCAR_MAX_GPIO_PER_BANK); 522 *npins = RCAR_MAX_GPIO_PER_BANK; 523 } 524 525 return 0; 526 } 527 528 static void gpio_rcar_enable_inputs(struct gpio_rcar_priv *p) 529 { 530 u32 mask = GENMASK(p->gpio_chip.ngpio - 1, 0); 531 const unsigned long *valid_mask; 532 533 valid_mask = gpiochip_query_valid_mask(&p->gpio_chip); 534 535 /* Select "Input Enable" in INEN */ 536 if (valid_mask) 537 mask &= valid_mask[0]; 538 if (mask) 539 gpio_rcar_write(p, INEN, gpio_rcar_read(p, INEN) | mask); 540 } 541 542 static int gpio_rcar_probe(struct platform_device *pdev) 543 { 544 struct gpio_rcar_priv *p; 545 struct gpio_chip *gpio_chip; 546 struct gpio_irq_chip *girq; 547 struct device *dev = &pdev->dev; 548 const char *name = dev_name(dev); 549 unsigned int npins; 550 int ret; 551 552 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 553 if (!p) 554 return -ENOMEM; 555 556 p->dev = dev; 557 raw_spin_lock_init(&p->lock); 558 559 /* Get device configuration from DT node */ 560 ret = gpio_rcar_parse_dt(p, &npins); 561 if (ret < 0) 562 return ret; 563 564 platform_set_drvdata(pdev, p); 565 566 pm_runtime_enable(dev); 567 568 ret = platform_get_irq(pdev, 0); 569 if (ret < 0) 570 goto err0; 571 p->irq_parent = ret; 572 573 p->base = devm_platform_ioremap_resource(pdev, 0); 574 if (IS_ERR(p->base)) { 575 ret = PTR_ERR(p->base); 576 goto err0; 577 } 578 579 gpio_chip = &p->gpio_chip; 580 gpio_chip->request = gpio_rcar_request; 581 gpio_chip->free = gpio_rcar_free; 582 gpio_chip->get_direction = gpio_rcar_get_direction; 583 gpio_chip->direction_input = gpio_rcar_direction_input; 584 gpio_chip->get = gpio_rcar_get; 585 gpio_chip->get_multiple = gpio_rcar_get_multiple; 586 gpio_chip->direction_output = gpio_rcar_direction_output; 587 gpio_chip->set = gpio_rcar_set; 588 gpio_chip->set_multiple = gpio_rcar_set_multiple; 589 gpio_chip->label = name; 590 gpio_chip->parent = dev; 591 gpio_chip->owner = THIS_MODULE; 592 gpio_chip->base = -1; 593 gpio_chip->ngpio = npins; 594 595 girq = &gpio_chip->irq; 596 gpio_irq_chip_set_chip(girq, &gpio_rcar_irq_chip); 597 /* This will let us handle the parent IRQ in the driver */ 598 girq->parent_handler = NULL; 599 girq->num_parents = 0; 600 girq->parents = NULL; 601 girq->default_type = IRQ_TYPE_NONE; 602 girq->handler = handle_level_irq; 603 604 ret = gpiochip_add_data(gpio_chip, p); 605 if (ret) { 606 dev_err(dev, "failed to add GPIO controller\n"); 607 goto err0; 608 } 609 610 irq_domain_set_pm_device(gpio_chip->irq.domain, dev); 611 ret = devm_request_irq(dev, p->irq_parent, gpio_rcar_irq_handler, 612 IRQF_SHARED, name, p); 613 if (ret) { 614 dev_err(dev, "failed to request IRQ\n"); 615 goto err1; 616 } 617 618 if (p->info.has_inen) { 619 pm_runtime_get_sync(dev); 620 gpio_rcar_enable_inputs(p); 621 pm_runtime_put(dev); 622 } 623 624 dev_info(dev, "driving %d GPIOs\n", npins); 625 626 return 0; 627 628 err1: 629 gpiochip_remove(gpio_chip); 630 err0: 631 pm_runtime_disable(dev); 632 return ret; 633 } 634 635 static void gpio_rcar_remove(struct platform_device *pdev) 636 { 637 struct gpio_rcar_priv *p = platform_get_drvdata(pdev); 638 639 gpiochip_remove(&p->gpio_chip); 640 641 pm_runtime_disable(&pdev->dev); 642 } 643 644 static int gpio_rcar_suspend(struct device *dev) 645 { 646 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 647 648 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL); 649 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL); 650 p->bank_info.outdt = gpio_rcar_read(p, OUTDT); 651 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK); 652 p->bank_info.posneg = gpio_rcar_read(p, POSNEG); 653 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL); 654 if (p->info.has_both_edge_trigger) 655 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE); 656 657 if (atomic_read(&p->wakeup_path)) 658 device_set_wakeup_path(dev); 659 660 return 0; 661 } 662 663 static int gpio_rcar_resume(struct device *dev) 664 { 665 struct gpio_rcar_priv *p = dev_get_drvdata(dev); 666 unsigned int offset; 667 u32 mask; 668 669 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { 670 if (!gpiochip_line_is_valid(&p->gpio_chip, offset)) 671 continue; 672 673 mask = BIT(offset); 674 /* I/O pin */ 675 if (!(p->bank_info.iointsel & mask)) { 676 if (p->bank_info.inoutsel & mask) 677 gpio_rcar_direction_output( 678 &p->gpio_chip, offset, 679 !!(p->bank_info.outdt & mask)); 680 else 681 gpio_rcar_direction_input(&p->gpio_chip, 682 offset); 683 } else { 684 /* Interrupt pin */ 685 gpio_rcar_config_interrupt_input_mode( 686 p, 687 offset, 688 !(p->bank_info.posneg & mask), 689 !(p->bank_info.edglevel & mask), 690 !!(p->bank_info.bothedge & mask)); 691 692 if (p->bank_info.intmsk & mask) 693 gpio_rcar_write(p, MSKCLR, mask); 694 } 695 } 696 697 if (p->info.has_inen) 698 gpio_rcar_enable_inputs(p); 699 700 return 0; 701 } 702 703 static DEFINE_SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, 704 gpio_rcar_resume); 705 706 static struct platform_driver gpio_rcar_device_driver = { 707 .probe = gpio_rcar_probe, 708 .remove = gpio_rcar_remove, 709 .driver = { 710 .name = "gpio_rcar", 711 .pm = pm_sleep_ptr(&gpio_rcar_pm_ops), 712 .of_match_table = gpio_rcar_of_table, 713 } 714 }; 715 716 module_platform_driver(gpio_rcar_device_driver); 717 718 MODULE_AUTHOR("Magnus Damm"); 719 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); 720 MODULE_LICENSE("GPL v2"); 721