xref: /linux/drivers/gpio/gpio-rcar.c (revision 110e6f26af80dfd90b6e5c645b1aed7228aa580d) 
1 /*
2  * Renesas R-Car GPIO Support
3  *
4  *  Copyright (C) 2014 Renesas Electronics Corporation
5  *  Copyright (C) 2013 Magnus Damm
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/gpio.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/ioport.h>
24 #include <linux/irq.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/spinlock.h>
31 #include <linux/slab.h>
32 
33 struct gpio_rcar_priv {
34 	void __iomem *base;
35 	spinlock_t lock;
36 	struct platform_device *pdev;
37 	struct gpio_chip gpio_chip;
38 	struct irq_chip irq_chip;
39 	struct clk *clk;
40 	unsigned int irq_parent;
41 	bool has_both_edge_trigger;
42 	bool needs_clk;
43 };
44 
45 #define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
46 #define INOUTSEL 0x04	/* General Input/Output Switching Register */
47 #define OUTDT 0x08	/* General Output Register */
48 #define INDT 0x0c	/* General Input Register */
49 #define INTDT 0x10	/* Interrupt Display Register */
50 #define INTCLR 0x14	/* Interrupt Clear Register */
51 #define INTMSK 0x18	/* Interrupt Mask Register */
52 #define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
53 #define POSNEG 0x20	/* Positive/Negative Logic Select Register */
54 #define EDGLEVEL 0x24	/* Edge/level Select Register */
55 #define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
56 #define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */
57 
58 #define RCAR_MAX_GPIO_PER_BANK		32
59 
60 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
61 {
62 	return ioread32(p->base + offs);
63 }
64 
65 static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
66 				   u32 value)
67 {
68 	iowrite32(value, p->base + offs);
69 }
70 
71 static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
72 				 int bit, bool value)
73 {
74 	u32 tmp = gpio_rcar_read(p, offs);
75 
76 	if (value)
77 		tmp |= BIT(bit);
78 	else
79 		tmp &= ~BIT(bit);
80 
81 	gpio_rcar_write(p, offs, tmp);
82 }
83 
84 static void gpio_rcar_irq_disable(struct irq_data *d)
85 {
86 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
87 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
88 
89 	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
90 }
91 
92 static void gpio_rcar_irq_enable(struct irq_data *d)
93 {
94 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
95 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
96 
97 	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
98 }
99 
100 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
101 						  unsigned int hwirq,
102 						  bool active_high_rising_edge,
103 						  bool level_trigger,
104 						  bool both)
105 {
106 	unsigned long flags;
107 
108 	/* follow steps in the GPIO documentation for
109 	 * "Setting Edge-Sensitive Interrupt Input Mode" and
110 	 * "Setting Level-Sensitive Interrupt Input Mode"
111 	 */
112 
113 	spin_lock_irqsave(&p->lock, flags);
114 
115 	/* Configure postive or negative logic in POSNEG */
116 	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
117 
118 	/* Configure edge or level trigger in EDGLEVEL */
119 	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
120 
121 	/* Select one edge or both edges in BOTHEDGE */
122 	if (p->has_both_edge_trigger)
123 		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
124 
125 	/* Select "Interrupt Input Mode" in IOINTSEL */
126 	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
127 
128 	/* Write INTCLR in case of edge trigger */
129 	if (!level_trigger)
130 		gpio_rcar_write(p, INTCLR, BIT(hwirq));
131 
132 	spin_unlock_irqrestore(&p->lock, flags);
133 }
134 
135 static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
136 {
137 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
138 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
139 	unsigned int hwirq = irqd_to_hwirq(d);
140 
141 	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
142 
143 	switch (type & IRQ_TYPE_SENSE_MASK) {
144 	case IRQ_TYPE_LEVEL_HIGH:
145 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
146 						      false);
147 		break;
148 	case IRQ_TYPE_LEVEL_LOW:
149 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
150 						      false);
151 		break;
152 	case IRQ_TYPE_EDGE_RISING:
153 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
154 						      false);
155 		break;
156 	case IRQ_TYPE_EDGE_FALLING:
157 		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
158 						      false);
159 		break;
160 	case IRQ_TYPE_EDGE_BOTH:
161 		if (!p->has_both_edge_trigger)
162 			return -EINVAL;
163 		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
164 						      true);
165 		break;
166 	default:
167 		return -EINVAL;
168 	}
169 	return 0;
170 }
171 
172 static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
173 {
174 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
175 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
176 	int error;
177 
178 	if (p->irq_parent) {
179 		error = irq_set_irq_wake(p->irq_parent, on);
180 		if (error) {
181 			dev_dbg(&p->pdev->dev,
182 				"irq %u doesn't support irq_set_wake\n",
183 				p->irq_parent);
184 			p->irq_parent = 0;
185 		}
186 	}
187 
188 	if (!p->clk)
189 		return 0;
190 
191 	if (on)
192 		clk_enable(p->clk);
193 	else
194 		clk_disable(p->clk);
195 
196 	return 0;
197 }
198 
199 static void gpio_rcar_irq_bus_lock(struct irq_data *d)
200 {
201 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
203 
204 	pm_runtime_get_sync(&p->pdev->dev);
205 }
206 
207 static void gpio_rcar_irq_bus_sync_unlock(struct irq_data *d)
208 {
209 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
210 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
211 
212 	pm_runtime_put(&p->pdev->dev);
213 }
214 
215 
216 static int gpio_rcar_irq_request_resources(struct irq_data *d)
217 {
218 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
219 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
220 	int error;
221 
222 	error = pm_runtime_get_sync(&p->pdev->dev);
223 	if (error < 0)
224 		return error;
225 
226 	return 0;
227 }
228 
229 static void gpio_rcar_irq_release_resources(struct irq_data *d)
230 {
231 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232 	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
233 
234 	pm_runtime_put(&p->pdev->dev);
235 }
236 
237 static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
238 {
239 	struct gpio_rcar_priv *p = dev_id;
240 	u32 pending;
241 	unsigned int offset, irqs_handled = 0;
242 
243 	while ((pending = gpio_rcar_read(p, INTDT) &
244 			  gpio_rcar_read(p, INTMSK))) {
245 		offset = __ffs(pending);
246 		gpio_rcar_write(p, INTCLR, BIT(offset));
247 		generic_handle_irq(irq_find_mapping(p->gpio_chip.irqdomain,
248 						    offset));
249 		irqs_handled++;
250 	}
251 
252 	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
253 }
254 
255 static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
256 						       unsigned int gpio,
257 						       bool output)
258 {
259 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
260 	unsigned long flags;
261 
262 	/* follow steps in the GPIO documentation for
263 	 * "Setting General Output Mode" and
264 	 * "Setting General Input Mode"
265 	 */
266 
267 	spin_lock_irqsave(&p->lock, flags);
268 
269 	/* Configure postive logic in POSNEG */
270 	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
271 
272 	/* Select "General Input/Output Mode" in IOINTSEL */
273 	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
274 
275 	/* Select Input Mode or Output Mode in INOUTSEL */
276 	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
277 
278 	spin_unlock_irqrestore(&p->lock, flags);
279 }
280 
281 static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
282 {
283 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
284 	int error;
285 
286 	error = pm_runtime_get_sync(&p->pdev->dev);
287 	if (error < 0)
288 		return error;
289 
290 	error = pinctrl_request_gpio(chip->base + offset);
291 	if (error)
292 		pm_runtime_put(&p->pdev->dev);
293 
294 	return error;
295 }
296 
297 static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
298 {
299 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
300 
301 	pinctrl_free_gpio(chip->base + offset);
302 
303 	/* Set the GPIO as an input to ensure that the next GPIO request won't
304 	 * drive the GPIO pin as an output.
305 	 */
306 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
307 
308 	pm_runtime_put(&p->pdev->dev);
309 }
310 
311 static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
312 {
313 	gpio_rcar_config_general_input_output_mode(chip, offset, false);
314 	return 0;
315 }
316 
317 static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
318 {
319 	u32 bit = BIT(offset);
320 
321 	/* testing on r8a7790 shows that INDT does not show correct pin state
322 	 * when configured as output, so use OUTDT in case of output pins */
323 	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
324 		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
325 	else
326 		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
327 }
328 
329 static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
330 {
331 	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
332 	unsigned long flags;
333 
334 	spin_lock_irqsave(&p->lock, flags);
335 	gpio_rcar_modify_bit(p, OUTDT, offset, value);
336 	spin_unlock_irqrestore(&p->lock, flags);
337 }
338 
339 static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
340 				      int value)
341 {
342 	/* write GPIO value to output before selecting output mode of pin */
343 	gpio_rcar_set(chip, offset, value);
344 	gpio_rcar_config_general_input_output_mode(chip, offset, true);
345 	return 0;
346 }
347 
348 struct gpio_rcar_info {
349 	bool has_both_edge_trigger;
350 	bool needs_clk;
351 };
352 
353 static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
354 	.has_both_edge_trigger = false,
355 	.needs_clk = false,
356 };
357 
358 static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
359 	.has_both_edge_trigger = true,
360 	.needs_clk = true,
361 };
362 
363 static const struct of_device_id gpio_rcar_of_table[] = {
364 	{
365 		.compatible = "renesas,gpio-r8a7790",
366 		.data = &gpio_rcar_info_gen2,
367 	}, {
368 		.compatible = "renesas,gpio-r8a7791",
369 		.data = &gpio_rcar_info_gen2,
370 	}, {
371 		.compatible = "renesas,gpio-r8a7793",
372 		.data = &gpio_rcar_info_gen2,
373 	}, {
374 		.compatible = "renesas,gpio-r8a7794",
375 		.data = &gpio_rcar_info_gen2,
376 	}, {
377 		.compatible = "renesas,gpio-r8a7795",
378 		/* Gen3 GPIO is identical to Gen2. */
379 		.data = &gpio_rcar_info_gen2,
380 	}, {
381 		.compatible = "renesas,gpio-rcar",
382 		.data = &gpio_rcar_info_gen1,
383 	}, {
384 		/* Terminator */
385 	},
386 };
387 
388 MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
389 
390 static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
391 {
392 	struct device_node *np = p->pdev->dev.of_node;
393 	const struct of_device_id *match;
394 	const struct gpio_rcar_info *info;
395 	struct of_phandle_args args;
396 	int ret;
397 
398 	match = of_match_node(gpio_rcar_of_table, np);
399 	if (!match)
400 		return -EINVAL;
401 
402 	info = match->data;
403 
404 	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
405 	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
406 	p->has_both_edge_trigger = info->has_both_edge_trigger;
407 	p->needs_clk = info->needs_clk;
408 
409 	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
410 		dev_warn(&p->pdev->dev,
411 			 "Invalid number of gpio lines %u, using %u\n", *npins,
412 			 RCAR_MAX_GPIO_PER_BANK);
413 		*npins = RCAR_MAX_GPIO_PER_BANK;
414 	}
415 
416 	return 0;
417 }
418 
419 static int gpio_rcar_probe(struct platform_device *pdev)
420 {
421 	struct gpio_rcar_priv *p;
422 	struct resource *io, *irq;
423 	struct gpio_chip *gpio_chip;
424 	struct irq_chip *irq_chip;
425 	struct device *dev = &pdev->dev;
426 	const char *name = dev_name(dev);
427 	unsigned int npins;
428 	int ret;
429 
430 	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
431 	if (!p)
432 		return -ENOMEM;
433 
434 	p->pdev = pdev;
435 	spin_lock_init(&p->lock);
436 
437 	/* Get device configuration from DT node */
438 	ret = gpio_rcar_parse_dt(p, &npins);
439 	if (ret < 0)
440 		return ret;
441 
442 	platform_set_drvdata(pdev, p);
443 
444 	p->clk = devm_clk_get(dev, NULL);
445 	if (IS_ERR(p->clk)) {
446 		if (p->needs_clk) {
447 			dev_err(dev, "unable to get clock\n");
448 			ret = PTR_ERR(p->clk);
449 			goto err0;
450 		}
451 		p->clk = NULL;
452 	}
453 
454 	pm_runtime_enable(dev);
455 
456 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
458 
459 	if (!io || !irq) {
460 		dev_err(dev, "missing IRQ or IOMEM\n");
461 		ret = -EINVAL;
462 		goto err0;
463 	}
464 
465 	p->base = devm_ioremap_nocache(dev, io->start, resource_size(io));
466 	if (!p->base) {
467 		dev_err(dev, "failed to remap I/O memory\n");
468 		ret = -ENXIO;
469 		goto err0;
470 	}
471 
472 	gpio_chip = &p->gpio_chip;
473 	gpio_chip->request = gpio_rcar_request;
474 	gpio_chip->free = gpio_rcar_free;
475 	gpio_chip->direction_input = gpio_rcar_direction_input;
476 	gpio_chip->get = gpio_rcar_get;
477 	gpio_chip->direction_output = gpio_rcar_direction_output;
478 	gpio_chip->set = gpio_rcar_set;
479 	gpio_chip->label = name;
480 	gpio_chip->parent = dev;
481 	gpio_chip->owner = THIS_MODULE;
482 	gpio_chip->base = -1;
483 	gpio_chip->ngpio = npins;
484 
485 	irq_chip = &p->irq_chip;
486 	irq_chip->name = name;
487 	irq_chip->irq_mask = gpio_rcar_irq_disable;
488 	irq_chip->irq_unmask = gpio_rcar_irq_enable;
489 	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
490 	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
491 	irq_chip->irq_bus_lock = gpio_rcar_irq_bus_lock;
492 	irq_chip->irq_bus_sync_unlock = gpio_rcar_irq_bus_sync_unlock;
493 	irq_chip->irq_request_resources = gpio_rcar_irq_request_resources;
494 	irq_chip->irq_release_resources = gpio_rcar_irq_release_resources;
495 	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
496 
497 	ret = gpiochip_add_data(gpio_chip, p);
498 	if (ret) {
499 		dev_err(dev, "failed to add GPIO controller\n");
500 		goto err0;
501 	}
502 
503 	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
504 				   IRQ_TYPE_NONE);
505 	if (ret) {
506 		dev_err(dev, "cannot add irqchip\n");
507 		goto err1;
508 	}
509 
510 	p->irq_parent = irq->start;
511 	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
512 			     IRQF_SHARED, name, p)) {
513 		dev_err(dev, "failed to request IRQ\n");
514 		ret = -ENOENT;
515 		goto err1;
516 	}
517 
518 	dev_info(dev, "driving %d GPIOs\n", npins);
519 
520 	return 0;
521 
522 err1:
523 	gpiochip_remove(gpio_chip);
524 err0:
525 	pm_runtime_disable(dev);
526 	return ret;
527 }
528 
529 static int gpio_rcar_remove(struct platform_device *pdev)
530 {
531 	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
532 
533 	gpiochip_remove(&p->gpio_chip);
534 
535 	pm_runtime_disable(&pdev->dev);
536 	return 0;
537 }
538 
539 static struct platform_driver gpio_rcar_device_driver = {
540 	.probe		= gpio_rcar_probe,
541 	.remove		= gpio_rcar_remove,
542 	.driver		= {
543 		.name	= "gpio_rcar",
544 		.of_match_table = of_match_ptr(gpio_rcar_of_table),
545 	}
546 };
547 
548 module_platform_driver(gpio_rcar_device_driver);
549 
550 MODULE_AUTHOR("Magnus Damm");
551 MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
552 MODULE_LICENSE("GPL v2");
553