1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/plat-pxa/gpio.c 4 * 5 * Generic PXA GPIO handling 6 * 7 * Author: Nicolas Pitre 8 * Created: Jun 15, 2001 9 * Copyright: MontaVista Software Inc. 10 */ 11 #include <linux/module.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio-pxa.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/platform_device.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/slab.h> 27 28 /* 29 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 30 * one set of registers. The register offsets are organized below: 31 * 32 * GPLR GPDR GPSR GPCR GRER GFER GEDR 33 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 34 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 35 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 36 * 37 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 38 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 39 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 40 * 41 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248 42 * 43 * NOTE: 44 * BANK 3 is only available on PXA27x and later processors. 45 * BANK 4 and 5 are only available on PXA935, PXA1928 46 * BANK 6 is only available on PXA1928 47 */ 48 49 #define GPLR_OFFSET 0x00 50 #define GPDR_OFFSET 0x0C 51 #define GPSR_OFFSET 0x18 52 #define GPCR_OFFSET 0x24 53 #define GRER_OFFSET 0x30 54 #define GFER_OFFSET 0x3C 55 #define GEDR_OFFSET 0x48 56 #define GAFR_OFFSET 0x54 57 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 58 59 #define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2) 60 61 int pxa_last_gpio; 62 static int irq_base; 63 64 struct pxa_gpio_bank { 65 void __iomem *regbase; 66 unsigned long irq_mask; 67 unsigned long irq_edge_rise; 68 unsigned long irq_edge_fall; 69 70 #ifdef CONFIG_PM 71 unsigned long saved_gplr; 72 unsigned long saved_gpdr; 73 unsigned long saved_grer; 74 unsigned long saved_gfer; 75 #endif 76 }; 77 78 struct pxa_gpio_chip { 79 struct device *dev; 80 struct gpio_chip chip; 81 struct pxa_gpio_bank *banks; 82 struct irq_domain *irqdomain; 83 84 int irq0; 85 int irq1; 86 int (*set_wake)(unsigned int gpio, unsigned int on); 87 }; 88 89 enum pxa_gpio_type { 90 PXA25X_GPIO = 0, 91 PXA26X_GPIO, 92 PXA27X_GPIO, 93 PXA3XX_GPIO, 94 PXA93X_GPIO, 95 MMP_GPIO = 0x10, 96 MMP2_GPIO, 97 PXA1928_GPIO, 98 }; 99 100 struct pxa_gpio_id { 101 enum pxa_gpio_type type; 102 int gpio_nums; 103 }; 104 105 static DEFINE_SPINLOCK(gpio_lock); 106 static struct pxa_gpio_chip *pxa_gpio_chip; 107 static enum pxa_gpio_type gpio_type; 108 109 static struct pxa_gpio_id pxa25x_id = { 110 .type = PXA25X_GPIO, 111 .gpio_nums = 85, 112 }; 113 114 static struct pxa_gpio_id pxa26x_id = { 115 .type = PXA26X_GPIO, 116 .gpio_nums = 90, 117 }; 118 119 static struct pxa_gpio_id pxa27x_id = { 120 .type = PXA27X_GPIO, 121 .gpio_nums = 121, 122 }; 123 124 static struct pxa_gpio_id pxa3xx_id = { 125 .type = PXA3XX_GPIO, 126 .gpio_nums = 128, 127 }; 128 129 static struct pxa_gpio_id pxa93x_id = { 130 .type = PXA93X_GPIO, 131 .gpio_nums = 192, 132 }; 133 134 static struct pxa_gpio_id mmp_id = { 135 .type = MMP_GPIO, 136 .gpio_nums = 128, 137 }; 138 139 static struct pxa_gpio_id mmp2_id = { 140 .type = MMP2_GPIO, 141 .gpio_nums = 192, 142 }; 143 144 static struct pxa_gpio_id pxa1928_id = { 145 .type = PXA1928_GPIO, 146 .gpio_nums = 224, 147 }; 148 149 #define for_each_gpio_bank(i, b, pc) \ 150 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++) 151 152 static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c) 153 { 154 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c); 155 156 return pxa_chip; 157 } 158 159 static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio) 160 { 161 struct pxa_gpio_chip *p = gpiochip_get_data(c); 162 struct pxa_gpio_bank *bank = p->banks + (gpio / 32); 163 164 return bank->regbase; 165 } 166 167 static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c, 168 unsigned gpio) 169 { 170 return chip_to_pxachip(c)->banks + gpio / 32; 171 } 172 173 static inline int gpio_is_mmp_type(int type) 174 { 175 return (type & MMP_GPIO) != 0; 176 } 177 178 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 179 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 180 */ 181 static inline int __gpio_is_inverted(int gpio) 182 { 183 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 184 return 1; 185 return 0; 186 } 187 188 /* 189 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 190 * function of a GPIO, and GPDRx cannot be altered once configured. It 191 * is attributed as "occupied" here (I know this terminology isn't 192 * accurate, you are welcome to propose a better one :-) 193 */ 194 static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio) 195 { 196 void __iomem *base; 197 unsigned long gafr = 0, gpdr = 0; 198 int ret, af = 0, dir = 0; 199 200 base = gpio_bank_base(&pchip->chip, gpio); 201 gpdr = readl_relaxed(base + GPDR_OFFSET); 202 203 switch (gpio_type) { 204 case PXA25X_GPIO: 205 case PXA26X_GPIO: 206 case PXA27X_GPIO: 207 gafr = readl_relaxed(base + GAFR_OFFSET); 208 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 209 dir = gpdr & GPIO_bit(gpio); 210 211 if (__gpio_is_inverted(gpio)) 212 ret = (af != 1) || (dir == 0); 213 else 214 ret = (af != 0) || (dir != 0); 215 break; 216 default: 217 ret = gpdr & GPIO_bit(gpio); 218 break; 219 } 220 return ret; 221 } 222 223 int pxa_irq_to_gpio(int irq) 224 { 225 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 226 int irq_gpio0; 227 228 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0); 229 if (irq_gpio0 > 0) 230 return irq - irq_gpio0; 231 232 return irq_gpio0; 233 } 234 235 static bool pxa_gpio_has_pinctrl(void) 236 { 237 switch (gpio_type) { 238 case PXA3XX_GPIO: 239 case MMP2_GPIO: 240 case MMP_GPIO: 241 return false; 242 243 default: 244 return true; 245 } 246 } 247 248 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 249 { 250 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip); 251 252 return irq_find_mapping(pchip->irqdomain, offset); 253 } 254 255 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 256 { 257 void __iomem *base = gpio_bank_base(chip, offset); 258 uint32_t value, mask = GPIO_bit(offset); 259 unsigned long flags; 260 int ret; 261 262 if (pxa_gpio_has_pinctrl()) { 263 ret = pinctrl_gpio_direction_input(chip, offset); 264 if (ret) 265 return ret; 266 } 267 268 spin_lock_irqsave(&gpio_lock, flags); 269 270 value = readl_relaxed(base + GPDR_OFFSET); 271 if (__gpio_is_inverted(chip->base + offset)) 272 value |= mask; 273 else 274 value &= ~mask; 275 writel_relaxed(value, base + GPDR_OFFSET); 276 277 spin_unlock_irqrestore(&gpio_lock, flags); 278 return 0; 279 } 280 281 static int pxa_gpio_direction_output(struct gpio_chip *chip, 282 unsigned offset, int value) 283 { 284 void __iomem *base = gpio_bank_base(chip, offset); 285 uint32_t tmp, mask = GPIO_bit(offset); 286 unsigned long flags; 287 int ret; 288 289 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 290 291 if (pxa_gpio_has_pinctrl()) { 292 ret = pinctrl_gpio_direction_output(chip, offset); 293 if (ret) 294 return ret; 295 } 296 297 spin_lock_irqsave(&gpio_lock, flags); 298 299 tmp = readl_relaxed(base + GPDR_OFFSET); 300 if (__gpio_is_inverted(chip->base + offset)) 301 tmp &= ~mask; 302 else 303 tmp |= mask; 304 writel_relaxed(tmp, base + GPDR_OFFSET); 305 306 spin_unlock_irqrestore(&gpio_lock, flags); 307 return 0; 308 } 309 310 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 311 { 312 void __iomem *base = gpio_bank_base(chip, offset); 313 u32 gplr = readl_relaxed(base + GPLR_OFFSET); 314 315 return !!(gplr & GPIO_bit(offset)); 316 } 317 318 static int pxa_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 319 { 320 void __iomem *base = gpio_bank_base(chip, offset); 321 322 writel_relaxed(GPIO_bit(offset), 323 base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 324 325 return 0; 326 } 327 328 #ifdef CONFIG_OF_GPIO 329 static int pxa_gpio_of_xlate(struct gpio_chip *gc, 330 const struct of_phandle_args *gpiospec, 331 u32 *flags) 332 { 333 if (gpiospec->args[0] > pxa_last_gpio) 334 return -EINVAL; 335 336 if (flags) 337 *flags = gpiospec->args[1]; 338 339 return gpiospec->args[0]; 340 } 341 #endif 342 343 static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase) 344 { 345 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32); 346 struct pxa_gpio_bank *bank; 347 348 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks), 349 GFP_KERNEL); 350 if (!pchip->banks) 351 return -ENOMEM; 352 353 pchip->chip.parent = pchip->dev; 354 pchip->chip.label = "gpio-pxa"; 355 pchip->chip.direction_input = pxa_gpio_direction_input; 356 pchip->chip.direction_output = pxa_gpio_direction_output; 357 pchip->chip.get = pxa_gpio_get; 358 pchip->chip.set_rv = pxa_gpio_set; 359 pchip->chip.to_irq = pxa_gpio_to_irq; 360 pchip->chip.ngpio = ngpio; 361 pchip->chip.request = gpiochip_generic_request; 362 pchip->chip.free = gpiochip_generic_free; 363 364 #ifdef CONFIG_OF_GPIO 365 pchip->chip.of_xlate = pxa_gpio_of_xlate; 366 pchip->chip.of_gpio_n_cells = 2; 367 #endif 368 369 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 370 bank = pchip->banks + i; 371 bank->regbase = regbase + BANK_OFF(i); 372 } 373 374 return gpiochip_add_data(&pchip->chip, pchip); 375 } 376 377 /* Update only those GRERx and GFERx edge detection register bits if those 378 * bits are set in c->irq_mask 379 */ 380 static inline void update_edge_detect(struct pxa_gpio_bank *c) 381 { 382 uint32_t grer, gfer; 383 384 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 385 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 386 grer |= c->irq_edge_rise & c->irq_mask; 387 gfer |= c->irq_edge_fall & c->irq_mask; 388 writel_relaxed(grer, c->regbase + GRER_OFFSET); 389 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 390 } 391 392 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 393 { 394 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 395 unsigned int gpio = irqd_to_hwirq(d); 396 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 397 unsigned long gpdr, mask = GPIO_bit(gpio); 398 399 if (type == IRQ_TYPE_PROBE) { 400 /* Don't mess with enabled GPIOs using preconfigured edges or 401 * GPIOs set to alternate function or to output during probe 402 */ 403 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 404 return 0; 405 406 if (__gpio_is_occupied(pchip, gpio)) 407 return 0; 408 409 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 410 } 411 412 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 413 414 if (__gpio_is_inverted(gpio)) 415 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 416 else 417 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 418 419 if (type & IRQ_TYPE_EDGE_RISING) 420 c->irq_edge_rise |= mask; 421 else 422 c->irq_edge_rise &= ~mask; 423 424 if (type & IRQ_TYPE_EDGE_FALLING) 425 c->irq_edge_fall |= mask; 426 else 427 c->irq_edge_fall &= ~mask; 428 429 update_edge_detect(c); 430 431 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 432 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 433 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 434 return 0; 435 } 436 437 static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d) 438 { 439 int loop, gpio, n, handled = 0; 440 unsigned long gedr; 441 struct pxa_gpio_chip *pchip = d; 442 struct pxa_gpio_bank *c; 443 444 do { 445 loop = 0; 446 for_each_gpio_bank(gpio, c, pchip) { 447 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 448 gedr = gedr & c->irq_mask; 449 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 450 451 for_each_set_bit(n, &gedr, BITS_PER_LONG) { 452 loop = 1; 453 454 generic_handle_domain_irq(pchip->irqdomain, 455 gpio + n); 456 } 457 } 458 handled += loop; 459 } while (loop); 460 461 return handled ? IRQ_HANDLED : IRQ_NONE; 462 } 463 464 static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d) 465 { 466 struct pxa_gpio_chip *pchip = d; 467 468 if (in_irq == pchip->irq0) { 469 generic_handle_domain_irq(pchip->irqdomain, 0); 470 } else if (in_irq == pchip->irq1) { 471 generic_handle_domain_irq(pchip->irqdomain, 1); 472 } else { 473 pr_err("%s() unknown irq %d\n", __func__, in_irq); 474 return IRQ_NONE; 475 } 476 return IRQ_HANDLED; 477 } 478 479 static void pxa_ack_muxed_gpio(struct irq_data *d) 480 { 481 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 482 unsigned int gpio = irqd_to_hwirq(d); 483 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 484 485 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET); 486 } 487 488 static void pxa_mask_muxed_gpio(struct irq_data *d) 489 { 490 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 491 unsigned int gpio = irqd_to_hwirq(d); 492 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio); 493 void __iomem *base = gpio_bank_base(&pchip->chip, gpio); 494 uint32_t grer, gfer; 495 496 b->irq_mask &= ~GPIO_bit(gpio); 497 498 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio); 499 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio); 500 writel_relaxed(grer, base + GRER_OFFSET); 501 writel_relaxed(gfer, base + GFER_OFFSET); 502 503 gpiochip_disable_irq(&pchip->chip, gpio); 504 } 505 506 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 507 { 508 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 509 unsigned int gpio = irqd_to_hwirq(d); 510 511 if (pchip->set_wake) 512 return pchip->set_wake(gpio, on); 513 else 514 return 0; 515 } 516 517 static void pxa_unmask_muxed_gpio(struct irq_data *d) 518 { 519 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d); 520 unsigned int gpio = irqd_to_hwirq(d); 521 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio); 522 523 gpiochip_enable_irq(&pchip->chip, gpio); 524 525 c->irq_mask |= GPIO_bit(gpio); 526 update_edge_detect(c); 527 } 528 529 static const struct irq_chip pxa_muxed_gpio_chip = { 530 .name = "GPIO", 531 .irq_ack = pxa_ack_muxed_gpio, 532 .irq_mask = pxa_mask_muxed_gpio, 533 .irq_unmask = pxa_unmask_muxed_gpio, 534 .irq_set_type = pxa_gpio_irq_type, 535 .irq_set_wake = pxa_gpio_set_wake, 536 .flags = IRQCHIP_IMMUTABLE, 537 GPIOCHIP_IRQ_RESOURCE_HELPERS, 538 }; 539 540 static int pxa_gpio_nums(struct platform_device *pdev) 541 { 542 const struct platform_device_id *id = platform_get_device_id(pdev); 543 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data; 544 int count = 0; 545 546 switch (pxa_id->type) { 547 case PXA25X_GPIO: 548 case PXA26X_GPIO: 549 case PXA27X_GPIO: 550 case PXA3XX_GPIO: 551 case PXA93X_GPIO: 552 case MMP_GPIO: 553 case MMP2_GPIO: 554 case PXA1928_GPIO: 555 gpio_type = pxa_id->type; 556 count = pxa_id->gpio_nums - 1; 557 break; 558 default: 559 count = -EINVAL; 560 break; 561 } 562 return count; 563 } 564 565 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 566 irq_hw_number_t hw) 567 { 568 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 569 handle_edge_irq); 570 irq_set_chip_data(irq, d->host_data); 571 irq_set_noprobe(irq); 572 return 0; 573 } 574 575 static const struct irq_domain_ops pxa_irq_domain_ops = { 576 .map = pxa_irq_domain_map, 577 .xlate = irq_domain_xlate_twocell, 578 }; 579 580 #ifdef CONFIG_OF 581 static const struct of_device_id pxa_gpio_dt_ids[] = { 582 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, }, 583 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, }, 584 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, }, 585 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, }, 586 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, }, 587 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, }, 588 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, }, 589 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, }, 590 {} 591 }; 592 593 static int pxa_gpio_probe_dt(struct platform_device *pdev, 594 struct pxa_gpio_chip *pchip) 595 { 596 int nr_gpios; 597 const struct pxa_gpio_id *gpio_id; 598 599 gpio_id = of_device_get_match_data(&pdev->dev); 600 gpio_type = gpio_id->type; 601 602 nr_gpios = gpio_id->gpio_nums; 603 pxa_last_gpio = nr_gpios - 1; 604 605 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0); 606 if (irq_base < 0) { 607 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 608 return irq_base; 609 } 610 return irq_base; 611 } 612 #else 613 #define pxa_gpio_probe_dt(pdev, pchip) (-1) 614 #endif 615 616 static int pxa_gpio_probe(struct platform_device *pdev) 617 { 618 struct pxa_gpio_chip *pchip; 619 struct pxa_gpio_bank *c; 620 struct clk *clk; 621 struct pxa_gpio_platform_data *info; 622 void __iomem *gpio_reg_base; 623 int gpio, ret; 624 int irq0 = 0, irq1 = 0, irq_mux; 625 626 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL); 627 if (!pchip) 628 return -ENOMEM; 629 pchip->dev = &pdev->dev; 630 631 info = dev_get_platdata(&pdev->dev); 632 if (info) { 633 irq_base = info->irq_base; 634 if (irq_base <= 0) 635 return -EINVAL; 636 pxa_last_gpio = pxa_gpio_nums(pdev); 637 pchip->set_wake = info->gpio_set_wake; 638 } else { 639 irq_base = pxa_gpio_probe_dt(pdev, pchip); 640 if (irq_base < 0) 641 return -EINVAL; 642 } 643 644 if (!pxa_last_gpio) 645 return -EINVAL; 646 647 pchip->irqdomain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), pxa_last_gpio + 1, 648 irq_base, 0, &pxa_irq_domain_ops, pchip); 649 if (!pchip->irqdomain) 650 return -ENOMEM; 651 652 irq0 = platform_get_irq_byname_optional(pdev, "gpio0"); 653 irq1 = platform_get_irq_byname_optional(pdev, "gpio1"); 654 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 655 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 656 || (irq_mux <= 0)) 657 return -EINVAL; 658 659 pchip->irq0 = irq0; 660 pchip->irq1 = irq1; 661 662 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0); 663 if (IS_ERR(gpio_reg_base)) 664 return PTR_ERR(gpio_reg_base); 665 666 clk = devm_clk_get_enabled(&pdev->dev, NULL); 667 if (IS_ERR(clk)) { 668 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 669 PTR_ERR(clk)); 670 return PTR_ERR(clk); 671 } 672 673 /* Initialize GPIO chips */ 674 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base); 675 if (ret) 676 return ret; 677 678 /* clear all GPIO edge detects */ 679 for_each_gpio_bank(gpio, c, pchip) { 680 writel_relaxed(0, c->regbase + GFER_OFFSET); 681 writel_relaxed(0, c->regbase + GRER_OFFSET); 682 writel_relaxed(~0, c->regbase + GEDR_OFFSET); 683 /* unmask GPIO edge detect for AP side */ 684 if (gpio_is_mmp_type(gpio_type)) 685 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 686 } 687 688 if (irq0 > 0) { 689 ret = devm_request_irq(&pdev->dev, 690 irq0, pxa_gpio_direct_handler, 0, 691 "gpio-0", pchip); 692 if (ret) 693 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n", 694 ret); 695 } 696 if (irq1 > 0) { 697 ret = devm_request_irq(&pdev->dev, 698 irq1, pxa_gpio_direct_handler, 0, 699 "gpio-1", pchip); 700 if (ret) 701 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n", 702 ret); 703 } 704 ret = devm_request_irq(&pdev->dev, 705 irq_mux, pxa_gpio_demux_handler, 0, 706 "gpio-mux", pchip); 707 if (ret) 708 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n", 709 ret); 710 711 pxa_gpio_chip = pchip; 712 713 return 0; 714 } 715 716 static const struct platform_device_id gpio_id_table[] = { 717 { "pxa25x-gpio", (unsigned long)&pxa25x_id }, 718 { "pxa26x-gpio", (unsigned long)&pxa26x_id }, 719 { "pxa27x-gpio", (unsigned long)&pxa27x_id }, 720 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id }, 721 { "pxa93x-gpio", (unsigned long)&pxa93x_id }, 722 { "mmp-gpio", (unsigned long)&mmp_id }, 723 { "mmp2-gpio", (unsigned long)&mmp2_id }, 724 { "pxa1928-gpio", (unsigned long)&pxa1928_id }, 725 { }, 726 }; 727 728 static struct platform_driver pxa_gpio_driver = { 729 .probe = pxa_gpio_probe, 730 .driver = { 731 .name = "pxa-gpio", 732 .of_match_table = of_match_ptr(pxa_gpio_dt_ids), 733 }, 734 .id_table = gpio_id_table, 735 }; 736 737 static int __init pxa_gpio_legacy_init(void) 738 { 739 if (of_have_populated_dt()) 740 return 0; 741 742 return platform_driver_register(&pxa_gpio_driver); 743 } 744 postcore_initcall(pxa_gpio_legacy_init); 745 746 static int __init pxa_gpio_dt_init(void) 747 { 748 if (of_have_populated_dt()) 749 return platform_driver_register(&pxa_gpio_driver); 750 751 return 0; 752 } 753 device_initcall(pxa_gpio_dt_init); 754 755 #ifdef CONFIG_PM 756 static int pxa_gpio_suspend(void) 757 { 758 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 759 struct pxa_gpio_bank *c; 760 int gpio; 761 762 if (!pchip) 763 return 0; 764 765 for_each_gpio_bank(gpio, c, pchip) { 766 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 767 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 768 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 769 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 770 771 /* Clear GPIO transition detect bits */ 772 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 773 } 774 return 0; 775 } 776 777 static void pxa_gpio_resume(void) 778 { 779 struct pxa_gpio_chip *pchip = pxa_gpio_chip; 780 struct pxa_gpio_bank *c; 781 int gpio; 782 783 if (!pchip) 784 return; 785 786 for_each_gpio_bank(gpio, c, pchip) { 787 /* restore level with set/clear */ 788 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET); 789 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 790 791 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 792 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 793 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 794 } 795 } 796 #else 797 #define pxa_gpio_suspend NULL 798 #define pxa_gpio_resume NULL 799 #endif 800 801 static struct syscore_ops pxa_gpio_syscore_ops = { 802 .suspend = pxa_gpio_suspend, 803 .resume = pxa_gpio_resume, 804 }; 805 806 static int __init pxa_gpio_sysinit(void) 807 { 808 register_syscore_ops(&pxa_gpio_syscore_ops); 809 return 0; 810 } 811 postcore_initcall(pxa_gpio_sysinit); 812