1 /* 2 * linux/arch/arm/plat-pxa/gpio.c 3 * 4 * Generic PXA GPIO handling 5 * 6 * Author: Nicolas Pitre 7 * Created: Jun 15, 2001 8 * Copyright: MontaVista Software Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/gpio.h> 18 #include <linux/gpio-pxa.h> 19 #include <linux/init.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/io.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/syscore_ops.h> 27 #include <linux/slab.h> 28 29 #include <mach/irqs.h> 30 31 /* 32 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with 33 * one set of registers. The register offsets are organized below: 34 * 35 * GPLR GPDR GPSR GPCR GRER GFER GEDR 36 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 37 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C 38 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 39 * 40 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 41 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C 42 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 43 * 44 * NOTE: 45 * BANK 3 is only available on PXA27x and later processors. 46 * BANK 4 and 5 are only available on PXA935 47 */ 48 49 #define GPLR_OFFSET 0x00 50 #define GPDR_OFFSET 0x0C 51 #define GPSR_OFFSET 0x18 52 #define GPCR_OFFSET 0x24 53 #define GRER_OFFSET 0x30 54 #define GFER_OFFSET 0x3C 55 #define GEDR_OFFSET 0x48 56 #define GAFR_OFFSET 0x54 57 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */ 58 59 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) 60 61 int pxa_last_gpio; 62 63 #ifdef CONFIG_OF 64 static struct irq_domain *domain; 65 #endif 66 67 struct pxa_gpio_chip { 68 struct gpio_chip chip; 69 void __iomem *regbase; 70 char label[10]; 71 72 unsigned long irq_mask; 73 unsigned long irq_edge_rise; 74 unsigned long irq_edge_fall; 75 int (*set_wake)(unsigned int gpio, unsigned int on); 76 77 #ifdef CONFIG_PM 78 unsigned long saved_gplr; 79 unsigned long saved_gpdr; 80 unsigned long saved_grer; 81 unsigned long saved_gfer; 82 #endif 83 }; 84 85 enum { 86 PXA25X_GPIO = 0, 87 PXA26X_GPIO, 88 PXA27X_GPIO, 89 PXA3XX_GPIO, 90 PXA93X_GPIO, 91 MMP_GPIO = 0x10, 92 }; 93 94 static DEFINE_SPINLOCK(gpio_lock); 95 static struct pxa_gpio_chip *pxa_gpio_chips; 96 static int gpio_type; 97 static void __iomem *gpio_reg_base; 98 99 #define for_each_gpio_chip(i, c) \ 100 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) 101 102 static inline void __iomem *gpio_chip_base(struct gpio_chip *c) 103 { 104 return container_of(c, struct pxa_gpio_chip, chip)->regbase; 105 } 106 107 static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio) 108 { 109 return &pxa_gpio_chips[gpio_to_bank(gpio)]; 110 } 111 112 static inline int gpio_is_pxa_type(int type) 113 { 114 return (type & MMP_GPIO) == 0; 115 } 116 117 static inline int gpio_is_mmp_type(int type) 118 { 119 return (type & MMP_GPIO) != 0; 120 } 121 122 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted, 123 * as well as their Alternate Function value being '1' for GPIO in GAFRx. 124 */ 125 static inline int __gpio_is_inverted(int gpio) 126 { 127 if ((gpio_type == PXA26X_GPIO) && (gpio > 85)) 128 return 1; 129 return 0; 130 } 131 132 /* 133 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate 134 * function of a GPIO, and GPDRx cannot be altered once configured. It 135 * is attributed as "occupied" here (I know this terminology isn't 136 * accurate, you are welcome to propose a better one :-) 137 */ 138 static inline int __gpio_is_occupied(unsigned gpio) 139 { 140 struct pxa_gpio_chip *pxachip; 141 void __iomem *base; 142 unsigned long gafr = 0, gpdr = 0; 143 int ret, af = 0, dir = 0; 144 145 pxachip = gpio_to_pxachip(gpio); 146 base = gpio_chip_base(&pxachip->chip); 147 gpdr = readl_relaxed(base + GPDR_OFFSET); 148 149 switch (gpio_type) { 150 case PXA25X_GPIO: 151 case PXA26X_GPIO: 152 case PXA27X_GPIO: 153 gafr = readl_relaxed(base + GAFR_OFFSET); 154 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3; 155 dir = gpdr & GPIO_bit(gpio); 156 157 if (__gpio_is_inverted(gpio)) 158 ret = (af != 1) || (dir == 0); 159 else 160 ret = (af != 0) || (dir != 0); 161 break; 162 default: 163 ret = gpdr & GPIO_bit(gpio); 164 break; 165 } 166 return ret; 167 } 168 169 #ifdef CONFIG_ARCH_PXA 170 static inline int __pxa_gpio_to_irq(int gpio) 171 { 172 if (gpio_is_pxa_type(gpio_type)) 173 return PXA_GPIO_TO_IRQ(gpio); 174 return -1; 175 } 176 177 static inline int __pxa_irq_to_gpio(int irq) 178 { 179 if (gpio_is_pxa_type(gpio_type)) 180 return irq - PXA_GPIO_TO_IRQ(0); 181 return -1; 182 } 183 #else 184 static inline int __pxa_gpio_to_irq(int gpio) { return -1; } 185 static inline int __pxa_irq_to_gpio(int irq) { return -1; } 186 #endif 187 188 #ifdef CONFIG_ARCH_MMP 189 static inline int __mmp_gpio_to_irq(int gpio) 190 { 191 if (gpio_is_mmp_type(gpio_type)) 192 return MMP_GPIO_TO_IRQ(gpio); 193 return -1; 194 } 195 196 static inline int __mmp_irq_to_gpio(int irq) 197 { 198 if (gpio_is_mmp_type(gpio_type)) 199 return irq - MMP_GPIO_TO_IRQ(0); 200 return -1; 201 } 202 #else 203 static inline int __mmp_gpio_to_irq(int gpio) { return -1; } 204 static inline int __mmp_irq_to_gpio(int irq) { return -1; } 205 #endif 206 207 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 208 { 209 int gpio, ret; 210 211 gpio = chip->base + offset; 212 ret = __pxa_gpio_to_irq(gpio); 213 if (ret >= 0) 214 return ret; 215 return __mmp_gpio_to_irq(gpio); 216 } 217 218 int pxa_irq_to_gpio(int irq) 219 { 220 int ret; 221 222 ret = __pxa_irq_to_gpio(irq); 223 if (ret >= 0) 224 return ret; 225 return __mmp_irq_to_gpio(irq); 226 } 227 228 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 229 { 230 void __iomem *base = gpio_chip_base(chip); 231 uint32_t value, mask = 1 << offset; 232 unsigned long flags; 233 234 spin_lock_irqsave(&gpio_lock, flags); 235 236 value = readl_relaxed(base + GPDR_OFFSET); 237 if (__gpio_is_inverted(chip->base + offset)) 238 value |= mask; 239 else 240 value &= ~mask; 241 writel_relaxed(value, base + GPDR_OFFSET); 242 243 spin_unlock_irqrestore(&gpio_lock, flags); 244 return 0; 245 } 246 247 static int pxa_gpio_direction_output(struct gpio_chip *chip, 248 unsigned offset, int value) 249 { 250 void __iomem *base = gpio_chip_base(chip); 251 uint32_t tmp, mask = 1 << offset; 252 unsigned long flags; 253 254 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); 255 256 spin_lock_irqsave(&gpio_lock, flags); 257 258 tmp = readl_relaxed(base + GPDR_OFFSET); 259 if (__gpio_is_inverted(chip->base + offset)) 260 tmp &= ~mask; 261 else 262 tmp |= mask; 263 writel_relaxed(tmp, base + GPDR_OFFSET); 264 265 spin_unlock_irqrestore(&gpio_lock, flags); 266 return 0; 267 } 268 269 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) 270 { 271 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); 272 } 273 274 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 275 { 276 writel_relaxed(1 << offset, gpio_chip_base(chip) + 277 (value ? GPSR_OFFSET : GPCR_OFFSET)); 278 } 279 280 static int __devinit pxa_init_gpio_chip(int gpio_end, 281 int (*set_wake)(unsigned int, unsigned int)) 282 { 283 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; 284 struct pxa_gpio_chip *chips; 285 286 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL); 287 if (chips == NULL) { 288 pr_err("%s: failed to allocate GPIO chips\n", __func__); 289 return -ENOMEM; 290 } 291 292 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { 293 struct gpio_chip *c = &chips[i].chip; 294 295 sprintf(chips[i].label, "gpio-%d", i); 296 chips[i].regbase = gpio_reg_base + BANK_OFF(i); 297 chips[i].set_wake = set_wake; 298 299 c->base = gpio; 300 c->label = chips[i].label; 301 302 c->direction_input = pxa_gpio_direction_input; 303 c->direction_output = pxa_gpio_direction_output; 304 c->get = pxa_gpio_get; 305 c->set = pxa_gpio_set; 306 c->to_irq = pxa_gpio_to_irq; 307 308 /* number of GPIOs on last bank may be less than 32 */ 309 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; 310 gpiochip_add(c); 311 } 312 pxa_gpio_chips = chips; 313 return 0; 314 } 315 316 /* Update only those GRERx and GFERx edge detection register bits if those 317 * bits are set in c->irq_mask 318 */ 319 static inline void update_edge_detect(struct pxa_gpio_chip *c) 320 { 321 uint32_t grer, gfer; 322 323 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; 324 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; 325 grer |= c->irq_edge_rise & c->irq_mask; 326 gfer |= c->irq_edge_fall & c->irq_mask; 327 writel_relaxed(grer, c->regbase + GRER_OFFSET); 328 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 329 } 330 331 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type) 332 { 333 struct pxa_gpio_chip *c; 334 int gpio = pxa_irq_to_gpio(d->irq); 335 unsigned long gpdr, mask = GPIO_bit(gpio); 336 337 c = gpio_to_pxachip(gpio); 338 339 if (type == IRQ_TYPE_PROBE) { 340 /* Don't mess with enabled GPIOs using preconfigured edges or 341 * GPIOs set to alternate function or to output during probe 342 */ 343 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) 344 return 0; 345 346 if (__gpio_is_occupied(gpio)) 347 return 0; 348 349 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 350 } 351 352 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 353 354 if (__gpio_is_inverted(gpio)) 355 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET); 356 else 357 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET); 358 359 if (type & IRQ_TYPE_EDGE_RISING) 360 c->irq_edge_rise |= mask; 361 else 362 c->irq_edge_rise &= ~mask; 363 364 if (type & IRQ_TYPE_EDGE_FALLING) 365 c->irq_edge_fall |= mask; 366 else 367 c->irq_edge_fall &= ~mask; 368 369 update_edge_detect(c); 370 371 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio, 372 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), 373 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); 374 return 0; 375 } 376 377 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) 378 { 379 struct pxa_gpio_chip *c; 380 int loop, gpio, gpio_base, n; 381 unsigned long gedr; 382 383 do { 384 loop = 0; 385 for_each_gpio_chip(gpio, c) { 386 gpio_base = c->chip.base; 387 388 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); 389 gedr = gedr & c->irq_mask; 390 writel_relaxed(gedr, c->regbase + GEDR_OFFSET); 391 392 n = find_first_bit(&gedr, BITS_PER_LONG); 393 while (n < BITS_PER_LONG) { 394 loop = 1; 395 396 generic_handle_irq(gpio_to_irq(gpio_base + n)); 397 n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); 398 } 399 } 400 } while (loop); 401 } 402 403 static void pxa_ack_muxed_gpio(struct irq_data *d) 404 { 405 int gpio = pxa_irq_to_gpio(d->irq); 406 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 407 408 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); 409 } 410 411 static void pxa_mask_muxed_gpio(struct irq_data *d) 412 { 413 int gpio = pxa_irq_to_gpio(d->irq); 414 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 415 uint32_t grer, gfer; 416 417 c->irq_mask &= ~GPIO_bit(gpio); 418 419 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); 420 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); 421 writel_relaxed(grer, c->regbase + GRER_OFFSET); 422 writel_relaxed(gfer, c->regbase + GFER_OFFSET); 423 } 424 425 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on) 426 { 427 int gpio = pxa_irq_to_gpio(d->irq); 428 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 429 430 if (c->set_wake) 431 return c->set_wake(gpio, on); 432 else 433 return 0; 434 } 435 436 static void pxa_unmask_muxed_gpio(struct irq_data *d) 437 { 438 int gpio = pxa_irq_to_gpio(d->irq); 439 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio); 440 441 c->irq_mask |= GPIO_bit(gpio); 442 update_edge_detect(c); 443 } 444 445 static struct irq_chip pxa_muxed_gpio_chip = { 446 .name = "GPIO", 447 .irq_ack = pxa_ack_muxed_gpio, 448 .irq_mask = pxa_mask_muxed_gpio, 449 .irq_unmask = pxa_unmask_muxed_gpio, 450 .irq_set_type = pxa_gpio_irq_type, 451 .irq_set_wake = pxa_gpio_set_wake, 452 }; 453 454 static int pxa_gpio_nums(void) 455 { 456 int count = 0; 457 458 #ifdef CONFIG_ARCH_PXA 459 if (cpu_is_pxa25x()) { 460 #ifdef CONFIG_CPU_PXA26x 461 count = 89; 462 gpio_type = PXA26X_GPIO; 463 #elif defined(CONFIG_PXA25x) 464 count = 84; 465 gpio_type = PXA26X_GPIO; 466 #endif /* CONFIG_CPU_PXA26x */ 467 } else if (cpu_is_pxa27x()) { 468 count = 120; 469 gpio_type = PXA27X_GPIO; 470 } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) { 471 count = 191; 472 gpio_type = PXA93X_GPIO; 473 } else if (cpu_is_pxa3xx()) { 474 count = 127; 475 gpio_type = PXA3XX_GPIO; 476 } 477 #endif /* CONFIG_ARCH_PXA */ 478 479 #ifdef CONFIG_ARCH_MMP 480 if (cpu_is_pxa168() || cpu_is_pxa910()) { 481 count = 127; 482 gpio_type = MMP_GPIO; 483 } else if (cpu_is_mmp2()) { 484 count = 191; 485 gpio_type = MMP_GPIO; 486 } 487 #endif /* CONFIG_ARCH_MMP */ 488 return count; 489 } 490 491 static struct of_device_id pxa_gpio_dt_ids[] = { 492 { .compatible = "mrvl,pxa-gpio" }, 493 { .compatible = "mrvl,mmp-gpio", .data = (void *)MMP_GPIO }, 494 {} 495 }; 496 497 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq, 498 irq_hw_number_t hw) 499 { 500 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 501 handle_edge_irq); 502 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 503 return 0; 504 } 505 506 const struct irq_domain_ops pxa_irq_domain_ops = { 507 .map = pxa_irq_domain_map, 508 }; 509 510 #ifdef CONFIG_OF 511 static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev) 512 { 513 int ret, nr_banks, nr_gpios, irq_base; 514 struct device_node *prev, *next, *np = pdev->dev.of_node; 515 const struct of_device_id *of_id = 516 of_match_device(pxa_gpio_dt_ids, &pdev->dev); 517 518 if (!of_id) { 519 dev_err(&pdev->dev, "Failed to find gpio controller\n"); 520 return -EFAULT; 521 } 522 gpio_type = (int)of_id->data; 523 524 next = of_get_next_child(np, NULL); 525 prev = next; 526 if (!next) { 527 dev_err(&pdev->dev, "Failed to find child gpio node\n"); 528 ret = -EINVAL; 529 goto err; 530 } 531 for (nr_banks = 1; ; nr_banks++) { 532 next = of_get_next_child(np, prev); 533 if (!next) 534 break; 535 prev = next; 536 } 537 of_node_put(prev); 538 nr_gpios = nr_banks << 5; 539 pxa_last_gpio = nr_gpios - 1; 540 541 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0); 542 if (irq_base < 0) { 543 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); 544 goto err; 545 } 546 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0, 547 &pxa_irq_domain_ops, NULL); 548 return 0; 549 err: 550 iounmap(gpio_reg_base); 551 return ret; 552 } 553 #else 554 #define pxa_gpio_probe_dt(pdev) (-1) 555 #endif 556 557 static int __devinit pxa_gpio_probe(struct platform_device *pdev) 558 { 559 struct pxa_gpio_chip *c; 560 struct resource *res; 561 struct clk *clk; 562 struct pxa_gpio_platform_data *info; 563 int gpio, irq, ret, use_of = 0; 564 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; 565 566 ret = pxa_gpio_probe_dt(pdev); 567 if (ret < 0) 568 pxa_last_gpio = pxa_gpio_nums(); 569 else 570 use_of = 1; 571 if (!pxa_last_gpio) 572 return -EINVAL; 573 574 irq0 = platform_get_irq_byname(pdev, "gpio0"); 575 irq1 = platform_get_irq_byname(pdev, "gpio1"); 576 irq_mux = platform_get_irq_byname(pdev, "gpio_mux"); 577 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0) 578 || (irq_mux <= 0)) 579 return -EINVAL; 580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 581 if (!res) 582 return -EINVAL; 583 gpio_reg_base = ioremap(res->start, resource_size(res)); 584 if (!gpio_reg_base) 585 return -EINVAL; 586 587 if (irq0 > 0) 588 gpio_offset = 2; 589 590 clk = clk_get(&pdev->dev, NULL); 591 if (IS_ERR(clk)) { 592 dev_err(&pdev->dev, "Error %ld to get gpio clock\n", 593 PTR_ERR(clk)); 594 iounmap(gpio_reg_base); 595 return PTR_ERR(clk); 596 } 597 ret = clk_prepare(clk); 598 if (ret) { 599 clk_put(clk); 600 iounmap(gpio_reg_base); 601 return ret; 602 } 603 ret = clk_enable(clk); 604 if (ret) { 605 clk_unprepare(clk); 606 clk_put(clk); 607 iounmap(gpio_reg_base); 608 return ret; 609 } 610 611 /* Initialize GPIO chips */ 612 info = dev_get_platdata(&pdev->dev); 613 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL); 614 615 /* clear all GPIO edge detects */ 616 for_each_gpio_chip(gpio, c) { 617 writel_relaxed(0, c->regbase + GFER_OFFSET); 618 writel_relaxed(0, c->regbase + GRER_OFFSET); 619 writel_relaxed(~0,c->regbase + GEDR_OFFSET); 620 /* unmask GPIO edge detect for AP side */ 621 if (gpio_is_mmp_type(gpio_type)) 622 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET); 623 } 624 625 if (!use_of) { 626 #ifdef CONFIG_ARCH_PXA 627 irq = gpio_to_irq(0); 628 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 629 handle_edge_irq); 630 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 631 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler); 632 633 irq = gpio_to_irq(1); 634 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 635 handle_edge_irq); 636 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 637 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler); 638 #endif 639 640 for (irq = gpio_to_irq(gpio_offset); 641 irq <= gpio_to_irq(pxa_last_gpio); irq++) { 642 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip, 643 handle_edge_irq); 644 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 645 } 646 } 647 648 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler); 649 return 0; 650 } 651 652 static struct platform_driver pxa_gpio_driver = { 653 .probe = pxa_gpio_probe, 654 .driver = { 655 .name = "pxa-gpio", 656 .of_match_table = pxa_gpio_dt_ids, 657 }, 658 }; 659 660 static int __init pxa_gpio_init(void) 661 { 662 return platform_driver_register(&pxa_gpio_driver); 663 } 664 postcore_initcall(pxa_gpio_init); 665 666 #ifdef CONFIG_PM 667 static int pxa_gpio_suspend(void) 668 { 669 struct pxa_gpio_chip *c; 670 int gpio; 671 672 for_each_gpio_chip(gpio, c) { 673 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET); 674 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); 675 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET); 676 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET); 677 678 /* Clear GPIO transition detect bits */ 679 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET); 680 } 681 return 0; 682 } 683 684 static void pxa_gpio_resume(void) 685 { 686 struct pxa_gpio_chip *c; 687 int gpio; 688 689 for_each_gpio_chip(gpio, c) { 690 /* restore level with set/clear */ 691 writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET); 692 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET); 693 694 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET); 695 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET); 696 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET); 697 } 698 } 699 #else 700 #define pxa_gpio_suspend NULL 701 #define pxa_gpio_resume NULL 702 #endif 703 704 struct syscore_ops pxa_gpio_syscore_ops = { 705 .suspend = pxa_gpio_suspend, 706 .resume = pxa_gpio_resume, 707 }; 708 709 static int __init pxa_gpio_sysinit(void) 710 { 711 register_syscore_ops(&pxa_gpio_syscore_ops); 712 return 0; 713 } 714 postcore_initcall(pxa_gpio_sysinit); 715